* [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ
@ 2020-01-14 11:31 chen gong
2020-01-14 11:31 ` [PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32 chen gong
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: chen gong @ 2020-01-14 11:31 UTC (permalink / raw)
To: amd-gfx; +Cc: chen gong
Move amdgpu_virt_kiq_rreg function to amdgpu_device.c, and rename it to
amdgpu_kiq_rreg.Make it generic and flexible。
Signed-off-by: chen gong <curry.gong@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 +++++++++++++++++++++++++++++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 46 ---------------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 -
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 +--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +--
9 files changed, 62 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 63eab0c..32bb883 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1009,7 +1009,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
int emu_soc_asic_init(struct amdgpu_device *adev);
-
+uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
/*
* Registers read & write functions.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2c64d2a..1d076c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -170,6 +170,53 @@ bool amdgpu_device_supports_baco(struct drm_device *dev)
return amdgpu_asic_supports_baco(adev);
}
+
+uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
+{
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+ struct amdgpu_ring *ring = &kiq->ring;
+
+ BUG_ON(!ring->funcs->emit_rreg);
+
+ spin_lock_irqsave(&kiq->ring_lock, flags);
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_emit_rreg(ring, reg);
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
+
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+ /* don't wait anymore for gpu reset case because this way may
+ * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
+ * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
+ * never return if we keep waiting in virt_kiq_rreg, which cause
+ * gpu_recover() hang there.
+ *
+ * also don't wait anymore for IRQ context
+ * */
+ if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+ goto failed_kiq_read;
+
+ might_sleep();
+ while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
+ msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+ }
+
+ if (cnt > MAX_KIQ_REG_TRY)
+ goto failed_kiq_read;
+
+ return adev->wb.wb[kiq->reg_val_offs];
+
+failed_kiq_read:
+ pr_err("failed to read reg:%x\n", reg);
+ return ~0;
+}
+
/**
* VRAM access helper functions.
*
@@ -218,7 +265,7 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
uint32_t ret;
if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
- return amdgpu_virt_kiq_rreg(adev, reg);
+ return amdgpu_kiq_rreg(adev, reg);
if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
@@ -276,6 +323,7 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
BUG();
}
+
/**
* amdgpu_mm_wreg - write to a memory mapped IO register
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index b88b8b8..f437767 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -296,7 +296,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
spin_lock_init(&kiq->ring_lock);
- r = amdgpu_device_wb_get(adev, &adev->virt.reg_val_offs);
+ r = amdgpu_device_wb_get(adev, &kiq->reg_val_offs);
if (r)
return r;
@@ -321,7 +321,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
{
- amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
+ amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs);
amdgpu_ring_fini(ring);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index af4bd27..2364964 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -94,6 +94,7 @@ struct amdgpu_kiq {
struct amdgpu_ring ring;
struct amdgpu_irq_src irq;
const struct kiq_pm4_funcs *pmf;
+ uint32_t reg_val_offs;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 103033f..040a3809 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -45,52 +45,6 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
adev->pg_flags = 0;
}
-uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
-{
- signed long r, cnt = 0;
- unsigned long flags;
- uint32_t seq;
- struct amdgpu_kiq *kiq = &adev->gfx.kiq;
- struct amdgpu_ring *ring = &kiq->ring;
-
- BUG_ON(!ring->funcs->emit_rreg);
-
- spin_lock_irqsave(&kiq->ring_lock, flags);
- amdgpu_ring_alloc(ring, 32);
- amdgpu_ring_emit_rreg(ring, reg);
- amdgpu_fence_emit_polling(ring, &seq);
- amdgpu_ring_commit(ring);
- spin_unlock_irqrestore(&kiq->ring_lock, flags);
-
- r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
-
- /* don't wait anymore for gpu reset case because this way may
- * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
- * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
- * never return if we keep waiting in virt_kiq_rreg, which cause
- * gpu_recover() hang there.
- *
- * also don't wait anymore for IRQ context
- * */
- if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
- goto failed_kiq_read;
-
- might_sleep();
- while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
- msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
- r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
- }
-
- if (cnt > MAX_KIQ_REG_TRY)
- goto failed_kiq_read;
-
- return adev->wb.wb[adev->virt.reg_val_offs];
-
-failed_kiq_read:
- pr_err("failed to read reg:%x\n", reg);
- return ~0;
-}
-
void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
{
signed long r, cnt = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 4d1ac76..f356f68 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -287,7 +287,6 @@ static inline bool is_virtual_machine(void)
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
void amdgpu_virt_init_setting(struct amdgpu_device *adev);
-uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
uint32_t reg0, uint32_t rreg1,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d72b60f..353ecef 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4743,6 +4743,7 @@ static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
{
struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_kiq *kiq = &adev->gfx.kiq;
amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
amdgpu_ring_write(ring, 0 | /* src: register*/
@@ -4751,9 +4752,9 @@ static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
amdgpu_ring_write(ring, reg);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
- adev->virt.reg_val_offs * 4));
+ kiq->reg_val_offs * 4));
amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
- adev->virt.reg_val_offs * 4));
+ kiq->reg_val_offs * 4));
}
static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 8b9f440..d6dd8a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6447,6 +6447,7 @@ static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
{
struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_kiq *kiq = &adev->gfx.kiq;
amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
amdgpu_ring_write(ring, 0 | /* src: register*/
@@ -6455,9 +6456,9 @@ static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
amdgpu_ring_write(ring, reg);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
- adev->virt.reg_val_offs * 4));
+ kiq->reg_val_offs * 4));
amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
- adev->virt.reg_val_offs * 4));
+ kiq->reg_val_offs * 4));
}
static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 44cdb6f..425762a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5218,6 +5218,7 @@ static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
{
struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_kiq *kiq = &adev->gfx.kiq;
amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
amdgpu_ring_write(ring, 0 | /* src: register*/
@@ -5226,9 +5227,9 @@ static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
amdgpu_ring_write(ring, reg);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
- adev->virt.reg_val_offs * 4));
+ kiq->reg_val_offs * 4));
amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
- adev->virt.reg_val_offs * 4));
+ kiq->reg_val_offs * 4));
}
static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32
2020-01-14 11:31 [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ chen gong
@ 2020-01-14 11:31 ` chen gong
2020-01-14 14:39 ` Alex Deucher
2020-01-14 11:31 ` [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro chen gong
2020-01-14 14:38 ` [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ Alex Deucher
2 siblings, 1 reply; 7+ messages in thread
From: chen gong @ 2020-01-14 11:31 UTC (permalink / raw)
To: amd-gfx; +Cc: chen gong
Reading some registers by mmio will result in hang when GPU is in
"gfxoff" state.
This problem can be solved by GPU in "ring command packages" way.
Signed-off-by: chen gong <curry.gong@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 32bb883..90f148a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1016,10 +1016,13 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
#define AMDGPU_REGS_IDX (1<<0)
#define AMDGPU_REGS_NO_KIQ (1<<1)
+#define AMDGPU_REGS_KIQ (1<<2)
#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
+#define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ)
+
#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1d076c0..1fceeb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -264,7 +264,7 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
{
uint32_t ret;
- if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
+ if ((acc_flags & AMDGPU_REGS_KIQ) || (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)))
return amdgpu_kiq_rreg(adev, reg);
if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32
2020-01-14 11:31 ` [PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32 chen gong
@ 2020-01-14 14:39 ` Alex Deucher
0 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2020-01-14 14:39 UTC (permalink / raw)
To: chen gong; +Cc: amd-gfx list
On Tue, Jan 14, 2020 at 6:43 AM chen gong <curry.gong@amd.com> wrote:
>
> Reading some registers by mmio will result in hang when GPU is in
> "gfxoff" state.
>
> This problem can be solved by GPU in "ring command packages" way.
>
> Signed-off-by: chen gong <curry.gong@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 32bb883..90f148a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1016,10 +1016,13 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
>
> #define AMDGPU_REGS_IDX (1<<0)
> #define AMDGPU_REGS_NO_KIQ (1<<1)
> +#define AMDGPU_REGS_KIQ (1<<2)
>
> #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
> #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
>
> +#define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ)
Please add a WREG32_KIQ helper as well.
Alex
> +
> #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
> #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 1d076c0..1fceeb2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -264,7 +264,7 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> {
> uint32_t ret;
>
> - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
> + if ((acc_flags & AMDGPU_REGS_KIQ) || (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)))
> return amdgpu_kiq_rreg(adev, reg);
>
> if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro
2020-01-14 11:31 [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ chen gong
2020-01-14 11:31 ` [PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32 chen gong
@ 2020-01-14 11:31 ` chen gong
2020-01-14 14:39 ` Alex Deucher
2020-01-14 14:38 ` [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ Alex Deucher
2 siblings, 1 reply; 7+ messages in thread
From: chen gong @ 2020-01-14 11:31 UTC (permalink / raw)
To: amd-gfx; +Cc: chen gong
Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to
hang when GPU is in "gfxoff" state.
I do a uniform substitution here.
Signed-off-by: chen gong <curry.gong@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 425762a..cdafacc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4714,12 +4714,12 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
*flags = 0;
/* AMD_CG_SUPPORT_GFX_MGCG */
- data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
+ data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
*flags |= AMD_CG_SUPPORT_GFX_MGCG;
/* AMD_CG_SUPPORT_GFX_CGCG */
- data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
+ data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
*flags |= AMD_CG_SUPPORT_GFX_CGCG;
@@ -4728,18 +4728,18 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
*flags |= AMD_CG_SUPPORT_GFX_CGLS;
/* AMD_CG_SUPPORT_GFX_RLC_LS */
- data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
+ data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
/* AMD_CG_SUPPORT_GFX_CP_LS */
- data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
+ data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
if (adev->asic_type != CHIP_ARCTURUS) {
/* AMD_CG_SUPPORT_GFX_3D_CGCG */
- data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
+ data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro
2020-01-14 11:31 ` [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro chen gong
@ 2020-01-14 14:39 ` Alex Deucher
2020-01-15 10:01 ` Gong, Curry
0 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2020-01-14 14:39 UTC (permalink / raw)
To: chen gong; +Cc: amd-gfx list
(On Tue, Jan 14, 2020 at 6:42 AM chen gong <curry.gong@amd.com> wrote:
>
> Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to
> hang when GPU is in "gfxoff" state.
> I do a uniform substitution here.
>
> Signed-off-by: chen gong <curry.gong@amd.com>
Alternatively, we could wrap this function with amdgpu_gfx_off_ctrl()
like we do for the AMDGPU_INFO_READ_MMR_REG. Maybe it would be better
to convert the amdgpu_asic_read_register() callbacks to use KIQ as
well? That can be something to look at in the future.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 425762a..cdafacc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4714,12 +4714,12 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
> *flags = 0;
>
> /* AMD_CG_SUPPORT_GFX_MGCG */
> - data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
> if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
> *flags |= AMD_CG_SUPPORT_GFX_MGCG;
>
> /* AMD_CG_SUPPORT_GFX_CGCG */
> - data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
> if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_CGCG;
>
> @@ -4728,18 +4728,18 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
> *flags |= AMD_CG_SUPPORT_GFX_CGLS;
>
> /* AMD_CG_SUPPORT_GFX_RLC_LS */
> - data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
> if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
>
> /* AMD_CG_SUPPORT_GFX_CP_LS */
> - data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
> if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
>
> if (adev->asic_type != CHIP_ARCTURUS) {
> /* AMD_CG_SUPPORT_GFX_3D_CGCG */
> - data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
> if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro
2020-01-14 14:39 ` Alex Deucher
@ 2020-01-15 10:01 ` Gong, Curry
0 siblings, 0 replies; 7+ messages in thread
From: Gong, Curry @ 2020-01-15 10:01 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
[AMD Official Use Only - Internal Distribution Only]
Hi Alex:
Thank you for your comments.
'convert the amdgpu_asic_read_register() callbacks to use KIQ' is a good suggestion. It is something to look at in the future.
BR
Curry Gong
-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Tuesday, January 14, 2020 10:40 PM
To: Gong, Curry <Curry.Gong@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro
(On Tue, Jan 14, 2020 at 6:42 AM chen gong <curry.gong@amd.com> wrote:
>
> Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to
> hang when GPU is in "gfxoff" state.
> I do a uniform substitution here.
>
> Signed-off-by: chen gong <curry.gong@amd.com>
Alternatively, we could wrap this function with amdgpu_gfx_off_ctrl() like we do for the AMDGPU_INFO_READ_MMR_REG. Maybe it would be better to convert the amdgpu_asic_read_register() callbacks to use KIQ as well? That can be something to look at in the future.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 425762a..cdafacc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4714,12 +4714,12 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
> *flags = 0;
>
> /* AMD_CG_SUPPORT_GFX_MGCG */
> - data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0,
> + mmRLC_CGTT_MGCG_OVERRIDE));
> if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
> *flags |= AMD_CG_SUPPORT_GFX_MGCG;
>
> /* AMD_CG_SUPPORT_GFX_CGCG */
> - data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0,
> + mmRLC_CGCG_CGLS_CTRL));
> if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_CGCG;
>
> @@ -4728,18 +4728,18 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
> *flags |= AMD_CG_SUPPORT_GFX_CGLS;
>
> /* AMD_CG_SUPPORT_GFX_RLC_LS */
> - data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0,
> + mmRLC_MEM_SLP_CNTL));
> if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_RLC_LS |
> AMD_CG_SUPPORT_GFX_MGLS;
>
> /* AMD_CG_SUPPORT_GFX_CP_LS */
> - data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
> if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_CP_LS |
> AMD_CG_SUPPORT_GFX_MGLS;
>
> if (adev->asic_type != CHIP_ARCTURUS) {
> /* AMD_CG_SUPPORT_GFX_3D_CGCG */
> - data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0,
> + mmRLC_CGCG_CGLS_CTRL_3D));
> if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Ccu
> rry.gong%40amd.com%7Ca53ec98e6f2848143fd308d798ff9e89%7C3dd8961fe4884e
> 608e11a82d994e183d%7C0%7C0%7C637146095959110200&sdata=zbCMK3WYn%2F
> nWZol8IO3cA1EvGefPpD7WzAchoA9A%2B1A%3D&reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ
2020-01-14 11:31 [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ chen gong
2020-01-14 11:31 ` [PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32 chen gong
2020-01-14 11:31 ` [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro chen gong
@ 2020-01-14 14:38 ` Alex Deucher
2 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2020-01-14 14:38 UTC (permalink / raw)
To: chen gong; +Cc: amd-gfx list
On Tue, Jan 14, 2020 at 6:42 AM chen gong <curry.gong@amd.com> wrote:
>
> Move amdgpu_virt_kiq_rreg function to amdgpu_device.c, and rename it to
> amdgpu_kiq_rreg.Make it generic and flexible。
>
> Signed-off-by: chen gong <curry.gong@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 +++++++++++++++++++++++++++++-
Please use amdgpu_kiq.c or amdgpu_gfx.c for the KIQ helpers rather
than adding them to amdgpu_device.c. Also for symmetry, please move
the kiq wreg helper as well.
Alex
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 +--
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 46 ---------------------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 -
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +--
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 +--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +--
> 9 files changed, 62 insertions(+), 57 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 63eab0c..32bb883 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1009,7 +1009,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
> bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
>
> int emu_soc_asic_init(struct amdgpu_device *adev);
> -
> +uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
> /*
> * Registers read & write functions.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 2c64d2a..1d076c0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -170,6 +170,53 @@ bool amdgpu_device_supports_baco(struct drm_device *dev)
> return amdgpu_asic_supports_baco(adev);
> }
>
> +
> +uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
> +{
> + signed long r, cnt = 0;
> + unsigned long flags;
> + uint32_t seq;
> + struct amdgpu_kiq *kiq = &adev->gfx.kiq;
> + struct amdgpu_ring *ring = &kiq->ring;
> +
> + BUG_ON(!ring->funcs->emit_rreg);
> +
> + spin_lock_irqsave(&kiq->ring_lock, flags);
> + amdgpu_ring_alloc(ring, 32);
> + amdgpu_ring_emit_rreg(ring, reg);
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> +
> + /* don't wait anymore for gpu reset case because this way may
> + * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
> + * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
> + * never return if we keep waiting in virt_kiq_rreg, which cause
> + * gpu_recover() hang there.
> + *
> + * also don't wait anymore for IRQ context
> + * */
> + if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
> + goto failed_kiq_read;
> +
> + might_sleep();
> + while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
> + msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
> + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> + }
> +
> + if (cnt > MAX_KIQ_REG_TRY)
> + goto failed_kiq_read;
> +
> + return adev->wb.wb[kiq->reg_val_offs];
> +
> +failed_kiq_read:
> + pr_err("failed to read reg:%x\n", reg);
> + return ~0;
> +}
> +
> /**
> * VRAM access helper functions.
> *
> @@ -218,7 +265,7 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> uint32_t ret;
>
> if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
> - return amdgpu_virt_kiq_rreg(adev, reg);
> + return amdgpu_kiq_rreg(adev, reg);
>
> if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
> ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
> @@ -276,6 +323,7 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
> BUG();
> }
>
> +
> /**
> * amdgpu_mm_wreg - write to a memory mapped IO register
> *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index b88b8b8..f437767 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -296,7 +296,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
>
> spin_lock_init(&kiq->ring_lock);
>
> - r = amdgpu_device_wb_get(adev, &adev->virt.reg_val_offs);
> + r = amdgpu_device_wb_get(adev, &kiq->reg_val_offs);
> if (r)
> return r;
>
> @@ -321,7 +321,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
>
> void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
> {
> - amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
> + amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs);
> amdgpu_ring_fini(ring);
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index af4bd27..2364964 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -94,6 +94,7 @@ struct amdgpu_kiq {
> struct amdgpu_ring ring;
> struct amdgpu_irq_src irq;
> const struct kiq_pm4_funcs *pmf;
> + uint32_t reg_val_offs;
> };
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 103033f..040a3809 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -45,52 +45,6 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
> adev->pg_flags = 0;
> }
>
> -uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
> -{
> - signed long r, cnt = 0;
> - unsigned long flags;
> - uint32_t seq;
> - struct amdgpu_kiq *kiq = &adev->gfx.kiq;
> - struct amdgpu_ring *ring = &kiq->ring;
> -
> - BUG_ON(!ring->funcs->emit_rreg);
> -
> - spin_lock_irqsave(&kiq->ring_lock, flags);
> - amdgpu_ring_alloc(ring, 32);
> - amdgpu_ring_emit_rreg(ring, reg);
> - amdgpu_fence_emit_polling(ring, &seq);
> - amdgpu_ring_commit(ring);
> - spin_unlock_irqrestore(&kiq->ring_lock, flags);
> -
> - r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> -
> - /* don't wait anymore for gpu reset case because this way may
> - * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
> - * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
> - * never return if we keep waiting in virt_kiq_rreg, which cause
> - * gpu_recover() hang there.
> - *
> - * also don't wait anymore for IRQ context
> - * */
> - if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
> - goto failed_kiq_read;
> -
> - might_sleep();
> - while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
> - msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
> - r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> - }
> -
> - if (cnt > MAX_KIQ_REG_TRY)
> - goto failed_kiq_read;
> -
> - return adev->wb.wb[adev->virt.reg_val_offs];
> -
> -failed_kiq_read:
> - pr_err("failed to read reg:%x\n", reg);
> - return ~0;
> -}
> -
> void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
> {
> signed long r, cnt = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 4d1ac76..f356f68 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -287,7 +287,6 @@ static inline bool is_virtual_machine(void)
>
> bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
> void amdgpu_virt_init_setting(struct amdgpu_device *adev);
> -uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
> void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
> void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
> uint32_t reg0, uint32_t rreg1,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index d72b60f..353ecef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4743,6 +4743,7 @@ static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
> static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
> {
> struct amdgpu_device *adev = ring->adev;
> + struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>
> amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
> amdgpu_ring_write(ring, 0 | /* src: register*/
> @@ -4751,9 +4752,9 @@ static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
> amdgpu_ring_write(ring, reg);
> amdgpu_ring_write(ring, 0);
> amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
> - adev->virt.reg_val_offs * 4));
> + kiq->reg_val_offs * 4));
> amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
> - adev->virt.reg_val_offs * 4));
> + kiq->reg_val_offs * 4));
> }
>
> static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 8b9f440..d6dd8a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6447,6 +6447,7 @@ static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
> static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
> {
> struct amdgpu_device *adev = ring->adev;
> + struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>
> amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
> amdgpu_ring_write(ring, 0 | /* src: register*/
> @@ -6455,9 +6456,9 @@ static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
> amdgpu_ring_write(ring, reg);
> amdgpu_ring_write(ring, 0);
> amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
> - adev->virt.reg_val_offs * 4));
> + kiq->reg_val_offs * 4));
> amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
> - adev->virt.reg_val_offs * 4));
> + kiq->reg_val_offs * 4));
> }
>
> static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 44cdb6f..425762a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -5218,6 +5218,7 @@ static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
> static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
> {
> struct amdgpu_device *adev = ring->adev;
> + struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>
> amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
> amdgpu_ring_write(ring, 0 | /* src: register*/
> @@ -5226,9 +5227,9 @@ static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
> amdgpu_ring_write(ring, reg);
> amdgpu_ring_write(ring, 0);
> amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
> - adev->virt.reg_val_offs * 4));
> + kiq->reg_val_offs * 4));
> amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
> - adev->virt.reg_val_offs * 4));
> + kiq->reg_val_offs * 4));
> }
>
> static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-01-15 10:01 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-14 11:31 [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ chen gong
2020-01-14 11:31 ` [PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32 chen gong
2020-01-14 14:39 ` Alex Deucher
2020-01-14 11:31 ` [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro chen gong
2020-01-14 14:39 ` Alex Deucher
2020-01-15 10:01 ` Gong, Curry
2020-01-14 14:38 ` [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ Alex Deucher
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