* [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3
@ 2020-02-14 14:50 Xiaojie Yuan
2020-02-14 14:50 ` [PATCH umr 2/2] print data values for WRITE_DATA packet Xiaojie Yuan
2020-02-14 14:55 ` [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3 Tom St Denis
0 siblings, 2 replies; 5+ messages in thread
From: Xiaojie Yuan @ 2020-02-14 14:50 UTC (permalink / raw)
To: amd-gfx, tom.stdenis; +Cc: Xiaojie Yuan
Fixes following error while dumping gfx ring:
[BUG]: reg [mmMM_INDEX] not found on asic [navi10]
[BUG]: reg [mmMM_INDEX_HI] not found on asic [navi10]
[BUG]: reg [mmMM_DATA] not found on asic [navi10]
Cannot read from system memory: Operation not permitted
[ERROR]: Accessing system memory returned: -1
Cannot read from system memory: Bad address
[ERROR]: Accessing system memory returned: -1
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
---
src/lib/ip/nbio230_bits.i | 6 +++---
src/lib/ip/nbio230_regs.i | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/lib/ip/nbio230_bits.i b/src/lib/ip/nbio230_bits.i
index 506ccba..fd5bad8 100644
--- a/src/lib/ip/nbio230_bits.i
+++ b/src/lib/ip/nbio230_bits.i
@@ -1,11 +1,11 @@
-static struct umr_bitfield mmBIF_BX_PF_MM_INDEX[] = {
+static struct umr_bitfield mmMM_INDEX[] = {
{ "MM_OFFSET", 0, 30, &umr_bitfield_default },
{ "MM_APER", 31, 31, &umr_bitfield_default },
};
-static struct umr_bitfield mmBIF_BX_PF_MM_DATA[] = {
+static struct umr_bitfield mmMM_DATA[] = {
{ "MM_DATA", 0, 31, &umr_bitfield_default },
};
-static struct umr_bitfield mmBIF_BX_PF_MM_INDEX_HI[] = {
+static struct umr_bitfield mmMM_INDEX_HI[] = {
{ "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSYSHUB_INDEX_OVLP[] = {
diff --git a/src/lib/ip/nbio230_regs.i b/src/lib/ip/nbio230_regs.i
index ab57385..27a644b 100644
--- a/src/lib/ip/nbio230_regs.i
+++ b/src/lib/ip/nbio230_regs.i
@@ -1,6 +1,6 @@
- { "mmBIF_BX_PF_MM_INDEX", REG_MMIO, 0x0000, 0, &mmBIF_BX_PF_MM_INDEX[0], sizeof(mmBIF_BX_PF_MM_INDEX)/sizeof(mmBIF_BX_PF_MM_INDEX[0]), 0, 0 },
- { "mmBIF_BX_PF_MM_DATA", REG_MMIO, 0x0001, 0, &mmBIF_BX_PF_MM_DATA[0], sizeof(mmBIF_BX_PF_MM_DATA)/sizeof(mmBIF_BX_PF_MM_DATA[0]), 0, 0 },
- { "mmBIF_BX_PF_MM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmBIF_BX_PF_MM_INDEX_HI[0], sizeof(mmBIF_BX_PF_MM_INDEX_HI)/sizeof(mmBIF_BX_PF_MM_INDEX_HI[0]), 0, 0 },
+ { "mmMM_INDEX", REG_MMIO, 0x0000, 0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
+ { "mmMM_DATA", REG_MMIO, 0x0001, 0, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
+ { "mmMM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
{ "mmSYSHUB_INDEX_OVLP", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX_OVLP[0], sizeof(mmSYSHUB_INDEX_OVLP)/sizeof(mmSYSHUB_INDEX_OVLP[0]), 0, 0 },
{ "mmSYSHUB_DATA_OVLP", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA_OVLP[0], sizeof(mmSYSHUB_DATA_OVLP)/sizeof(mmSYSHUB_DATA_OVLP[0]), 0, 0 },
{ "mmPCIE_INDEX", REG_MMIO, 0x000c, 0, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },
--
2.20.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH umr 2/2] print data values for WRITE_DATA packet
2020-02-14 14:50 [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3 Xiaojie Yuan
@ 2020-02-14 14:50 ` Xiaojie Yuan
2020-02-14 14:55 ` [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3 Tom St Denis
1 sibling, 0 replies; 5+ messages in thread
From: Xiaojie Yuan @ 2020-02-14 14:50 UTC (permalink / raw)
To: amd-gfx, tom.stdenis; +Cc: Xiaojie Yuan
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
---
src/lib/ring_decode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index 863cb4f..47256cf 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -673,7 +673,7 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, struct umr_ring_decoder
if (!decoder->pm4.next_write_mem.addr_lo)
decoder->pm4.next_write_mem.addr_hi++;
} else {
- printf("DATA");
+ printf("DATA: %s%08lx%s", YELLOW, (unsigned long)ib, RST);
}
}
break;
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3
2020-02-14 14:50 [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3 Xiaojie Yuan
2020-02-14 14:50 ` [PATCH umr 2/2] print data values for WRITE_DATA packet Xiaojie Yuan
@ 2020-02-14 14:55 ` Tom St Denis
2020-02-14 15:06 ` Yuan, Xiaojie
1 sibling, 1 reply; 5+ messages in thread
From: Tom St Denis @ 2020-02-14 14:55 UTC (permalink / raw)
To: Xiaojie Yuan, amd-gfx
Hi,
Thanks for the patch however since the *.i files are machine generate
I'd rather like to avoid patches like this (since they will need to be
continually applied).
The ideal solution is to either patch src/lib/read_vram.c or to patch
the kernel headers. The kernel headers are also likewise machine
generated so patching umr is probably the best.
I'll do this myself.
I will however apply patch #2 of the series.
Thanks,
Tom
On 2020-02-14 9:50 a.m., Xiaojie Yuan wrote:
> Fixes following error while dumping gfx ring:
>
> [BUG]: reg [mmMM_INDEX] not found on asic [navi10]
> [BUG]: reg [mmMM_INDEX_HI] not found on asic [navi10]
> [BUG]: reg [mmMM_DATA] not found on asic [navi10]
> Cannot read from system memory: Operation not permitted
> [ERROR]: Accessing system memory returned: -1
> Cannot read from system memory: Bad address
> [ERROR]: Accessing system memory returned: -1
>
> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
> ---
> src/lib/ip/nbio230_bits.i | 6 +++---
> src/lib/ip/nbio230_regs.i | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/src/lib/ip/nbio230_bits.i b/src/lib/ip/nbio230_bits.i
> index 506ccba..fd5bad8 100644
> --- a/src/lib/ip/nbio230_bits.i
> +++ b/src/lib/ip/nbio230_bits.i
> @@ -1,11 +1,11 @@
> -static struct umr_bitfield mmBIF_BX_PF_MM_INDEX[] = {
> +static struct umr_bitfield mmMM_INDEX[] = {
> { "MM_OFFSET", 0, 30, &umr_bitfield_default },
> { "MM_APER", 31, 31, &umr_bitfield_default },
> };
> -static struct umr_bitfield mmBIF_BX_PF_MM_DATA[] = {
> +static struct umr_bitfield mmMM_DATA[] = {
> { "MM_DATA", 0, 31, &umr_bitfield_default },
> };
> -static struct umr_bitfield mmBIF_BX_PF_MM_INDEX_HI[] = {
> +static struct umr_bitfield mmMM_INDEX_HI[] = {
> { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
> };
> static struct umr_bitfield mmSYSHUB_INDEX_OVLP[] = {
> diff --git a/src/lib/ip/nbio230_regs.i b/src/lib/ip/nbio230_regs.i
> index ab57385..27a644b 100644
> --- a/src/lib/ip/nbio230_regs.i
> +++ b/src/lib/ip/nbio230_regs.i
> @@ -1,6 +1,6 @@
> - { "mmBIF_BX_PF_MM_INDEX", REG_MMIO, 0x0000, 0, &mmBIF_BX_PF_MM_INDEX[0], sizeof(mmBIF_BX_PF_MM_INDEX)/sizeof(mmBIF_BX_PF_MM_INDEX[0]), 0, 0 },
> - { "mmBIF_BX_PF_MM_DATA", REG_MMIO, 0x0001, 0, &mmBIF_BX_PF_MM_DATA[0], sizeof(mmBIF_BX_PF_MM_DATA)/sizeof(mmBIF_BX_PF_MM_DATA[0]), 0, 0 },
> - { "mmBIF_BX_PF_MM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmBIF_BX_PF_MM_INDEX_HI[0], sizeof(mmBIF_BX_PF_MM_INDEX_HI)/sizeof(mmBIF_BX_PF_MM_INDEX_HI[0]), 0, 0 },
> + { "mmMM_INDEX", REG_MMIO, 0x0000, 0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
> + { "mmMM_DATA", REG_MMIO, 0x0001, 0, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
> + { "mmMM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
> { "mmSYSHUB_INDEX_OVLP", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX_OVLP[0], sizeof(mmSYSHUB_INDEX_OVLP)/sizeof(mmSYSHUB_INDEX_OVLP[0]), 0, 0 },
> { "mmSYSHUB_DATA_OVLP", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA_OVLP[0], sizeof(mmSYSHUB_DATA_OVLP)/sizeof(mmSYSHUB_DATA_OVLP[0]), 0, 0 },
> { "mmPCIE_INDEX", REG_MMIO, 0x000c, 0, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3
2020-02-14 14:55 ` [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3 Tom St Denis
@ 2020-02-14 15:06 ` Yuan, Xiaojie
2020-02-14 15:13 ` Tom St Denis
0 siblings, 1 reply; 5+ messages in thread
From: Yuan, Xiaojie @ 2020-02-14 15:06 UTC (permalink / raw)
To: StDenis, Tom; +Cc: amd-gfx
Thanks Tom. I'm just publishing this quick fix so that I can continue my debugging with umr, and your solution sounds more reasonable ; )
BR,
Xiaojie
> On Feb 14, 2020, at 10:55 PM, StDenis, Tom <Tom.StDenis@amd.com> wrote:
>
> Hi,
>
> Thanks for the patch however since the *.i files are machine generate I'd rather like to avoid patches like this (since they will need to be continually applied).
>
> The ideal solution is to either patch src/lib/read_vram.c or to patch the kernel headers. The kernel headers are also likewise machine generated so patching umr is probably the best.
>
> I'll do this myself.
>
> I will however apply patch #2 of the series.
>
> Thanks,
>
> Tom
>
>
>> On 2020-02-14 9:50 a.m., Xiaojie Yuan wrote:
>> Fixes following error while dumping gfx ring:
>>
>> [BUG]: reg [mmMM_INDEX] not found on asic [navi10]
>> [BUG]: reg [mmMM_INDEX_HI] not found on asic [navi10]
>> [BUG]: reg [mmMM_DATA] not found on asic [navi10]
>> Cannot read from system memory: Operation not permitted
>> [ERROR]: Accessing system memory returned: -1
>> Cannot read from system memory: Bad address
>> [ERROR]: Accessing system memory returned: -1
>>
>> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
>> ---
>> src/lib/ip/nbio230_bits.i | 6 +++---
>> src/lib/ip/nbio230_regs.i | 6 +++---
>> 2 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/src/lib/ip/nbio230_bits.i b/src/lib/ip/nbio230_bits.i
>> index 506ccba..fd5bad8 100644
>> --- a/src/lib/ip/nbio230_bits.i
>> +++ b/src/lib/ip/nbio230_bits.i
>> @@ -1,11 +1,11 @@
>> -static struct umr_bitfield mmBIF_BX_PF_MM_INDEX[] = {
>> +static struct umr_bitfield mmMM_INDEX[] = {
>> { "MM_OFFSET", 0, 30, &umr_bitfield_default },
>> { "MM_APER", 31, 31, &umr_bitfield_default },
>> };
>> -static struct umr_bitfield mmBIF_BX_PF_MM_DATA[] = {
>> +static struct umr_bitfield mmMM_DATA[] = {
>> { "MM_DATA", 0, 31, &umr_bitfield_default },
>> };
>> -static struct umr_bitfield mmBIF_BX_PF_MM_INDEX_HI[] = {
>> +static struct umr_bitfield mmMM_INDEX_HI[] = {
>> { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
>> };
>> static struct umr_bitfield mmSYSHUB_INDEX_OVLP[] = {
>> diff --git a/src/lib/ip/nbio230_regs.i b/src/lib/ip/nbio230_regs.i
>> index ab57385..27a644b 100644
>> --- a/src/lib/ip/nbio230_regs.i
>> +++ b/src/lib/ip/nbio230_regs.i
>> @@ -1,6 +1,6 @@
>> - { "mmBIF_BX_PF_MM_INDEX", REG_MMIO, 0x0000, 0, &mmBIF_BX_PF_MM_INDEX[0], sizeof(mmBIF_BX_PF_MM_INDEX)/sizeof(mmBIF_BX_PF_MM_INDEX[0]), 0, 0 },
>> - { "mmBIF_BX_PF_MM_DATA", REG_MMIO, 0x0001, 0, &mmBIF_BX_PF_MM_DATA[0], sizeof(mmBIF_BX_PF_MM_DATA)/sizeof(mmBIF_BX_PF_MM_DATA[0]), 0, 0 },
>> - { "mmBIF_BX_PF_MM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmBIF_BX_PF_MM_INDEX_HI[0], sizeof(mmBIF_BX_PF_MM_INDEX_HI)/sizeof(mmBIF_BX_PF_MM_INDEX_HI[0]), 0, 0 },
>> + { "mmMM_INDEX", REG_MMIO, 0x0000, 0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
>> + { "mmMM_DATA", REG_MMIO, 0x0001, 0, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
>> + { "mmMM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
>> { "mmSYSHUB_INDEX_OVLP", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX_OVLP[0], sizeof(mmSYSHUB_INDEX_OVLP)/sizeof(mmSYSHUB_INDEX_OVLP[0]), 0, 0 },
>> { "mmSYSHUB_DATA_OVLP", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA_OVLP[0], sizeof(mmSYSHUB_DATA_OVLP)/sizeof(mmSYSHUB_DATA_OVLP[0]), 0, 0 },
>> { "mmPCIE_INDEX", REG_MMIO, 0x000c, 0, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3
2020-02-14 15:06 ` Yuan, Xiaojie
@ 2020-02-14 15:13 ` Tom St Denis
0 siblings, 0 replies; 5+ messages in thread
From: Tom St Denis @ 2020-02-14 15:13 UTC (permalink / raw)
To: Yuan, Xiaojie; +Cc: amd-gfx
Both fixes pushed out to master (on gitlab)
Thanks again!
Tom
On 2020-02-14 10:06 a.m., Yuan, Xiaojie wrote:
> Thanks Tom. I'm just publishing this quick fix so that I can continue my debugging with umr, and your solution sounds more reasonable ; )
>
> BR,
> Xiaojie
>
>> On Feb 14, 2020, at 10:55 PM, StDenis, Tom <Tom.StDenis@amd.com> wrote:
>>
>> Hi,
>>
>> Thanks for the patch however since the *.i files are machine generate I'd rather like to avoid patches like this (since they will need to be continually applied).
>>
>> The ideal solution is to either patch src/lib/read_vram.c or to patch the kernel headers. The kernel headers are also likewise machine generated so patching umr is probably the best.
>>
>> I'll do this myself.
>>
>> I will however apply patch #2 of the series.
>>
>> Thanks,
>>
>> Tom
>>
>>
>>> On 2020-02-14 9:50 a.m., Xiaojie Yuan wrote:
>>> Fixes following error while dumping gfx ring:
>>>
>>> [BUG]: reg [mmMM_INDEX] not found on asic [navi10]
>>> [BUG]: reg [mmMM_INDEX_HI] not found on asic [navi10]
>>> [BUG]: reg [mmMM_DATA] not found on asic [navi10]
>>> Cannot read from system memory: Operation not permitted
>>> [ERROR]: Accessing system memory returned: -1
>>> Cannot read from system memory: Bad address
>>> [ERROR]: Accessing system memory returned: -1
>>>
>>> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
>>> ---
>>> src/lib/ip/nbio230_bits.i | 6 +++---
>>> src/lib/ip/nbio230_regs.i | 6 +++---
>>> 2 files changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/src/lib/ip/nbio230_bits.i b/src/lib/ip/nbio230_bits.i
>>> index 506ccba..fd5bad8 100644
>>> --- a/src/lib/ip/nbio230_bits.i
>>> +++ b/src/lib/ip/nbio230_bits.i
>>> @@ -1,11 +1,11 @@
>>> -static struct umr_bitfield mmBIF_BX_PF_MM_INDEX[] = {
>>> +static struct umr_bitfield mmMM_INDEX[] = {
>>> { "MM_OFFSET", 0, 30, &umr_bitfield_default },
>>> { "MM_APER", 31, 31, &umr_bitfield_default },
>>> };
>>> -static struct umr_bitfield mmBIF_BX_PF_MM_DATA[] = {
>>> +static struct umr_bitfield mmMM_DATA[] = {
>>> { "MM_DATA", 0, 31, &umr_bitfield_default },
>>> };
>>> -static struct umr_bitfield mmBIF_BX_PF_MM_INDEX_HI[] = {
>>> +static struct umr_bitfield mmMM_INDEX_HI[] = {
>>> { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
>>> };
>>> static struct umr_bitfield mmSYSHUB_INDEX_OVLP[] = {
>>> diff --git a/src/lib/ip/nbio230_regs.i b/src/lib/ip/nbio230_regs.i
>>> index ab57385..27a644b 100644
>>> --- a/src/lib/ip/nbio230_regs.i
>>> +++ b/src/lib/ip/nbio230_regs.i
>>> @@ -1,6 +1,6 @@
>>> - { "mmBIF_BX_PF_MM_INDEX", REG_MMIO, 0x0000, 0, &mmBIF_BX_PF_MM_INDEX[0], sizeof(mmBIF_BX_PF_MM_INDEX)/sizeof(mmBIF_BX_PF_MM_INDEX[0]), 0, 0 },
>>> - { "mmBIF_BX_PF_MM_DATA", REG_MMIO, 0x0001, 0, &mmBIF_BX_PF_MM_DATA[0], sizeof(mmBIF_BX_PF_MM_DATA)/sizeof(mmBIF_BX_PF_MM_DATA[0]), 0, 0 },
>>> - { "mmBIF_BX_PF_MM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmBIF_BX_PF_MM_INDEX_HI[0], sizeof(mmBIF_BX_PF_MM_INDEX_HI)/sizeof(mmBIF_BX_PF_MM_INDEX_HI[0]), 0, 0 },
>>> + { "mmMM_INDEX", REG_MMIO, 0x0000, 0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
>>> + { "mmMM_DATA", REG_MMIO, 0x0001, 0, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
>>> + { "mmMM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
>>> { "mmSYSHUB_INDEX_OVLP", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX_OVLP[0], sizeof(mmSYSHUB_INDEX_OVLP)/sizeof(mmSYSHUB_INDEX_OVLP[0]), 0, 0 },
>>> { "mmSYSHUB_DATA_OVLP", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA_OVLP[0], sizeof(mmSYSHUB_DATA_OVLP)/sizeof(mmSYSHUB_DATA_OVLP[0]), 0, 0 },
>>> { "mmPCIE_INDEX", REG_MMIO, 0x000c, 0, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-02-14 15:14 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-14 14:50 [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3 Xiaojie Yuan
2020-02-14 14:50 ` [PATCH umr 2/2] print data values for WRITE_DATA packet Xiaojie Yuan
2020-02-14 14:55 ` [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3 Tom St Denis
2020-02-14 15:06 ` Yuan, Xiaojie
2020-02-14 15:13 ` Tom St Denis
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