* [PATCH 1/2] drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c
@ 2020-01-28 19:47 Alex Deucher
2020-01-28 19:47 ` [PATCH 2/2] drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency Alex Deucher
2020-01-29 13:53 ` [PATCH 1/2] drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c Kazlauskas, Nicholas
0 siblings, 2 replies; 5+ messages in thread
From: Alex Deucher @ 2020-01-28 19:47 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
We might get different numbers of clocks from powerplay depending
on what the OEM has populated.
Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 31 ++++++++++++-------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index a27d84ca15a5..8ad32a11d363 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1446,17 +1446,26 @@ void dcn_bw_update_from_pplib(struct dc *dc)
res = verify_clock_values(&fclks);
if (res) {
- ASSERT(fclks.num_levels >= 3);
- dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
- dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
- (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
- * ddr4_dram_factor_single_Channel / 1000.0;
- dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
- (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
- * ddr4_dram_factor_single_Channel / 1000.0;
- dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
- (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
- * ddr4_dram_factor_single_Channel / 1000.0;
+ unsigned vmin0p65_idx = 0;
+ unsigned vmid0p72_idx = fclks.num_levels -
+ (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1));
+ unsigned vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1);
+ unsigned vmax0p9_idx = fclks.num_levels - 1;
+
+ dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =
+ 32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0;
+ dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =
+ dc->dcn_soc->number_of_channels *
+ (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0)
+ * ddr4_dram_factor_single_Channel / 1000.0;
+ dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =
+ dc->dcn_soc->number_of_channels *
+ (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0)
+ * ddr4_dram_factor_single_Channel / 1000.0;
+ dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =
+ dc->dcn_soc->number_of_channels *
+ (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0)
+ * ddr4_dram_factor_single_Channel / 1000.0;
} else
BREAK_TO_DEBUGGER();
--
2.24.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency
2020-01-28 19:47 [PATCH 1/2] drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c Alex Deucher
@ 2020-01-28 19:47 ` Alex Deucher
2020-02-03 21:31 ` Alex Deucher
2020-02-04 2:07 ` Quan, Evan
2020-01-29 13:53 ` [PATCH 1/2] drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c Kazlauskas, Nicholas
1 sibling, 2 replies; 5+ messages in thread
From: Alex Deucher @ 2020-01-28 19:47 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Only send non-0 clocks to DC for validation. This mirrors
what the windows driver does.
Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 4e8ab139bb3b..273126cfc37d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1026,12 +1026,15 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
clocks->num_levels = 0;
for (i = 0; i < pclk_vol_table->count; i++) {
- clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
- clocks->data[i].latency_in_us = latency_required ?
- smu10_get_mem_latency(hwmgr,
- pclk_vol_table->entries[i].clk) :
- 0;
- clocks->num_levels++;
+ if (pclk_vol_table->entries[i].clk) {
+ clocks->data[clocks->num_levels].clocks_in_khz =
+ pclk_vol_table->entries[i].clk * 10;
+ clocks->data[clocks->num_levels].latency_in_us = latency_required ?
+ smu10_get_mem_latency(hwmgr,
+ pclk_vol_table->entries[i].clk) :
+ 0;
+ clocks->num_levels++;
+ }
}
return 0;
--
2.24.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c
2020-01-28 19:47 [PATCH 1/2] drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c Alex Deucher
2020-01-28 19:47 ` [PATCH 2/2] drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency Alex Deucher
@ 2020-01-29 13:53 ` Kazlauskas, Nicholas
1 sibling, 0 replies; 5+ messages in thread
From: Kazlauskas, Nicholas @ 2020-01-29 13:53 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher
On 2020-01-28 2:47 p.m., Alex Deucher wrote:
> We might get different numbers of clocks from powerplay depending
> on what the OEM has populated.
>
> Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 31 ++++++++++++-------
> 1 file changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index a27d84ca15a5..8ad32a11d363 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -1446,17 +1446,26 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> res = verify_clock_values(&fclks);
>
> if (res) {
> - ASSERT(fclks.num_levels >= 3);
> - dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
> - dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
> - (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
> - * ddr4_dram_factor_single_Channel / 1000.0;
> - dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
> - (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
> - * ddr4_dram_factor_single_Channel / 1000.0;
> - dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
> - (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
> - * ddr4_dram_factor_single_Channel / 1000.0;
> + unsigned vmin0p65_idx = 0;
> + unsigned vmid0p72_idx = fclks.num_levels -
> + (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1));
> + unsigned vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1);
> + unsigned vmax0p9_idx = fclks.num_levels - 1;
Might want an assertion for fclks.num_levels > 0 still, since that's
what the function is expecting now.
With that change, this is:
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> +
> + dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =
> + 32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0;
> + dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =
> + dc->dcn_soc->number_of_channels *
> + (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0)
> + * ddr4_dram_factor_single_Channel / 1000.0;
> + dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =
> + dc->dcn_soc->number_of_channels *
> + (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0)
> + * ddr4_dram_factor_single_Channel / 1000.0;
> + dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =
> + dc->dcn_soc->number_of_channels *
> + (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0)
> + * ddr4_dram_factor_single_Channel / 1000.0;
> } else
> BREAK_TO_DEBUGGER();
>
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency
2020-01-28 19:47 ` [PATCH 2/2] drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency Alex Deucher
@ 2020-02-03 21:31 ` Alex Deucher
2020-02-04 2:07 ` Quan, Evan
1 sibling, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2020-02-03 21:31 UTC (permalink / raw)
To: amd-gfx list; +Cc: Alex Deucher
Ping?
On Tue, Jan 28, 2020 at 2:47 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> Only send non-0 clocks to DC for validation. This mirrors
> what the windows driver does.
>
> Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 4e8ab139bb3b..273126cfc37d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1026,12 +1026,15 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
>
> clocks->num_levels = 0;
> for (i = 0; i < pclk_vol_table->count; i++) {
> - clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
> - clocks->data[i].latency_in_us = latency_required ?
> - smu10_get_mem_latency(hwmgr,
> - pclk_vol_table->entries[i].clk) :
> - 0;
> - clocks->num_levels++;
> + if (pclk_vol_table->entries[i].clk) {
> + clocks->data[clocks->num_levels].clocks_in_khz =
> + pclk_vol_table->entries[i].clk * 10;
> + clocks->data[clocks->num_levels].latency_in_us = latency_required ?
> + smu10_get_mem_latency(hwmgr,
> + pclk_vol_table->entries[i].clk) :
> + 0;
> + clocks->num_levels++;
> + }
> }
>
> return 0;
> --
> 2.24.1
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH 2/2] drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency
2020-01-28 19:47 ` [PATCH 2/2] drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency Alex Deucher
2020-02-03 21:31 ` Alex Deucher
@ 2020-02-04 2:07 ` Quan, Evan
1 sibling, 0 replies; 5+ messages in thread
From: Quan, Evan @ 2020-02-04 2:07 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Deucher, Alexander
Reviewed-by: Evan Quan <evan.quan@amd.com>
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Wednesday, January 29, 2020 3:47 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: [PATCH 2/2] drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency
Only send non-0 clocks to DC for validation. This mirrors what the windows driver does.
Bug: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2Fissues%2F963&data=02%7C01%7Cevan.quan%40amd.com%7C201c9325bf144200f84208d7a42ae179%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637158377025664935&sdata=n61wTpS6nqQjPoeM4gDHg9fu79rQIBgtOir%2B%2FJzvj5E%3D&reserved=0
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 4e8ab139bb3b..273126cfc37d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1026,12 +1026,15 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
clocks->num_levels = 0;
for (i = 0; i < pclk_vol_table->count; i++) {
- clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
- clocks->data[i].latency_in_us = latency_required ?
- smu10_get_mem_latency(hwmgr,
- pclk_vol_table->entries[i].clk) :
- 0;
- clocks->num_levels++;
+ if (pclk_vol_table->entries[i].clk) {
+ clocks->data[clocks->num_levels].clocks_in_khz =
+ pclk_vol_table->entries[i].clk * 10;
+ clocks->data[clocks->num_levels].latency_in_us = latency_required ?
+ smu10_get_mem_latency(hwmgr,
+ pclk_vol_table->entries[i].clk) :
+ 0;
+ clocks->num_levels++;
+ }
}
return 0;
--
2.24.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-02-04 2:07 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-28 19:47 [PATCH 1/2] drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c Alex Deucher
2020-01-28 19:47 ` [PATCH 2/2] drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency Alex Deucher
2020-02-03 21:31 ` Alex Deucher
2020-02-04 2:07 ` Quan, Evan
2020-01-29 13:53 ` [PATCH 1/2] drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c Kazlauskas, Nicholas
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