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From: Matt Coffin <mcoffin13@gmail.com>
To: Evan Quan <evan.quan@amd.com>, amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs
Date: Mon, 11 Nov 2019 16:35:58 -0700	[thread overview]
Message-ID: <b9c08122-5bd7-bbd4-395b-ffef149e3ee2@gmail.com> (raw)
Message-ID: <20191111233558.afDzX-Q7Aiu04DJiacM2d6Xw5JvL6U34EfwmQ7hVMgc@z> (raw)
In-Reply-To: <20191111092506.18913-1-evan.quan@amd.com>

Patch is Tested-by: Matt Coffin <mcoffin13@gmail.com>

On 11/11/19 2:25 AM, Evan Quan wrote:
> Otherwise, without RLC reinitialization, the DPM reenablement
> will fail. That affects the custom pptable uploading.
> 
> Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 32 +++++++++++++++----
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
>  2 files changed, 26 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 76a4154b3be2..a4d67b30fd72 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1293,10 +1293,25 @@ static int smu_hw_fini(void *handle)
>  		return ret;
>  	}
>  
> -	ret = smu_stop_dpms(smu);
> -	if (ret) {
> -		pr_warn("Fail to stop Dpms!\n");
> -		return ret;
> +	/*
> +	 * For custom pptable uploading, skip the DPM features
> +	 * disable process on Navi1x ASICs.
> +	 *   - As the gfx related features are under control of
> +	 *     RLC on those ASICs. RLC reinitialization will be
> +	 *     needed to reenable them. That will cost much more
> +	 *     efforts.
> +	 *
> +	 *   - SMU firmware can handle the DPM reenablement
> +	 *     properly.
> +	 */
> +	if (!smu->uploading_custom_pp_table ||
> +	    !((adev->asic_type >= CHIP_NAVI10) &&
> +	      (adev->asic_type <= CHIP_NAVI12))) {
> +		ret = smu_stop_dpms(smu);
> +		if (ret) {
> +			pr_warn("Fail to stop Dpms!\n");
> +			return ret;
> +		}
>  	}
>  
>  	kfree(table_context->driver_pptable);
> @@ -1324,13 +1339,16 @@ int smu_reset(struct smu_context *smu)
>  	struct amdgpu_device *adev = smu->adev;
>  	int ret = 0;
>  
> +	smu->uploading_custom_pp_table = true;
> +
>  	ret = smu_hw_fini(adev);
>  	if (ret)
> -		return ret;
> +		goto out;
>  
>  	ret = smu_hw_init(adev);
> -	if (ret)
> -		return ret;
> +
> +out:
> +	smu->uploading_custom_pp_table = false;
>  
>  	return ret;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 8120e7587585..215841f5fb93 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -391,6 +391,7 @@ struct smu_context
>  
>  	uint32_t smc_if_version;
>  
> +	bool uploading_custom_pp_table;
>  };
>  
>  struct i2c_adapter;
> 
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  parent reply	other threads:[~2019-11-11 23:36 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-11  9:25 [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs Evan Quan
2019-11-11  9:25 ` Evan Quan
     [not found] ` <20191111092506.18913-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-11-11 17:33   ` Alex Deucher
2019-11-11 17:33     ` Alex Deucher
     [not found]     ` <CADnq5_OhXnzYx6EgMM87dh1jgUi6Br86Axwi_KfvLjXuO2+gxw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-11-12  1:33       ` Quan, Evan
2019-11-12  1:33         ` Quan, Evan
2019-11-11 23:35   ` Matt Coffin [this message]
2019-11-11 23:35     ` Matt Coffin

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