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* [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2
@ 2019-11-12  1:46 Evan Quan
  2019-11-12  1:46 ` Evan Quan
       [not found] ` <20191112014653.21325-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 2 replies; 4+ messages in thread
From: Evan Quan @ 2019-11-12  1:46 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: alexdeucher-Re5JQEeQqe8AvxtiuMwx3w, Matt Coffin, Evan Quan

Otherwise, without RLC reinitialization, the DPM reenablement
will fail. That affects the custom pptable uploading.

V2: setting/clearing uploading_custom_pp_table in
    smu_sys_set_pp_table()

Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
Reported-by: Matt Coffin <mcoffin13@gmail.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Matt Coffin <mcoffin13@gmail.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 31 ++++++++++++++++---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 76a4154b3be2..54c21f5a1861 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -591,10 +591,18 @@ int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 	smu_table->power_play_table = smu_table->hardcode_pptable;
 	smu_table->power_play_table_size = size;
 
+	/*
+	 * Special hw_fini action(for Navi1x, the DPMs disablement will be
+	 * skipped) may be needed for custom pptable uploading.
+	 */
+	smu->uploading_custom_pp_table = true;
+
 	ret = smu_reset(smu);
 	if (ret)
 		pr_info("smu reset failed, ret = %d\n", ret);
 
+	smu->uploading_custom_pp_table = false;
+
 failed:
 	mutex_unlock(&smu->mutex);
 	return ret;
@@ -1293,10 +1301,25 @@ static int smu_hw_fini(void *handle)
 		return ret;
 	}
 
-	ret = smu_stop_dpms(smu);
-	if (ret) {
-		pr_warn("Fail to stop Dpms!\n");
-		return ret;
+	/*
+	 * For custom pptable uploading, skip the DPM features
+	 * disable process on Navi1x ASICs.
+	 *   - As the gfx related features are under control of
+	 *     RLC on those ASICs. RLC reinitialization will be
+	 *     needed to reenable them. That will cost much more
+	 *     efforts.
+	 *
+	 *   - SMU firmware can handle the DPM reenablement
+	 *     properly.
+	 */
+	if (!smu->uploading_custom_pp_table ||
+	    !((adev->asic_type >= CHIP_NAVI10) &&
+	      (adev->asic_type <= CHIP_NAVI12))) {
+		ret = smu_stop_dpms(smu);
+		if (ret) {
+			pr_warn("Fail to stop Dpms!\n");
+			return ret;
+		}
 	}
 
 	kfree(table_context->driver_pptable);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8120e7587585..215841f5fb93 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -391,6 +391,7 @@ struct smu_context
 
 	uint32_t smc_if_version;
 
+	bool uploading_custom_pp_table;
 };
 
 struct i2c_adapter;
-- 
2.24.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2
  2019-11-12  1:46 [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2 Evan Quan
@ 2019-11-12  1:46 ` Evan Quan
       [not found] ` <20191112014653.21325-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
  1 sibling, 0 replies; 4+ messages in thread
From: Evan Quan @ 2019-11-12  1:46 UTC (permalink / raw)
  To: amd-gfx; +Cc: alexdeucher, Matt Coffin, Evan Quan

Otherwise, without RLC reinitialization, the DPM reenablement
will fail. That affects the custom pptable uploading.

V2: setting/clearing uploading_custom_pp_table in
    smu_sys_set_pp_table()

Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
Reported-by: Matt Coffin <mcoffin13@gmail.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Matt Coffin <mcoffin13@gmail.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 31 ++++++++++++++++---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 76a4154b3be2..54c21f5a1861 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -591,10 +591,18 @@ int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 	smu_table->power_play_table = smu_table->hardcode_pptable;
 	smu_table->power_play_table_size = size;
 
+	/*
+	 * Special hw_fini action(for Navi1x, the DPMs disablement will be
+	 * skipped) may be needed for custom pptable uploading.
+	 */
+	smu->uploading_custom_pp_table = true;
+
 	ret = smu_reset(smu);
 	if (ret)
 		pr_info("smu reset failed, ret = %d\n", ret);
 
+	smu->uploading_custom_pp_table = false;
+
 failed:
 	mutex_unlock(&smu->mutex);
 	return ret;
@@ -1293,10 +1301,25 @@ static int smu_hw_fini(void *handle)
 		return ret;
 	}
 
-	ret = smu_stop_dpms(smu);
-	if (ret) {
-		pr_warn("Fail to stop Dpms!\n");
-		return ret;
+	/*
+	 * For custom pptable uploading, skip the DPM features
+	 * disable process on Navi1x ASICs.
+	 *   - As the gfx related features are under control of
+	 *     RLC on those ASICs. RLC reinitialization will be
+	 *     needed to reenable them. That will cost much more
+	 *     efforts.
+	 *
+	 *   - SMU firmware can handle the DPM reenablement
+	 *     properly.
+	 */
+	if (!smu->uploading_custom_pp_table ||
+	    !((adev->asic_type >= CHIP_NAVI10) &&
+	      (adev->asic_type <= CHIP_NAVI12))) {
+		ret = smu_stop_dpms(smu);
+		if (ret) {
+			pr_warn("Fail to stop Dpms!\n");
+			return ret;
+		}
 	}
 
 	kfree(table_context->driver_pptable);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8120e7587585..215841f5fb93 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -391,6 +391,7 @@ struct smu_context
 
 	uint32_t smc_if_version;
 
+	bool uploading_custom_pp_table;
 };
 
 struct i2c_adapter;
-- 
2.24.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2
       [not found] ` <20191112014653.21325-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-11-12  9:44   ` Feng, Kenneth
  2019-11-12  9:44     ` Feng, Kenneth
  0 siblings, 1 reply; 4+ messages in thread
From: Feng, Kenneth @ 2019-11-12  9:44 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: alexdeucher-Re5JQEeQqe8AvxtiuMwx3w, Matt Coffin, Quan, Evan

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>



-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Evan Quan
Sent: Tuesday, November 12, 2019 9:47 AM
To: amd-gfx@lists.freedesktop.org
Cc: alexdeucher@gmail.com; Matt Coffin <mcoffin13@gmail.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2

[CAUTION: External Email]

Otherwise, without RLC reinitialization, the DPM reenablement will fail. That affects the custom pptable uploading.

V2: setting/clearing uploading_custom_pp_table in
    smu_sys_set_pp_table()

Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
Reported-by: Matt Coffin <mcoffin13@gmail.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Matt Coffin <mcoffin13@gmail.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 31 ++++++++++++++++---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 76a4154b3be2..54c21f5a1861 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -591,10 +591,18 @@ int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
        smu_table->power_play_table = smu_table->hardcode_pptable;
        smu_table->power_play_table_size = size;

+       /*
+        * Special hw_fini action(for Navi1x, the DPMs disablement will be
+        * skipped) may be needed for custom pptable uploading.
+        */
+       smu->uploading_custom_pp_table = true;
+
        ret = smu_reset(smu);
        if (ret)
                pr_info("smu reset failed, ret = %d\n", ret);

+       smu->uploading_custom_pp_table = false;
+
 failed:
        mutex_unlock(&smu->mutex);
        return ret;
@@ -1293,10 +1301,25 @@ static int smu_hw_fini(void *handle)
                return ret;
        }

-       ret = smu_stop_dpms(smu);
-       if (ret) {
-               pr_warn("Fail to stop Dpms!\n");
-               return ret;
+       /*
+        * For custom pptable uploading, skip the DPM features
+        * disable process on Navi1x ASICs.
+        *   - As the gfx related features are under control of
+        *     RLC on those ASICs. RLC reinitialization will be
+        *     needed to reenable them. That will cost much more
+        *     efforts.
+        *
+        *   - SMU firmware can handle the DPM reenablement
+        *     properly.
+        */
+       if (!smu->uploading_custom_pp_table ||
+           !((adev->asic_type >= CHIP_NAVI10) &&
+             (adev->asic_type <= CHIP_NAVI12))) {
+               ret = smu_stop_dpms(smu);
+               if (ret) {
+                       pr_warn("Fail to stop Dpms!\n");
+                       return ret;
+               }
        }

        kfree(table_context->driver_pptable);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8120e7587585..215841f5fb93 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -391,6 +391,7 @@ struct smu_context

        uint32_t smc_if_version;

+       bool uploading_custom_pp_table;
 };

 struct i2c_adapter;
--
2.24.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2
  2019-11-12  9:44   ` Feng, Kenneth
@ 2019-11-12  9:44     ` Feng, Kenneth
  0 siblings, 0 replies; 4+ messages in thread
From: Feng, Kenneth @ 2019-11-12  9:44 UTC (permalink / raw)
  To: Quan, Evan, amd-gfx; +Cc: alexdeucher, Matt Coffin, Quan, Evan

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>



-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Evan Quan
Sent: Tuesday, November 12, 2019 9:47 AM
To: amd-gfx@lists.freedesktop.org
Cc: alexdeucher@gmail.com; Matt Coffin <mcoffin13@gmail.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2

[CAUTION: External Email]

Otherwise, without RLC reinitialization, the DPM reenablement will fail. That affects the custom pptable uploading.

V2: setting/clearing uploading_custom_pp_table in
    smu_sys_set_pp_table()

Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
Reported-by: Matt Coffin <mcoffin13@gmail.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Matt Coffin <mcoffin13@gmail.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 31 ++++++++++++++++---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 76a4154b3be2..54c21f5a1861 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -591,10 +591,18 @@ int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
        smu_table->power_play_table = smu_table->hardcode_pptable;
        smu_table->power_play_table_size = size;

+       /*
+        * Special hw_fini action(for Navi1x, the DPMs disablement will be
+        * skipped) may be needed for custom pptable uploading.
+        */
+       smu->uploading_custom_pp_table = true;
+
        ret = smu_reset(smu);
        if (ret)
                pr_info("smu reset failed, ret = %d\n", ret);

+       smu->uploading_custom_pp_table = false;
+
 failed:
        mutex_unlock(&smu->mutex);
        return ret;
@@ -1293,10 +1301,25 @@ static int smu_hw_fini(void *handle)
                return ret;
        }

-       ret = smu_stop_dpms(smu);
-       if (ret) {
-               pr_warn("Fail to stop Dpms!\n");
-               return ret;
+       /*
+        * For custom pptable uploading, skip the DPM features
+        * disable process on Navi1x ASICs.
+        *   - As the gfx related features are under control of
+        *     RLC on those ASICs. RLC reinitialization will be
+        *     needed to reenable them. That will cost much more
+        *     efforts.
+        *
+        *   - SMU firmware can handle the DPM reenablement
+        *     properly.
+        */
+       if (!smu->uploading_custom_pp_table ||
+           !((adev->asic_type >= CHIP_NAVI10) &&
+             (adev->asic_type <= CHIP_NAVI12))) {
+               ret = smu_stop_dpms(smu);
+               if (ret) {
+                       pr_warn("Fail to stop Dpms!\n");
+                       return ret;
+               }
        }

        kfree(table_context->driver_pptable);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8120e7587585..215841f5fb93 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -391,6 +391,7 @@ struct smu_context

        uint32_t smc_if_version;

+       bool uploading_custom_pp_table;
 };

 struct i2c_adapter;
--
2.24.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-11-12  9:44 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-12  1:46 [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2 Evan Quan
2019-11-12  1:46 ` Evan Quan
     [not found] ` <20191112014653.21325-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-11-12  9:44   ` Feng, Kenneth
2019-11-12  9:44     ` Feng, Kenneth

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