* [PATCH v9 01/18] drm/dp_mst: Add PBN calculation for DSC modes
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-20 21:35 ` Lyude Paul
2019-12-13 20:08 ` [PATCH v9 02/18] drm/dp_mst: Parse FEC capability on MST ports mikita.lipski
` (16 subsequent siblings)
17 siblings, 1 reply; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: David Francis <David.Francis@amd.com>
With DSC, bpp can be fractional in multiples of 1/16.
Change drm_dp_calc_pbn_mode to reflect this, adding a new
parameter bool dsc. When this parameter is true, treat the
bpp parameter as having units not of bits per pixel, but
1/16 of a bit per pixel
v2: Don't add separate function for this
v3: In the equation divide bpp by 16 as it is expected
not to leave any remainder
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/drm_dp_mst_topology.c | 12 +++++++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +-
drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c | 10 ++++++----
include/drm/drm_dp_mst_helper.h | 3 +--
7 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 455c51c38720..9fc03fc1017d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4967,7 +4967,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
is_y420);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
- dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp);
+ dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
}
dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
mst_mgr,
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index ae5809a1f19a..363e7e58e7e7 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4342,10 +4342,11 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
* drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
* @clock: dot clock for the mode
* @bpp: bpp for the mode.
+ * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
*
* This uses the formula in the spec to calculate the PBN value for a mode.
*/
-int drm_dp_calc_pbn_mode(int clock, int bpp)
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
{
/*
* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
@@ -4356,7 +4357,16 @@ int drm_dp_calc_pbn_mode(int clock, int bpp)
* peak_kbps *= (1006/1000)
* peak_kbps *= (64/54)
* peak_kbps *= 8 convert to bytes
+ *
+ * If the bpp is in units of 1/16, further divide by 16. Put this
+ * factor in the numerator rather than the denominator to avoid
+ * integer overflow
*/
+
+ if (dsc)
+ return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
+ 8 * 54 * 1000 * 1000);
+
return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
8 * 54 * 1000 * 1000);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 03d1cba0b696..92be17711287 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -61,7 +61,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
crtc_state->pipe_bpp = bpp;
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
- crtc_state->pipe_bpp);
+ crtc_state->pipe_bpp,
+ false);
slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
port, crtc_state->pbn);
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 549486f1d937..1c9e23d5a6fd 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -782,7 +782,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
const int bpp = connector->display_info.bpc * 3;
const int clock = crtc_state->adjusted_mode.clock;
- asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp);
+ asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
}
slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index ee28f5b3785e..28eef9282874 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -518,7 +518,7 @@ static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
mst_enc = radeon_encoder->enc_priv;
- mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
+ mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false);
mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
index af2b2de65316..73fc1c485283 100644
--- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
+++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
@@ -18,15 +18,17 @@ int igt_dp_mst_calc_pbn_mode(void *ignored)
int rate;
int bpp;
int expected;
+ bool dsc;
} test_params[] = {
- { 154000, 30, 689 },
- { 234000, 30, 1047 },
- { 297000, 24, 1063 },
+ { 154000, 30, 689, false },
+ { 234000, 30, 1047, false },
+ { 297000, 24, 1063, false },
};
for (i = 0; i < ARRAY_SIZE(test_params); i++) {
pbn = drm_dp_calc_pbn_mode(test_params[i].rate,
- test_params[i].bpp);
+ test_params[i].bpp,
+ test_params[i].dsc);
FAIL(pbn != test_params[i].expected,
"Expected PBN %d for clock %d bpp %d, got %d\n",
test_params[i].expected, test_params[i].rate,
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index d5fc90b30487..68656913cfe5 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -719,8 +719,7 @@ bool drm_dp_mst_port_has_audio(struct drm_dp_mst_topology_mgr *mgr,
struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
-int drm_dp_calc_pbn_mode(int clock, int bpp);
-
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port, int pbn, int slots);
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v9 01/18] drm/dp_mst: Add PBN calculation for DSC modes
2019-12-13 20:08 ` [PATCH v9 01/18] drm/dp_mst: Add PBN calculation for DSC modes mikita.lipski
@ 2019-12-20 21:35 ` Lyude Paul
0 siblings, 0 replies; 30+ messages in thread
From: Lyude Paul @ 2019-12-20 21:35 UTC (permalink / raw)
To: mikita.lipski, amd-gfx; +Cc: David Francis, dri-devel
Actually, one comment on this that should be very simple to add
On Fri, 2019-12-13 at 15:08 -0500, mikita.lipski@amd.com wrote:
> From: David Francis <David.Francis@amd.com>
>
> With DSC, bpp can be fractional in multiples of 1/16.
>
> Change drm_dp_calc_pbn_mode to reflect this, adding a new
> parameter bool dsc. When this parameter is true, treat the
> bpp parameter as having units not of bits per pixel, but
> 1/16 of a bit per pixel
>
> v2: Don't add separate function for this
> v3: In the equation divide bpp by 16 as it is expected
> not to leave any remainder
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Lyude Paul <lyude@redhat.com>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> drivers/gpu/drm/drm_dp_mst_topology.c | 12 +++++++++++-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
> drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +-
> drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c | 10 ++++++----
> include/drm/drm_dp_mst_helper.h | 3 +--
> 7 files changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 455c51c38720..9fc03fc1017d 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4967,7 +4967,7 @@ static int dm_encoder_helper_atomic_check(struct
> drm_encoder *encoder,
> is_y420);
> bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
> clock = adjusted_mode->clock;
> - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock,
> bpp);
> + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp,
> false);
> }
> dm_new_connector_state->vcpi_slots =
> drm_dp_atomic_find_vcpi_slots(state,
> mst
> _mgr,
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index ae5809a1f19a..363e7e58e7e7 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -4342,10 +4342,11 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
> * @clock: dot clock for the mode
> * @bpp: bpp for the mode.
> + * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
> *
> * This uses the formula in the spec to calculate the PBN value for a mode.
> */
> -int drm_dp_calc_pbn_mode(int clock, int bpp)
> +int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> {
> /*
> * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> @@ -4356,7 +4357,16 @@ int drm_dp_calc_pbn_mode(int clock, int bpp)
> * peak_kbps *= (1006/1000)
> * peak_kbps *= (64/54)
> * peak_kbps *= 8 convert to bytes
> + *
> + * If the bpp is in units of 1/16, further divide by 16. Put this
> + * factor in the numerator rather than the denominator to avoid
> + * integer overflow
> */
> +
> + if (dsc)
> + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 *
> 1006),
> + 8 * 54 * 1000 * 1000);
> +
> return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> 8 * 54 * 1000 * 1000);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 03d1cba0b696..92be17711287 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -61,7 +61,8 @@ static int intel_dp_mst_compute_link_config(struct
> intel_encoder *encoder,
> crtc_state->pipe_bpp = bpp;
>
> crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode-
> >crtc_clock,
> - crtc_state->pipe_bpp);
> + crtc_state->pipe_bpp,
> + false);
>
> slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp-
> >mst_mgr,
> port, crtc_state->pbn);
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index 549486f1d937..1c9e23d5a6fd 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -782,7 +782,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
> const int bpp = connector->display_info.bpc * 3;
> const int clock = crtc_state->adjusted_mode.clock;
>
> - asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp);
> + asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp,
> false);
> }
>
> slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
> diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c
> b/drivers/gpu/drm/radeon/radeon_dp_mst.c
> index ee28f5b3785e..28eef9282874 100644
> --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
> +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
> @@ -518,7 +518,7 @@ static bool radeon_mst_mode_fixup(struct drm_encoder
> *encoder,
>
> mst_enc = radeon_encoder->enc_priv;
>
> - mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
> + mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false);
>
> mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc-
> >connector->devices;
> DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for
> encoder %d\n",
> diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> index af2b2de65316..73fc1c485283 100644
> --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> @@ -18,15 +18,17 @@ int igt_dp_mst_calc_pbn_mode(void *ignored)
> int rate;
> int bpp;
> int expected;
> + bool dsc;
> } test_params[] = {
> - { 154000, 30, 689 },
> - { 234000, 30, 1047 },
> - { 297000, 24, 1063 },
> + { 154000, 30, 689, false },
> + { 234000, 30, 1047, false },
> + { 297000, 24, 1063, false },
Mind adding one or two test_params that actually use dsc here?
> };
>
> for (i = 0; i < ARRAY_SIZE(test_params); i++) {
> pbn = drm_dp_calc_pbn_mode(test_params[i].rate,
> - test_params[i].bpp);
> + test_params[i].bpp,
> + test_params[i].dsc);
> FAIL(pbn != test_params[i].expected,
> "Expected PBN %d for clock %d bpp %d, got %d\n",
> test_params[i].expected, test_params[i].rate,
> diff --git a/include/drm/drm_dp_mst_helper.h
> b/include/drm/drm_dp_mst_helper.h
> index d5fc90b30487..68656913cfe5 100644
> --- a/include/drm/drm_dp_mst_helper.h
> +++ b/include/drm/drm_dp_mst_helper.h
> @@ -719,8 +719,7 @@ bool drm_dp_mst_port_has_audio(struct
> drm_dp_mst_topology_mgr *mgr,
> struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct
> drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
>
>
> -int drm_dp_calc_pbn_mode(int clock, int bpp);
> -
> +int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
>
> bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr,
> struct drm_dp_mst_port *port, int pbn, int
> slots);
--
Cheers,
Lyude Paul
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v9 02/18] drm/dp_mst: Parse FEC capability on MST ports
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
2019-12-13 20:08 ` [PATCH v9 01/18] drm/dp_mst: Add PBN calculation for DSC modes mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 03/18] drm/dp_mst: Add MST support to DP DPCD R/W functions mikita.lipski
` (15 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: David Francis <David.Francis@amd.com>
As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.
The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)
That value is needed for FEC and DSC support
Store it on drm_dp_mst_port
Reviewed-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
include/drm/drm_dp_mst_helper.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 363e7e58e7e7..ba5328cdc853 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -846,6 +846,7 @@ static bool drm_dp_sideband_parse_enum_path_resources_ack(struct drm_dp_sideband
{
int idx = 1;
repmsg->u.path_resources.port_number = (raw->msg[idx] >> 4) & 0xf;
+ repmsg->u.path_resources.fec_capable = raw->msg[idx] & 0x1;
idx++;
if (idx > raw->curlen)
goto fail_len;
@@ -2894,6 +2895,7 @@ drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr,
path_res->avail_payload_bw_number);
port->available_pbn =
path_res->avail_payload_bw_number;
+ port->fec_capable = path_res->fec_capable;
}
}
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 68656913cfe5..0cada01e8139 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -156,6 +156,8 @@ struct drm_dp_mst_port {
* audio-capable.
*/
bool has_audio;
+
+ bool fec_capable;
};
/**
@@ -383,6 +385,7 @@ struct drm_dp_port_number_req {
struct drm_dp_enum_path_resources_ack_reply {
u8 port_number;
+ bool fec_capable;
u16 full_payload_bw_number;
u16 avail_payload_bw_number;
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 03/18] drm/dp_mst: Add MST support to DP DPCD R/W functions
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
2019-12-13 20:08 ` [PATCH v9 01/18] drm/dp_mst: Add PBN calculation for DSC modes mikita.lipski
2019-12-13 20:08 ` [PATCH v9 02/18] drm/dp_mst: Parse FEC capability on MST ports mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 04/18] drm/dp_mst: Fill branch->num_ports mikita.lipski
` (14 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: David Francis <David.Francis@amd.com>
Instead of having drm_dp_dpcd_read/write and
drm_dp_mst_dpcd_read/write as entry points into the
aux code, have drm_dp_dpcd_read/write handle both.
This means that DRM drivers can make MST DPCD read/writes.
v2: Fix spacing
v3: Dump dpcd access on MST read/writes
v4: Fix calling wrong function on DPCD write
v5: delete deprecated include of drmP.h
Reviewed-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/drm_dp_aux_dev.c | 12 ++----------
drivers/gpu/drm/drm_dp_helper.c | 30 ++++++++++++++++++++----------
2 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c b/drivers/gpu/drm/drm_dp_aux_dev.c
index 0cfb386754c3..2510717d5a08 100644
--- a/drivers/gpu/drm/drm_dp_aux_dev.c
+++ b/drivers/gpu/drm/drm_dp_aux_dev.c
@@ -163,11 +163,7 @@ static ssize_t auxdev_read_iter(struct kiocb *iocb, struct iov_iter *to)
break;
}
- if (aux_dev->aux->is_remote)
- res = drm_dp_mst_dpcd_read(aux_dev->aux, pos, buf,
- todo);
- else
- res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
+ res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
if (res <= 0)
break;
@@ -215,11 +211,7 @@ static ssize_t auxdev_write_iter(struct kiocb *iocb, struct iov_iter *from)
break;
}
- if (aux_dev->aux->is_remote)
- res = drm_dp_mst_dpcd_write(aux_dev->aux, pos, buf,
- todo);
- else
- res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
+ res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
if (res <= 0)
break;
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..2faef8bd911f 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -32,6 +32,7 @@
#include <drm/drm_dp_helper.h>
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
+#include <drm/drm_dp_mst_helper.h>
#include "drm_crtc_helper_internal.h"
@@ -266,7 +267,7 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
/**
* drm_dp_dpcd_read() - read a series of bytes from the DPCD
- * @aux: DisplayPort AUX channel
+ * @aux: DisplayPort AUX channel (SST or MST)
* @offset: address of the (first) register to read
* @buffer: buffer to store the register values
* @size: number of bytes in @buffer
@@ -295,13 +296,18 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
* We just have to do it before any DPCD access and hope that the
* monitor doesn't power down exactly after the throw away read.
*/
- ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
- 1);
- if (ret != 1)
- goto out;
+ if (!aux->is_remote) {
+ ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
+ buffer, 1);
+ if (ret != 1)
+ goto out;
+ }
- ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
- size);
+ if (aux->is_remote)
+ ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
+ else
+ ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
+ buffer, size);
out:
drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
@@ -311,7 +317,7 @@ EXPORT_SYMBOL(drm_dp_dpcd_read);
/**
* drm_dp_dpcd_write() - write a series of bytes to the DPCD
- * @aux: DisplayPort AUX channel
+ * @aux: DisplayPort AUX channel (SST or MST)
* @offset: address of the (first) register to write
* @buffer: buffer containing the values to write
* @size: number of bytes in @buffer
@@ -328,8 +334,12 @@ ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
{
int ret;
- ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
- size);
+ if (aux->is_remote)
+ ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
+ else
+ ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
+ buffer, size);
+
drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
return ret;
}
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 04/18] drm/dp_mst: Fill branch->num_ports
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (2 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 03/18] drm/dp_mst: Add MST support to DP DPCD R/W functions mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 05/18] drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux mikita.lipski
` (13 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: David Francis <David.Francis@amd.com>
This field on drm_dp_mst_branch was never filled
It is initialized to zero when the port is kzallocced.
When a port is added to the list, increment num_ports,
and when a port is removed from the list, decrement num_ports.
v2: remember to decrement on port removal
v3: don't explicitly init to 0
v4: move decrement of num_ports to unlink_port function
Reviewed-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index ba5328cdc853..5a4c2db15c35 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -2157,6 +2157,7 @@ drm_dp_mst_topology_unlink_port(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port)
{
mutex_lock(&mgr->lock);
+ port->parent->num_ports--;
list_del(&port->next);
mutex_unlock(&mgr->lock);
drm_dp_mst_topology_put_port(port);
@@ -2256,6 +2257,7 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb,
mutex_lock(&mgr->lock);
drm_dp_mst_topology_get_port(port);
list_add(&port->next, &mstb->ports);
+ mstb->num_ports++;
mutex_unlock(&mgr->lock);
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 05/18] drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (3 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 04/18] drm/dp_mst: Fill branch->num_ports mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 06/18] drm/dp_mst: Add new quirk for Synaptics MST hubs mikita.lipski
` (12 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: David Francis <David.Francis@amd.com>
Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED
register might have to be written on the leaf port's DPCD,
its parent's DPCD, or the MST manager's DPCD. This function
finds the correct aux for the job.
As part of this, add drm_dp_mst_is_virtual_dpcd. Virtual DPCD
is a DP feature new in DP v1.4, which exposes certain DPCD
registers on virtual ports.
v2: Remember to unlock mutex on all paths
v3: Refactor to match coding style and increase brevity
v4: - Check DSC capable MST sink connected directly to the device.
- Check branch's port_parent to be set
Cc: Lyude Paul <lyude@redhat.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 143 ++++++++++++++++++++++++++
include/drm/drm_dp_mst_helper.h | 2 +
2 files changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 5a4c2db15c35..d58adcde8d72 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -5003,3 +5003,146 @@ static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux)
{
i2c_del_adapter(&aux->ddc);
}
+
+/**
+ * drm_dp_mst_is_virtual_dpcd() - Is the given port a virtual DP Peer Device
+ * @port: The port to check
+ *
+ * A single physical MST hub object can be represented in the topology
+ * by multiple branches, with virtual ports between those branches.
+ *
+ * As of DP1.4, An MST hub with internal (virtual) ports must expose
+ * certain DPCD registers over those ports. See sections 2.6.1.1.1
+ * and 2.6.1.1.2 of Display Port specification v1.4 for details.
+ *
+ * May acquire mgr->lock
+ *
+ * Returns:
+ * true if the port is a virtual DP peer device, false otherwise
+ */
+static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port)
+{
+ struct drm_dp_mst_port *downstream_port;
+
+ if (!port || port->dpcd_rev < DP_DPCD_REV_14)
+ return false;
+
+ /* Virtual DP Sink (Internal Display Panel) */
+ if (port->port_num >= 8)
+ return true;
+
+ /* DP-to-HDMI Protocol Converter */
+ if (port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV &&
+ !port->mcs &&
+ port->ldps)
+ return true;
+
+ /* DP-to-DP */
+ mutex_lock(&port->mgr->lock);
+ if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
+ port->mstb &&
+ port->mstb->num_ports == 2) {
+ list_for_each_entry(downstream_port, &port->mstb->ports, next) {
+ if (downstream_port->pdt == DP_PEER_DEVICE_SST_SINK &&
+ !downstream_port->input) {
+ mutex_unlock(&port->mgr->lock);
+ return true;
+ }
+ }
+ }
+ mutex_unlock(&port->mgr->lock);
+
+ return false;
+}
+
+/**
+ * drm_dp_mst_dsc_aux_for_port() - Find the correct aux for DSC
+ * @port: The port to check. A leaf of the MST tree with an attached display.
+ *
+ * Depending on the situation, DSC may be enabled via the endpoint aux,
+ * the immediately upstream aux, or the connector's physical aux.
+ *
+ * This is both the correct aux to read DSC_CAPABILITY and the
+ * correct aux to write DSC_ENABLED.
+ *
+ * This operation can be expensive (up to four aux reads), so
+ * the caller should cache the return.
+ *
+ * Returns:
+ * NULL if DSC cannot be enabled on this port, otherwise the aux device
+ */
+struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
+{
+ struct drm_dp_mst_port *immediate_upstream_port;
+ struct drm_dp_mst_port *fec_port;
+ u8 endpoint_fec;
+ u8 endpoint_dsc;
+
+ if (!port)
+ return NULL;
+
+ if (port->parent->port_parent)
+ immediate_upstream_port = port->parent->port_parent;
+ else
+ immediate_upstream_port = NULL;
+
+ fec_port = immediate_upstream_port;
+ while (fec_port) {
+ /*
+ * Each physical link (i.e. not a virtual port) between the
+ * output and the primary device must support FEC
+ */
+ if (!drm_dp_mst_is_virtual_dpcd(fec_port) &&
+ !fec_port->fec_capable)
+ return NULL;
+
+ fec_port = fec_port->parent->port_parent;
+ }
+
+ /* DP-to-DP peer device */
+ if (drm_dp_mst_is_virtual_dpcd(immediate_upstream_port)) {
+ u8 upstream_dsc;
+
+ if (drm_dp_dpcd_read(&port->aux,
+ DP_DSC_SUPPORT, &endpoint_dsc, 1) != 1)
+ return NULL;
+ if (drm_dp_dpcd_read(&port->aux,
+ DP_FEC_CAPABILITY, &endpoint_fec, 1) != 1)
+ return NULL;
+ if (drm_dp_dpcd_read(&immediate_upstream_port->aux,
+ DP_DSC_SUPPORT, &upstream_dsc, 1) != 1)
+ return NULL;
+
+ /* Enpoint decompression with DP-to-DP peer device */
+ if ((endpoint_dsc & DP_DSC_DECOMPRESSION_IS_SUPPORTED) &&
+ (endpoint_fec & DP_FEC_CAPABLE) &&
+ (upstream_dsc & 0x2) /* DSC passthrough */)
+ return &port->aux;
+
+ /* Virtual DPCD decompression with DP-to-DP peer device */
+ return &immediate_upstream_port->aux;
+ }
+
+ /* Virtual DPCD decompression with DP-to-HDMI or Virtual DP Sink */
+ if (drm_dp_mst_is_virtual_dpcd(port))
+ return &port->aux;
+
+ /*
+ * The check below verifies if the MST sink
+ * connected to the GPU is capable of DSC -
+ * therefore the endpoint needs to be
+ * both DSC and FEC capable.
+ */
+ if (drm_dp_dpcd_read(&port->aux,
+ DP_DSC_SUPPORT, &endpoint_dsc, 1) != 1)
+ return NULL;
+ if (drm_dp_dpcd_read(&port->aux,
+ DP_FEC_CAPABILITY, &endpoint_fec, 1) != 1)
+ return NULL;
+ if ((endpoint_dsc & DP_DSC_DECOMPRESSION_IS_SUPPORTED) &&
+ (endpoint_fec & DP_FEC_CAPABLE))
+ return &port->aux;
+
+ return NULL;
+}
+EXPORT_SYMBOL(drm_dp_mst_dsc_aux_for_port);
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 0cada01e8139..32e60b9d7098 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -783,6 +783,8 @@ int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);
void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port);
void drm_dp_mst_put_port_malloc(struct drm_dp_mst_port *port);
+struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port);
+
extern const struct drm_private_state_funcs drm_dp_mst_topology_state_funcs;
/**
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 06/18] drm/dp_mst: Add new quirk for Synaptics MST hubs
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (4 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 05/18] drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 07/18] drm/amd/display: Initialize DSC PPS variables to 0 mikita.lipski
` (11 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: Mikita Lipski <mikita.lipski@amd.com>
Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not
support virtual DPCD registers, but do support DSC.
The DSC caps can be read from the physical aux,
like in SST DSC. These hubs have many different
DEVICE_IDs. Add a new quirk to detect this case.
v2: Fix error when checking return of drm_dp_read_desc
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/drm_dp_helper.c | 2 ++
drivers/gpu/drm/drm_dp_mst_topology.c | 27 +++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 7 +++++++
3 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2faef8bd911f..374cedc6c2ac 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1165,6 +1165,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
/* CH7511 seems to leave SINK_COUNT zeroed */
{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
+ /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
};
#undef OUI
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index d58adcde8d72..74bed71f7315 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -5075,6 +5075,7 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
{
struct drm_dp_mst_port *immediate_upstream_port;
struct drm_dp_mst_port *fec_port;
+ struct drm_dp_desc desc = { 0 };
u8 endpoint_fec;
u8 endpoint_dsc;
@@ -5127,6 +5128,32 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
if (drm_dp_mst_is_virtual_dpcd(port))
return &port->aux;
+ /*
+ * Synaptics quirk
+ * Applies to ports for which:
+ * - Physical aux has Synaptics OUI
+ * - DPv1.4 or higher
+ * - Port is on primary branch device
+ * - Not a VGA adapter (DP_DWN_STRM_PORT_TYPE_ANALOG)
+ */
+ if (drm_dp_read_desc(port->mgr->aux, &desc, true))
+ return NULL;
+
+ if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&
+ port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
+ port->parent == port->mgr->mst_primary) {
+ u8 downstreamport;
+
+ if (drm_dp_dpcd_read(&port->aux, DP_DOWNSTREAMPORT_PRESENT,
+ &downstreamport, 1) < 0)
+ return NULL;
+
+ if ((downstreamport & DP_DWN_STRM_PORT_PRESENT) &&
+ ((downstreamport & DP_DWN_STRM_PORT_TYPE_MASK)
+ != DP_DWN_STRM_PORT_TYPE_ANALOG))
+ return port->mgr->aux;
+ }
+
/*
* The check below verifies if the MST sink
* connected to the GPU is capable of DSC -
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index b2057009aabc..7972c8bf97cf 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1522,6 +1522,13 @@ enum drm_dp_quirk {
* The driver should ignore SINK_COUNT during detection.
*/
DP_DPCD_QUIRK_NO_SINK_COUNT,
+ /**
+ * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
+ *
+ * The device supports MST DSC despite not supporting Virtual DPCD.
+ * The DSC caps can be read from the physical aux instead.
+ */
+ DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
};
/**
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 07/18] drm/amd/display: Initialize DSC PPS variables to 0
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (5 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 06/18] drm/dp_mst: Add new quirk for Synaptics MST hubs mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 08/18] drm/amd/display: Validate DSC caps on MST endpoints mikita.lipski
` (10 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: David Francis <David.Francis@amd.com>
For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.
memset to 0 to avoid this
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 548aac02ca11..4fd51c76317a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -518,6 +518,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
struct dsc_config dsc_cfg;
uint8_t dsc_packed_pps[128];
+ memset(&dsc_cfg, 0, sizeof(dsc_cfg));
+ memset(dsc_packed_pps, 0, 128);
+
/* Enable DSC hw block */
dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 0111545dac75..6bdfee20b6a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -206,6 +206,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
struct dsc_reg_values dsc_reg_vals;
struct dsc_optc_config dsc_optc_cfg;
+ memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
+ memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
+
DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
dsc_config_log(dsc, dsc_cfg);
DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 08/18] drm/amd/display: Validate DSC caps on MST endpoints
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (6 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 07/18] drm/amd/display: Initialize DSC PPS variables to 0 mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 09/18] drm/amd/display: Write DSC enable to MST DPCD mikita.lipski
` (9 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: David Francis <David.Francis@amd.com>
During MST mode enumeration, if a new dc_sink is created,
populate it with dsc caps as appropriate.
Use drm_dp_mst_dsc_aux_for_port to get the raw caps,
then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 27 ++++++++++++++++++-
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index ae36d99d0fb2..b544498d435e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -323,6 +323,7 @@ struct amdgpu_dm_connector {
struct drm_dp_mst_port *port;
struct amdgpu_dm_connector *mst_port;
struct amdgpu_encoder *mst_encoder;
+ struct drm_dp_aux *dsc_aux;
/* TODO see if we can merge with ddc_bus or make a dm_connector */
struct amdgpu_i2c_adapter *i2c;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 81367c869134..7557edee7db0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -25,6 +25,7 @@
#include <linux/version.h>
#include <drm/drm_atomic_helper.h>
+#include <drm/drm_dp_mst_helper.h>
#include "dm_services.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
@@ -180,6 +181,26 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
.early_unregister = amdgpu_dm_mst_connector_early_unregister,
};
+static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
+{
+ struct dc_sink *dc_sink = aconnector->dc_sink;
+ struct drm_dp_mst_port *port = aconnector->port;
+ u8 dsc_caps[16] = { 0 };
+
+ aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
+
+ if (!aconnector->dsc_aux)
+ return false;
+
+ if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
+ return false;
+
+ if (!dc_dsc_parse_dsc_dpcd(dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps))
+ return false;
+
+ return true;
+}
+
static int dm_dp_mst_get_modes(struct drm_connector *connector)
{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
@@ -222,10 +243,14 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
/* dc_link_add_remote_sink returns a new reference */
aconnector->dc_sink = dc_sink;
- if (aconnector->dc_sink)
+ if (aconnector->dc_sink) {
amdgpu_dm_update_freesync_caps(
connector, aconnector->edid);
+ if (!validate_dsc_caps_on_connector(aconnector))
+ memset(&aconnector->dc_sink->sink_dsc_caps,
+ 0, sizeof(aconnector->dc_sink->sink_dsc_caps));
+ }
}
drm_connector_update_edid_property(
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 09/18] drm/amd/display: Write DSC enable to MST DPCD
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (7 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 08/18] drm/amd/display: Validate DSC caps on MST endpoints mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 10/18] drm/dp_mst: Manually overwrite PBN divider for calculating timeslots mikita.lipski
` (8 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: David Francis <David.Francis@amd.com>
Rework the dm_helpers_write_dsc_enable callback to
handle the MST case.
Use the cached dsc_aux field.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 66f266a5e10b..069b7a6f5597 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -37,6 +37,7 @@
#include "dc.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_irq.h"
+#include "amdgpu_dm_mst_types.h"
#include "dm_helpers.h"
@@ -516,8 +517,24 @@ bool dm_helpers_dp_write_dsc_enable(
)
{
uint8_t enable_dsc = enable ? 1 : 0;
+ struct amdgpu_dm_connector *aconnector;
+
+ if (!stream)
+ return false;
+
+ if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+
+ if (!aconnector->dsc_aux)
+ return false;
+
+ return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1) >= 0);
+ }
+
+ if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)
+ return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
- return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
+ return false;
}
bool dm_helpers_is_dp_sink_present(struct dc_link *link)
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 10/18] drm/dp_mst: Manually overwrite PBN divider for calculating timeslots
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (8 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 09/18] drm/amd/display: Write DSC enable to MST DPCD mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-20 21:45 ` Lyude Paul
2019-12-13 20:08 ` [PATCH v9 11/18] drm/dp_mst: Add DSC enablement helpers to DRM mikita.lipski
` (7 subsequent siblings)
17 siblings, 1 reply; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Manasi Navare, Harry Wentland, Mikita Lipski, dri-devel
From: Mikita Lipski <mikita.lipski@amd.com>
[why]
For DSC case we cannot use topology manager's PBN divider
variable. The default divider does not take FEC into account.
Therefore the driver has to calculate its own divider based
on the link rate and lane count its handling, as it is hw specific.
[how]
Pass pbn_div as an argument, which is used if its more than
zero, otherwise default topology manager's pbn_div will be used.
Cc: Lyude Paul <lyude@redhat.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
drivers/gpu/drm/drm_dp_mst_topology.c | 9 +++++++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 ++-
include/drm/drm_dp_mst_helper.h | 3 ++-
5 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9fc03fc1017d..753a79734817 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4972,7 +4972,8 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
mst_mgr,
mst_port,
- dm_new_connector_state->pbn);
+ dm_new_connector_state->pbn,
+ 0);
if (dm_new_connector_state->vcpi_slots < 0) {
DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
return dm_new_connector_state->vcpi_slots;
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 74bed71f7315..bb0844dfb3d2 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4020,6 +4020,7 @@ static int drm_dp_init_vcpi(struct drm_dp_mst_topology_mgr *mgr,
* @mgr: MST topology manager for the port
* @port: port to find vcpi slots for
* @pbn: bandwidth required for the mode in PBN
+ * @pbn_div: divider for DSC mode that takes FEC into account
*
* Allocates VCPI slots to @port, replacing any previous VCPI allocations it
* may have had. Any atomic drivers which support MST must call this function
@@ -4046,7 +4047,8 @@ static int drm_dp_init_vcpi(struct drm_dp_mst_topology_mgr *mgr,
*/
int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
- struct drm_dp_mst_port *port, int pbn)
+ struct drm_dp_mst_port *port, int pbn,
+ int pbn_div)
{
struct drm_dp_mst_topology_state *topology_state;
struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
@@ -4079,7 +4081,10 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
if (!vcpi)
prev_slots = 0;
- req_slots = DIV_ROUND_UP(pbn, mgr->pbn_div);
+ if (pbn_div <= 0)
+ pbn_div = mgr->pbn_div;
+
+ req_slots = DIV_ROUND_UP(pbn, pbn_div);
DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
port->connector->base.id, port->connector->name,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 92be17711287..a068f54a6793 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -65,7 +65,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
false);
slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
- port, crtc_state->pbn);
+ port, crtc_state->pbn, 0);
if (slots == -EDEADLK)
return slots;
if (slots >= 0)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 1c9e23d5a6fd..edb78966c5b6 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -787,7 +787,8 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
mstc->port,
- asyh->dp.pbn);
+ asyh->dp.pbn,
+ 0);
if (slots < 0)
return slots;
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 32e60b9d7098..0f813d6346aa 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -771,7 +771,8 @@ struct drm_dp_mst_topology_state *drm_atomic_get_mst_topology_state(struct drm_a
int __must_check
drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
- struct drm_dp_mst_port *port, int pbn);
+ struct drm_dp_mst_port *port, int pbn,
+ int pbn_div);
int __must_check
drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v9 10/18] drm/dp_mst: Manually overwrite PBN divider for calculating timeslots
2019-12-13 20:08 ` [PATCH v9 10/18] drm/dp_mst: Manually overwrite PBN divider for calculating timeslots mikita.lipski
@ 2019-12-20 21:45 ` Lyude Paul
0 siblings, 0 replies; 30+ messages in thread
From: Lyude Paul @ 2019-12-20 21:45 UTC (permalink / raw)
To: mikita.lipski, amd-gfx; +Cc: Manasi Navare, Harry Wentland, dri-devel
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Fri, 2019-12-13 at 15:08 -0500, mikita.lipski@amd.com wrote:
> From: Mikita Lipski <mikita.lipski@amd.com>
>
> [why]
> For DSC case we cannot use topology manager's PBN divider
> variable. The default divider does not take FEC into account.
> Therefore the driver has to calculate its own divider based
> on the link rate and lane count its handling, as it is hw specific.
>
> [how]
> Pass pbn_div as an argument, which is used if its more than
> zero, otherwise default topology manager's pbn_div will be used.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
> drivers/gpu/drm/drm_dp_mst_topology.c | 9 +++++++--
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 ++-
> include/drm/drm_dp_mst_helper.h | 3 ++-
> 5 files changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 9fc03fc1017d..753a79734817 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4972,7 +4972,8 @@ static int dm_encoder_helper_atomic_check(struct
> drm_encoder *encoder,
> dm_new_connector_state->vcpi_slots =
> drm_dp_atomic_find_vcpi_slots(state,
> mst
> _mgr,
> mst
> _port,
> - dm_
> new_connector_state->pbn);
> + dm_
> new_connector_state->pbn,
> + 0);
> if (dm_new_connector_state->vcpi_slots < 0) {
> DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n",
> (int)dm_new_connector_state->vcpi_slots);
> return dm_new_connector_state->vcpi_slots;
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 74bed71f7315..bb0844dfb3d2 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -4020,6 +4020,7 @@ static int drm_dp_init_vcpi(struct
> drm_dp_mst_topology_mgr *mgr,
> * @mgr: MST topology manager for the port
> * @port: port to find vcpi slots for
> * @pbn: bandwidth required for the mode in PBN
> + * @pbn_div: divider for DSC mode that takes FEC into account
> *
> * Allocates VCPI slots to @port, replacing any previous VCPI allocations
> it
> * may have had. Any atomic drivers which support MST must call this
> function
> @@ -4046,7 +4047,8 @@ static int drm_dp_init_vcpi(struct
> drm_dp_mst_topology_mgr *mgr,
> */
> int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> struct drm_dp_mst_topology_mgr *mgr,
> - struct drm_dp_mst_port *port, int pbn)
> + struct drm_dp_mst_port *port, int pbn,
> + int pbn_div)
> {
> struct drm_dp_mst_topology_state *topology_state;
> struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
> @@ -4079,7 +4081,10 @@ int drm_dp_atomic_find_vcpi_slots(struct
> drm_atomic_state *state,
> if (!vcpi)
> prev_slots = 0;
>
> - req_slots = DIV_ROUND_UP(pbn, mgr->pbn_div);
> + if (pbn_div <= 0)
> + pbn_div = mgr->pbn_div;
> +
> + req_slots = DIV_ROUND_UP(pbn, pbn_div);
>
> DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
> port->connector->base.id, port->connector->name,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 92be17711287..a068f54a6793 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -65,7 +65,7 @@ static int intel_dp_mst_compute_link_config(struct
> intel_encoder *encoder,
> false);
>
> slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp-
> >mst_mgr,
> - port, crtc_state->pbn);
> + port, crtc_state->pbn,
> 0);
> if (slots == -EDEADLK)
> return slots;
> if (slots >= 0)
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index 1c9e23d5a6fd..edb78966c5b6 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -787,7 +787,8 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
>
> slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
> mstc->port,
> - asyh->dp.pbn);
> + asyh->dp.pbn,
> + 0);
> if (slots < 0)
> return slots;
>
> diff --git a/include/drm/drm_dp_mst_helper.h
> b/include/drm/drm_dp_mst_helper.h
> index 32e60b9d7098..0f813d6346aa 100644
> --- a/include/drm/drm_dp_mst_helper.h
> +++ b/include/drm/drm_dp_mst_helper.h
> @@ -771,7 +771,8 @@ struct drm_dp_mst_topology_state
> *drm_atomic_get_mst_topology_state(struct drm_a
> int __must_check
> drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> struct drm_dp_mst_topology_mgr *mgr,
> - struct drm_dp_mst_port *port, int pbn);
> + struct drm_dp_mst_port *port, int pbn,
> + int pbn_div);
> int __must_check
> drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state,
> struct drm_dp_mst_topology_mgr *mgr,
--
Cheers,
Lyude Paul
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v9 11/18] drm/dp_mst: Add DSC enablement helpers to DRM
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (9 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 10/18] drm/dp_mst: Manually overwrite PBN divider for calculating timeslots mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 12/18] drm/dp_mst: Add branch bandwidth validation to MST atomic check mikita.lipski
` (6 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Mikita Lipski, dri-devel
From: Mikita Lipski <mikita.lipski@amd.com>
Adding a helper function to be called by
drivers outside of DRM to enable DSC on
the MST ports.
Function is called to recalculate VCPI allocation
if DSC is enabled and raise the DSC flag to enable.
In case of disabling DSC the flag is set to false
and recalculation of VCPI slots is expected to be done
in encoder's atomic_check.
v2: squash separate functions into one and call it per
port
v3: Fix comment typos
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 61 +++++++++++++++++++++++++++
include/drm/drm_dp_mst_helper.h | 5 +++
2 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index bb0844dfb3d2..7cd505e771ff 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4716,6 +4716,67 @@ drm_dp_mst_atomic_check_topology_state(struct drm_dp_mst_topology_mgr *mgr,
return 0;
}
+/**
+ * drm_dp_mst_atomic_enable_dsc - Set DSC Enable Flag to On/Off
+ * @state: Pointer to the new drm_atomic_state
+ * @port: Pointer to the affected MST Port
+ * @pbn: Newly recalculated bw required for link with DSC enabled
+ * @pbn_div: Divider to calculate correct number of pbn per slot
+ * @enable: Boolean flag to enable or disable DSC on the port
+ *
+ * This function enables DSC on the given Port
+ * by recalculating its vcpi from pbn provided
+ * and sets dsc_enable flag to keep track of which
+ * ports have DSC enabled
+ *
+ */
+int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
+ struct drm_dp_mst_port *port,
+ int pbn, int pbn_div,
+ bool enable)
+{
+ struct drm_dp_mst_topology_state *mst_state;
+ struct drm_dp_vcpi_allocation *pos;
+ bool found = false;
+ int vcpi = 0;
+
+ mst_state = drm_atomic_get_mst_topology_state(state, port->mgr);
+
+ if (IS_ERR(mst_state))
+ return PTR_ERR(mst_state);
+
+ list_for_each_entry(pos, &mst_state->vcpis, next) {
+ if (pos->port == port) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ DRM_DEBUG_ATOMIC("[MST PORT:%p] Couldn't find VCPI allocation in mst state %p\n",
+ port, mst_state);
+ return -EINVAL;
+ }
+
+ if (pos->dsc_enabled == enable) {
+ DRM_DEBUG_ATOMIC("[MST PORT:%p] DSC flag is already set to %d, returning %d VCPI slots\n",
+ port, enable, pos->vcpi);
+ vcpi = pos->vcpi;
+ }
+
+ if (enable) {
+ vcpi = drm_dp_atomic_find_vcpi_slots(state, port->mgr, port, pbn, pbn_div);
+ DRM_DEBUG_ATOMIC("[MST PORT:%p] Enabling DSC flag, reallocating %d VCPI slots on the port\n",
+ port, vcpi);
+ if (vcpi < 0)
+ return -EINVAL;
+ }
+
+ pos->dsc_enabled = enable;
+
+ return vcpi;
+}
+EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
/**
* drm_dp_mst_atomic_check - Check that the new state of an MST topology in an
* atomic update is valid
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 0f813d6346aa..830c94b7f45d 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -502,6 +502,7 @@ struct drm_dp_payload {
struct drm_dp_vcpi_allocation {
struct drm_dp_mst_port *port;
int vcpi;
+ bool dsc_enabled;
struct list_head next;
};
@@ -773,6 +774,10 @@ drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port, int pbn,
int pbn_div);
+int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
+ struct drm_dp_mst_port *port,
+ int pbn, int pbn_div,
+ bool enable);
int __must_check
drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 12/18] drm/dp_mst: Add branch bandwidth validation to MST atomic check
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (10 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 11/18] drm/dp_mst: Add DSC enablement helpers to DRM mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2020-01-17 15:09 ` Sean Paul
2019-12-13 20:08 ` [PATCH v9 13/18] drm/dp_mst: Rename drm_dp_mst_atomic_check_topology_state mikita.lipski
` (5 subsequent siblings)
17 siblings, 1 reply; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Mikita Lipski, dri-devel
From: Mikita Lipski <mikita.lipski@amd.com>
[why]
Adding PBN attribute to drm_dp_vcpi_allocation structure to
keep track of how much bandwidth each Port requires.
Adding drm_dp_mst_atomic_check_bw_limit to verify that
state's bandwidth needs doesn't exceed available bandwidth.
The funtion is called in drm_dp_mst_atomic_check after
drm_dp_mst_atomic_check_topology_state to fully verify that
the proposed topology is supported.
v2: Fixing some typos and indentations
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 66 ++++++++++++++++++++++++++-
include/drm/drm_dp_mst_helper.h | 1 +
2 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 7cd505e771ff..f8b72ac79c66 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4052,7 +4052,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
{
struct drm_dp_mst_topology_state *topology_state;
struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
- int prev_slots, req_slots;
+ int prev_slots, prev_bw, req_slots;
topology_state = drm_atomic_get_mst_topology_state(state, mgr);
if (IS_ERR(topology_state))
@@ -4063,6 +4063,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
if (pos->port == port) {
vcpi = pos;
prev_slots = vcpi->vcpi;
+ prev_bw = vcpi->pbn;
/*
* This should never happen, unless the driver tries
@@ -4078,8 +4079,10 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
break;
}
}
- if (!vcpi)
+ if (!vcpi) {
prev_slots = 0;
+ prev_bw = 0;
+ }
if (pbn_div <= 0)
pbn_div = mgr->pbn_div;
@@ -4089,6 +4092,9 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
port->connector->base.id, port->connector->name,
port, prev_slots, req_slots);
+ DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] PBN %d -> %d\n",
+ port->connector->base.id, port->connector->name,
+ port, prev_bw, pbn);
/* Add the new allocation to the state */
if (!vcpi) {
@@ -4101,6 +4107,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
list_add(&vcpi->next, &topology_state->vcpis);
}
vcpi->vcpi = req_slots;
+ vcpi->pbn = pbn;
return req_slots;
}
@@ -4677,6 +4684,58 @@ static void drm_dp_mst_destroy_state(struct drm_private_obj *obj,
kfree(mst_state);
}
+static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
+ struct drm_dp_mst_branch *branch)
+{
+ while (port->parent) {
+ if (port->parent == branch)
+ return true;
+
+ if (port->parent->port_parent)
+ port = port->parent->port_parent;
+ else
+ break;
+ }
+ return false;
+}
+
+static inline
+int drm_dp_mst_atomic_check_bw_limit(struct drm_dp_mst_branch *branch,
+ struct drm_dp_mst_topology_state *mst_state)
+{
+ struct drm_dp_mst_port *port;
+ struct drm_dp_vcpi_allocation *vcpi;
+ int pbn_limit = 0, pbn_used = 0;
+
+ list_for_each_entry(port, &branch->ports, next) {
+ if (port->mstb)
+ if (drm_dp_mst_atomic_check_bw_limit(port->mstb, mst_state))
+ return -EINVAL;
+
+ if (port->available_pbn > 0)
+ pbn_limit = port->available_pbn;
+ }
+ DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch has %d PBN available\n",
+ branch, pbn_limit);
+
+ list_for_each_entry(vcpi, &mst_state->vcpis, next) {
+ if (!vcpi->pbn)
+ continue;
+
+ if (drm_dp_mst_port_downstream_of_branch(vcpi->port, branch))
+ pbn_used += vcpi->pbn;
+ }
+ DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch used %d PBN\n",
+ branch, pbn_used);
+
+ if (pbn_used > pbn_limit) {
+ DRM_DEBUG_ATOMIC("[MST BRANCH:%p] No available bandwidth\n",
+ branch);
+ return -EINVAL;
+ }
+ return 0;
+}
+
static inline int
drm_dp_mst_atomic_check_topology_state(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_topology_state *mst_state)
@@ -4808,6 +4867,9 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
ret = drm_dp_mst_atomic_check_topology_state(mgr, mst_state);
if (ret)
break;
+ ret = drm_dp_mst_atomic_check_bw_limit(mgr->mst_primary, mst_state);
+ if (ret)
+ break;
}
return ret;
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 830c94b7f45d..2919d9776af3 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -502,6 +502,7 @@ struct drm_dp_payload {
struct drm_dp_vcpi_allocation {
struct drm_dp_mst_port *port;
int vcpi;
+ int pbn;
bool dsc_enabled;
struct list_head next;
};
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v9 12/18] drm/dp_mst: Add branch bandwidth validation to MST atomic check
2019-12-13 20:08 ` [PATCH v9 12/18] drm/dp_mst: Add branch bandwidth validation to MST atomic check mikita.lipski
@ 2020-01-17 15:09 ` Sean Paul
2020-01-17 15:26 ` Mikita Lipski
0 siblings, 1 reply; 30+ messages in thread
From: Sean Paul @ 2020-01-17 15:09 UTC (permalink / raw)
To: Mikita Lipski; +Cc: Alex Deucher, dri-devel, amd-gfx list
On Fri, Dec 13, 2019 at 3:09 PM <mikita.lipski@amd.com> wrote:
>
> From: Mikita Lipski <mikita.lipski@amd.com>
>
Hi Mikita,
Unfortunately this patch causes a crash on my i915 device when I
unplug my MST hub. The panic is below.
[ 38.514014] BUG: kernel NULL pointer dereference, address: 0000000000000030
[ 38.521801] #PF: supervisor read access in kernel mode
[ 38.527556] #PF: error_code(0x0000) - not-present page
[ 38.533299] PGD 0 P4D 0
[ 38.536127] Oops: 0000 [#1] PREEMPT SMP PTI
[ 38.540798] CPU: 1 PID: 1324 Comm: DrmThread Not tainted
5.5.0-rc6-02273-g9bb4096398e7 #36
[ 38.550040] Hardware name: Google Fizz/Fizz, BIOS
Google_Fizz.10139.39.0 01/04/2018
[ 38.558606] RIP: 0010:drm_dp_mst_atomic_check_bw_limit+0x11/0x102
[ 38.565418] Code: 05 ff cb bf 19 48 f7 f6 c3 0f 1f 44 00 00 55 b8
0b 80 ff 0f 48 89 e5 5d c3 55 48 89 e5 41 57 41 56 41 55 41 54 4c 8d
77 30 53 <48> 8b 47 30 49 89 fd 49 89 f7 45 31 e4 48 8d 58 e8 48 8d 53
18 4c
[ 38.586422] RSP: 0018:ffffc9000139f9d8 EFLAGS: 00010282
[ 38.592264] RAX: 0000000000000000 RBX: ffff888272aeac88 RCX: ffff888236f529e0
[ 38.600242] RDX: ffff888272aeac88 RSI: ffff888236f529e0 RDI: 0000000000000000
[ 38.608220] RBP: ffffc9000139fa00 R08: 0000000000000031 R09: 000000000000000e
[ 38.616198] R10: ffff888236f529e8 R11: ffff8882621f3440 R12: 0000000000000000
[ 38.624176] R13: ffff888236f529d0 R14: 0000000000000030 R15: ffff888236f529e0
[ 38.632153] FS: 00007cd9229ce700(0000) GS:ffff888276c80000(0000)
knlGS:0000000000000000
[ 38.641193] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 38.647616] CR2: 0000000000000030 CR3: 00000002618e8004 CR4: 00000000003606e0
[ 38.655593] Call Trace:
[ 38.658329] drm_dp_mst_atomic_check+0x152/0x16d
[ 38.663484] intel_atomic_check+0xcfe/0x1e6f
[ 38.668259] ? trace_hardirqs_on+0x28/0x3d
[ 38.672835] ? intel_pipe_config_compare+0x1b38/0x1b38
[ 38.678580] drm_atomic_check_only+0x5ab/0x70f
[ 38.683547] ? drm_atomic_set_crtc_for_connector+0xf5/0x102
[ 38.689778] ? drm_atomic_helper_shutdown+0xb6/0xb6
[ 38.695221] drm_atomic_commit+0x18/0x53
[ 38.699604] drm_atomic_helper_set_config+0x5a/0x70
[ 38.705057] drm_mode_setcrtc+0x2ab/0x833
[ 38.709537] ? rcu_read_unlock+0x57/0x57
[ 38.713920] ? drm_mode_getcrtc+0x173/0x173
[ 38.718594] drm_ioctl+0x2e5/0x424
[ 38.722392] ? drm_mode_getcrtc+0x173/0x173
[ 38.727069] vfs_ioctl+0x21/0x2f
[ 38.730675] do_vfs_ioctl+0x5fb/0x61e
[ 38.734766] ksys_ioctl+0x55/0x75
[ 38.738469] __x64_sys_ioctl+0x1a/0x1e
[ 38.742659] do_syscall_64+0x5c/0x6d
[ 38.746653] entry_SYSCALL_64_after_hwframe+0x49/0xbe
[ 38.752298] RIP: 0033:0x7cd92552d497
[ 38.756291] Code: 8a 66 90 48 8b 05 d1 d9 2b 00 64 c7 00 26 00 00
00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00
00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d a1 d9 2b 00 f7 d8 64 89
01 48
[ 38.777296] RSP: 002b:00007cd9229cd698 EFLAGS: 00000246 ORIG_RAX:
0000000000000010
[ 38.785762] RAX: ffffffffffffffda RBX: 000020323373da80 RCX: 00007cd92552d497
[ 38.793740] RDX: 00007cd9229cd6d0 RSI: 00000000c06864a2 RDI: 000000000000001c
[ 38.801717] RBP: 00007cd9229cd6c0 R08: 0000000000000000 R09: 0000000000000000
[ 38.809693] R10: 0000000000000000 R11: 0000000000000246 R12: 000000000000001c
[ 38.817670] R13: 0000000000000000 R14: 00007cd9229cd6d0 R15: 00000000c06864a2
[ 38.825642] Modules linked in: xt_nat cdc_ether r8152 bridge stp
llc usbhid btusb btrtl btbcm btintel bluetooth asix usbnet
ecdh_generic ecc mii snd_soc_hdac_hdmi snd_soc_dmic xhci_pci xhci_hcd
snd_soc_skl snd_soc_sst_ipc snd_soc_sst_dsp snd_hda_ext_core
snd_intel_dspcfg snd_hda_core usbcore usb_common acpi_als kfifo_buf
industrialio xt_MASQUERADE iptable_nat nf_nat xt_mark fuse
ip6table_filter iwlmvm mac80211 r8169 realtek iwlwifi lzo_rle
lzo_compress zram cfg80211
[ 38.871839] CR2: 0000000000000030
[ 38.875542] ---[ end trace 6bb39ec52e30c7cb ]---
[ 38.886142] RIP: 0010:drm_dp_mst_atomic_check_bw_limit+0x11/0x102
[ 38.892957] Code: 05 ff cb bf 19 48 f7 f6 c3 0f 1f 44 00 00 55 b8
0b 80 ff 0f 48 89 e5 5d c3 55 48 89 e5 41 57 41 56 41 55 41 54 4c 8d
77 30 53 <48> 8b 47 30 49 89 fd 49 89 f7 45 31 e4 48 8d 58 e8 48 8d 53
18 4c
[ 38.913964] RSP: 0018:ffffc9000139f9d8 EFLAGS: 00010282
[ 38.919804] RAX: 0000000000000000 RBX: ffff888272aeac88 RCX: ffff888236f529e0
[ 38.927784] RDX: ffff888272aeac88 RSI: ffff888236f529e0 RDI: 0000000000000000
[ 38.935765] RBP: ffffc9000139fa00 R08: 0000000000000031 R09: 000000000000000e
[ 38.943733] R10: ffff888236f529e8 R11: ffff8882621f3440 R12: 0000000000000000
[ 38.951712] R13: ffff888236f529d0 R14: 0000000000000030 R15: ffff888236f529e0
[ 38.959692] FS: 00007cd9229ce700(0000) GS:ffff888276c80000(0000)
knlGS:0000000000000000
[ 38.968730] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 38.975144] CR2: 0000000000000030 CR3: 00000002618e8004 CR4: 00000000003606e0
[ 38.983121] Kernel panic - not syncing: Fatal exception
[ 38.988967] Kernel Offset: disabled
[ 38.998280] ---[ end Kernel panic - not syncing: Fatal exception ]---
> [why]
> Adding PBN attribute to drm_dp_vcpi_allocation structure to
> keep track of how much bandwidth each Port requires.
> Adding drm_dp_mst_atomic_check_bw_limit to verify that
> state's bandwidth needs doesn't exceed available bandwidth.
> The funtion is called in drm_dp_mst_atomic_check after
> drm_dp_mst_atomic_check_topology_state to fully verify that
> the proposed topology is supported.
>
> v2: Fixing some typos and indentations
>
> Reviewed-by: Lyude Paul <lyude@redhat.com>
> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 66 ++++++++++++++++++++++++++-
> include/drm/drm_dp_mst_helper.h | 1 +
> 2 files changed, 65 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 7cd505e771ff..f8b72ac79c66 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -4052,7 +4052,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> {
> struct drm_dp_mst_topology_state *topology_state;
> struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
> - int prev_slots, req_slots;
> + int prev_slots, prev_bw, req_slots;
>
> topology_state = drm_atomic_get_mst_topology_state(state, mgr);
> if (IS_ERR(topology_state))
> @@ -4063,6 +4063,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> if (pos->port == port) {
> vcpi = pos;
> prev_slots = vcpi->vcpi;
> + prev_bw = vcpi->pbn;
>
> /*
> * This should never happen, unless the driver tries
> @@ -4078,8 +4079,10 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> break;
> }
> }
> - if (!vcpi)
> + if (!vcpi) {
> prev_slots = 0;
> + prev_bw = 0;
> + }
>
> if (pbn_div <= 0)
> pbn_div = mgr->pbn_div;
> @@ -4089,6 +4092,9 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
> port->connector->base.id, port->connector->name,
> port, prev_slots, req_slots);
> + DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] PBN %d -> %d\n",
> + port->connector->base.id, port->connector->name,
> + port, prev_bw, pbn);
>
> /* Add the new allocation to the state */
> if (!vcpi) {
> @@ -4101,6 +4107,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> list_add(&vcpi->next, &topology_state->vcpis);
> }
> vcpi->vcpi = req_slots;
> + vcpi->pbn = pbn;
>
> return req_slots;
> }
> @@ -4677,6 +4684,58 @@ static void drm_dp_mst_destroy_state(struct drm_private_obj *obj,
> kfree(mst_state);
> }
>
> +static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
> + struct drm_dp_mst_branch *branch)
> +{
> + while (port->parent) {
> + if (port->parent == branch)
> + return true;
> +
> + if (port->parent->port_parent)
> + port = port->parent->port_parent;
> + else
> + break;
> + }
> + return false;
> +}
> +
> +static inline
> +int drm_dp_mst_atomic_check_bw_limit(struct drm_dp_mst_branch *branch,
> + struct drm_dp_mst_topology_state *mst_state)
> +{
> + struct drm_dp_mst_port *port;
> + struct drm_dp_vcpi_allocation *vcpi;
> + int pbn_limit = 0, pbn_used = 0;
> +
> + list_for_each_entry(port, &branch->ports, next) {
> + if (port->mstb)
> + if (drm_dp_mst_atomic_check_bw_limit(port->mstb, mst_state))
> + return -EINVAL;
> +
> + if (port->available_pbn > 0)
> + pbn_limit = port->available_pbn;
> + }
> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch has %d PBN available\n",
> + branch, pbn_limit);
> +
> + list_for_each_entry(vcpi, &mst_state->vcpis, next) {
> + if (!vcpi->pbn)
> + continue;
> +
> + if (drm_dp_mst_port_downstream_of_branch(vcpi->port, branch))
> + pbn_used += vcpi->pbn;
> + }
> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch used %d PBN\n",
> + branch, pbn_used);
> +
> + if (pbn_used > pbn_limit) {
> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] No available bandwidth\n",
> + branch);
> + return -EINVAL;
> + }
> + return 0;
> +}
> +
> static inline int
> drm_dp_mst_atomic_check_topology_state(struct drm_dp_mst_topology_mgr *mgr,
> struct drm_dp_mst_topology_state *mst_state)
> @@ -4808,6 +4867,9 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
> ret = drm_dp_mst_atomic_check_topology_state(mgr, mst_state);
> if (ret)
> break;
> + ret = drm_dp_mst_atomic_check_bw_limit(mgr->mst_primary, mst_state);
> + if (ret)
> + break;
> }
>
> return ret;
> diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
> index 830c94b7f45d..2919d9776af3 100644
> --- a/include/drm/drm_dp_mst_helper.h
> +++ b/include/drm/drm_dp_mst_helper.h
> @@ -502,6 +502,7 @@ struct drm_dp_payload {
> struct drm_dp_vcpi_allocation {
> struct drm_dp_mst_port *port;
> int vcpi;
> + int pbn;
> bool dsc_enabled;
> struct list_head next;
> };
> --
> 2.17.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v9 12/18] drm/dp_mst: Add branch bandwidth validation to MST atomic check
2020-01-17 15:09 ` Sean Paul
@ 2020-01-17 15:26 ` Mikita Lipski
2020-01-17 15:39 ` Sean Paul
0 siblings, 1 reply; 30+ messages in thread
From: Mikita Lipski @ 2020-01-17 15:26 UTC (permalink / raw)
To: Sean Paul, Mikita Lipski; +Cc: Alex Deucher, dri-devel, amd-gfx list
On 1/17/20 10:09 AM, Sean Paul wrote:
> On Fri, Dec 13, 2019 at 3:09 PM <mikita.lipski@amd.com> wrote:
>>
>> From: Mikita Lipski <mikita.lipski@amd.com>
>>
>
> Hi Mikita,
> Unfortunately this patch causes a crash on my i915 device when I
> unplug my MST hub. The panic is below.
Hi Sean,
I thought this issue was fixed by Wayne Lin in
https://patchwork.freedesktop.org/patch/346736/?series=71388&rev=1
but now I checked it seems it never got pushed. I will resend Wayne's
patch once again.
Thanks
Mikita
>
> [ 38.514014] BUG: kernel NULL pointer dereference, address: 0000000000000030
> [ 38.521801] #PF: supervisor read access in kernel mode
> [ 38.527556] #PF: error_code(0x0000) - not-present page
> [ 38.533299] PGD 0 P4D 0
> [ 38.536127] Oops: 0000 [#1] PREEMPT SMP PTI
> [ 38.540798] CPU: 1 PID: 1324 Comm: DrmThread Not tainted
> 5.5.0-rc6-02273-g9bb4096398e7 #36
> [ 38.550040] Hardware name: Google Fizz/Fizz, BIOS
> Google_Fizz.10139.39.0 01/04/2018
> [ 38.558606] RIP: 0010:drm_dp_mst_atomic_check_bw_limit+0x11/0x102
> [ 38.565418] Code: 05 ff cb bf 19 48 f7 f6 c3 0f 1f 44 00 00 55 b8
> 0b 80 ff 0f 48 89 e5 5d c3 55 48 89 e5 41 57 41 56 41 55 41 54 4c 8d
> 77 30 53 <48> 8b 47 30 49 89 fd 49 89 f7 45 31 e4 48 8d 58 e8 48 8d 53
> 18 4c
> [ 38.586422] RSP: 0018:ffffc9000139f9d8 EFLAGS: 00010282
> [ 38.592264] RAX: 0000000000000000 RBX: ffff888272aeac88 RCX: ffff888236f529e0
> [ 38.600242] RDX: ffff888272aeac88 RSI: ffff888236f529e0 RDI: 0000000000000000
> [ 38.608220] RBP: ffffc9000139fa00 R08: 0000000000000031 R09: 000000000000000e
> [ 38.616198] R10: ffff888236f529e8 R11: ffff8882621f3440 R12: 0000000000000000
> [ 38.624176] R13: ffff888236f529d0 R14: 0000000000000030 R15: ffff888236f529e0
> [ 38.632153] FS: 00007cd9229ce700(0000) GS:ffff888276c80000(0000)
> knlGS:0000000000000000
> [ 38.641193] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 38.647616] CR2: 0000000000000030 CR3: 00000002618e8004 CR4: 00000000003606e0
> [ 38.655593] Call Trace:
> [ 38.658329] drm_dp_mst_atomic_check+0x152/0x16d
> [ 38.663484] intel_atomic_check+0xcfe/0x1e6f
> [ 38.668259] ? trace_hardirqs_on+0x28/0x3d
> [ 38.672835] ? intel_pipe_config_compare+0x1b38/0x1b38
> [ 38.678580] drm_atomic_check_only+0x5ab/0x70f
> [ 38.683547] ? drm_atomic_set_crtc_for_connector+0xf5/0x102
> [ 38.689778] ? drm_atomic_helper_shutdown+0xb6/0xb6
> [ 38.695221] drm_atomic_commit+0x18/0x53
> [ 38.699604] drm_atomic_helper_set_config+0x5a/0x70
> [ 38.705057] drm_mode_setcrtc+0x2ab/0x833
> [ 38.709537] ? rcu_read_unlock+0x57/0x57
> [ 38.713920] ? drm_mode_getcrtc+0x173/0x173
> [ 38.718594] drm_ioctl+0x2e5/0x424
> [ 38.722392] ? drm_mode_getcrtc+0x173/0x173
> [ 38.727069] vfs_ioctl+0x21/0x2f
> [ 38.730675] do_vfs_ioctl+0x5fb/0x61e
> [ 38.734766] ksys_ioctl+0x55/0x75
> [ 38.738469] __x64_sys_ioctl+0x1a/0x1e
> [ 38.742659] do_syscall_64+0x5c/0x6d
> [ 38.746653] entry_SYSCALL_64_after_hwframe+0x49/0xbe
> [ 38.752298] RIP: 0033:0x7cd92552d497
> [ 38.756291] Code: 8a 66 90 48 8b 05 d1 d9 2b 00 64 c7 00 26 00 00
> 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00
> 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d a1 d9 2b 00 f7 d8 64 89
> 01 48
> [ 38.777296] RSP: 002b:00007cd9229cd698 EFLAGS: 00000246 ORIG_RAX:
> 0000000000000010
> [ 38.785762] RAX: ffffffffffffffda RBX: 000020323373da80 RCX: 00007cd92552d497
> [ 38.793740] RDX: 00007cd9229cd6d0 RSI: 00000000c06864a2 RDI: 000000000000001c
> [ 38.801717] RBP: 00007cd9229cd6c0 R08: 0000000000000000 R09: 0000000000000000
> [ 38.809693] R10: 0000000000000000 R11: 0000000000000246 R12: 000000000000001c
> [ 38.817670] R13: 0000000000000000 R14: 00007cd9229cd6d0 R15: 00000000c06864a2
> [ 38.825642] Modules linked in: xt_nat cdc_ether r8152 bridge stp
> llc usbhid btusb btrtl btbcm btintel bluetooth asix usbnet
> ecdh_generic ecc mii snd_soc_hdac_hdmi snd_soc_dmic xhci_pci xhci_hcd
> snd_soc_skl snd_soc_sst_ipc snd_soc_sst_dsp snd_hda_ext_core
> snd_intel_dspcfg snd_hda_core usbcore usb_common acpi_als kfifo_buf
> industrialio xt_MASQUERADE iptable_nat nf_nat xt_mark fuse
> ip6table_filter iwlmvm mac80211 r8169 realtek iwlwifi lzo_rle
> lzo_compress zram cfg80211
> [ 38.871839] CR2: 0000000000000030
> [ 38.875542] ---[ end trace 6bb39ec52e30c7cb ]---
> [ 38.886142] RIP: 0010:drm_dp_mst_atomic_check_bw_limit+0x11/0x102
> [ 38.892957] Code: 05 ff cb bf 19 48 f7 f6 c3 0f 1f 44 00 00 55 b8
> 0b 80 ff 0f 48 89 e5 5d c3 55 48 89 e5 41 57 41 56 41 55 41 54 4c 8d
> 77 30 53 <48> 8b 47 30 49 89 fd 49 89 f7 45 31 e4 48 8d 58 e8 48 8d 53
> 18 4c
> [ 38.913964] RSP: 0018:ffffc9000139f9d8 EFLAGS: 00010282
> [ 38.919804] RAX: 0000000000000000 RBX: ffff888272aeac88 RCX: ffff888236f529e0
> [ 38.927784] RDX: ffff888272aeac88 RSI: ffff888236f529e0 RDI: 0000000000000000
> [ 38.935765] RBP: ffffc9000139fa00 R08: 0000000000000031 R09: 000000000000000e
> [ 38.943733] R10: ffff888236f529e8 R11: ffff8882621f3440 R12: 0000000000000000
> [ 38.951712] R13: ffff888236f529d0 R14: 0000000000000030 R15: ffff888236f529e0
> [ 38.959692] FS: 00007cd9229ce700(0000) GS:ffff888276c80000(0000)
> knlGS:0000000000000000
> [ 38.968730] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 38.975144] CR2: 0000000000000030 CR3: 00000002618e8004 CR4: 00000000003606e0
> [ 38.983121] Kernel panic - not syncing: Fatal exception
> [ 38.988967] Kernel Offset: disabled
> [ 38.998280] ---[ end Kernel panic - not syncing: Fatal exception ]---
>
>
>
>
>
>
>> [why]
>> Adding PBN attribute to drm_dp_vcpi_allocation structure to
>> keep track of how much bandwidth each Port requires.
>> Adding drm_dp_mst_atomic_check_bw_limit to verify that
>> state's bandwidth needs doesn't exceed available bandwidth.
>> The funtion is called in drm_dp_mst_atomic_check after
>> drm_dp_mst_atomic_check_topology_state to fully verify that
>> the proposed topology is supported.
>>
>> v2: Fixing some typos and indentations
>>
>> Reviewed-by: Lyude Paul <lyude@redhat.com>
>> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
>> ---
>> drivers/gpu/drm/drm_dp_mst_topology.c | 66 ++++++++++++++++++++++++++-
>> include/drm/drm_dp_mst_helper.h | 1 +
>> 2 files changed, 65 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
>> index 7cd505e771ff..f8b72ac79c66 100644
>> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
>> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
>> @@ -4052,7 +4052,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
>> {
>> struct drm_dp_mst_topology_state *topology_state;
>> struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
>> - int prev_slots, req_slots;
>> + int prev_slots, prev_bw, req_slots;
>>
>> topology_state = drm_atomic_get_mst_topology_state(state, mgr);
>> if (IS_ERR(topology_state))
>> @@ -4063,6 +4063,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
>> if (pos->port == port) {
>> vcpi = pos;
>> prev_slots = vcpi->vcpi;
>> + prev_bw = vcpi->pbn;
>>
>> /*
>> * This should never happen, unless the driver tries
>> @@ -4078,8 +4079,10 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
>> break;
>> }
>> }
>> - if (!vcpi)
>> + if (!vcpi) {
>> prev_slots = 0;
>> + prev_bw = 0;
>> + }
>>
>> if (pbn_div <= 0)
>> pbn_div = mgr->pbn_div;
>> @@ -4089,6 +4092,9 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
>> DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
>> port->connector->base.id, port->connector->name,
>> port, prev_slots, req_slots);
>> + DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] PBN %d -> %d\n",
>> + port->connector->base.id, port->connector->name,
>> + port, prev_bw, pbn);
>>
>> /* Add the new allocation to the state */
>> if (!vcpi) {
>> @@ -4101,6 +4107,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
>> list_add(&vcpi->next, &topology_state->vcpis);
>> }
>> vcpi->vcpi = req_slots;
>> + vcpi->pbn = pbn;
>>
>> return req_slots;
>> }
>> @@ -4677,6 +4684,58 @@ static void drm_dp_mst_destroy_state(struct drm_private_obj *obj,
>> kfree(mst_state);
>> }
>>
>> +static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
>> + struct drm_dp_mst_branch *branch)
>> +{
>> + while (port->parent) {
>> + if (port->parent == branch)
>> + return true;
>> +
>> + if (port->parent->port_parent)
>> + port = port->parent->port_parent;
>> + else
>> + break;
>> + }
>> + return false;
>> +}
>> +
>> +static inline
>> +int drm_dp_mst_atomic_check_bw_limit(struct drm_dp_mst_branch *branch,
>> + struct drm_dp_mst_topology_state *mst_state)
>> +{
>> + struct drm_dp_mst_port *port;
>> + struct drm_dp_vcpi_allocation *vcpi;
>> + int pbn_limit = 0, pbn_used = 0;
>> +
>> + list_for_each_entry(port, &branch->ports, next) {
>> + if (port->mstb)
>> + if (drm_dp_mst_atomic_check_bw_limit(port->mstb, mst_state))
>> + return -EINVAL;
>> +
>> + if (port->available_pbn > 0)
>> + pbn_limit = port->available_pbn;
>> + }
>> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch has %d PBN available\n",
>> + branch, pbn_limit);
>> +
>> + list_for_each_entry(vcpi, &mst_state->vcpis, next) {
>> + if (!vcpi->pbn)
>> + continue;
>> +
>> + if (drm_dp_mst_port_downstream_of_branch(vcpi->port, branch))
>> + pbn_used += vcpi->pbn;
>> + }
>> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch used %d PBN\n",
>> + branch, pbn_used);
>> +
>> + if (pbn_used > pbn_limit) {
>> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] No available bandwidth\n",
>> + branch);
>> + return -EINVAL;
>> + }
>> + return 0;
>> +}
>> +
>> static inline int
>> drm_dp_mst_atomic_check_topology_state(struct drm_dp_mst_topology_mgr *mgr,
>> struct drm_dp_mst_topology_state *mst_state)
>> @@ -4808,6 +4867,9 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
>> ret = drm_dp_mst_atomic_check_topology_state(mgr, mst_state);
>> if (ret)
>> break;
>> + ret = drm_dp_mst_atomic_check_bw_limit(mgr->mst_primary, mst_state);
>> + if (ret)
>> + break;
>> }
>>
>> return ret;
>> diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
>> index 830c94b7f45d..2919d9776af3 100644
>> --- a/include/drm/drm_dp_mst_helper.h
>> +++ b/include/drm/drm_dp_mst_helper.h
>> @@ -502,6 +502,7 @@ struct drm_dp_payload {
>> struct drm_dp_vcpi_allocation {
>> struct drm_dp_mst_port *port;
>> int vcpi;
>> + int pbn;
>> bool dsc_enabled;
>> struct list_head next;
>> };
>> --
>> 2.17.1
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=02%7C01%7Cmikita.lipski%40amd.com%7C2b736cb4c0f1456691ec08d79b5f4c69%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637148705931074877&sdata=s4q0ni0H%2FiPgonlMMK9Od7UK5M%2FC%2F0rsQEGsr1FP0XU%3D&reserved=0
--
Thanks,
Mikita Lipski
Software Engineer 2, AMD
mikita.lipski@amd.com
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v9 12/18] drm/dp_mst: Add branch bandwidth validation to MST atomic check
2020-01-17 15:26 ` Mikita Lipski
@ 2020-01-17 15:39 ` Sean Paul
2020-01-17 20:26 ` Lyude Paul
0 siblings, 1 reply; 30+ messages in thread
From: Sean Paul @ 2020-01-17 15:39 UTC (permalink / raw)
To: Mikita Lipski; +Cc: Alex Deucher, Mikita Lipski, dri-devel, amd-gfx list
On Fri, Jan 17, 2020 at 10:26 AM Mikita Lipski <mlipski@amd.com> wrote:
>
>
>
> On 1/17/20 10:09 AM, Sean Paul wrote:
> > On Fri, Dec 13, 2019 at 3:09 PM <mikita.lipski@amd.com> wrote:
> >>
> >> From: Mikita Lipski <mikita.lipski@amd.com>
> >>
> >
> > Hi Mikita,
> > Unfortunately this patch causes a crash on my i915 device when I
> > unplug my MST hub. The panic is below.
>
> Hi Sean,
>
> I thought this issue was fixed by Wayne Lin in
> https://patchwork.freedesktop.org/patch/346736/?series=71388&rev=1
> but now I checked it seems it never got pushed. I will resend Wayne's
> patch once again.
>
No need to resend, I can push Wayne's patch.
Thanks for the pointer,
Sean
> Thanks
> Mikita
> >
> > [ 38.514014] BUG: kernel NULL pointer dereference, address: 0000000000000030
> > [ 38.521801] #PF: supervisor read access in kernel mode
> > [ 38.527556] #PF: error_code(0x0000) - not-present page
> > [ 38.533299] PGD 0 P4D 0
> > [ 38.536127] Oops: 0000 [#1] PREEMPT SMP PTI
> > [ 38.540798] CPU: 1 PID: 1324 Comm: DrmThread Not tainted
> > 5.5.0-rc6-02273-g9bb4096398e7 #36
> > [ 38.550040] Hardware name: Google Fizz/Fizz, BIOS
> > Google_Fizz.10139.39.0 01/04/2018
> > [ 38.558606] RIP: 0010:drm_dp_mst_atomic_check_bw_limit+0x11/0x102
> > [ 38.565418] Code: 05 ff cb bf 19 48 f7 f6 c3 0f 1f 44 00 00 55 b8
> > 0b 80 ff 0f 48 89 e5 5d c3 55 48 89 e5 41 57 41 56 41 55 41 54 4c 8d
> > 77 30 53 <48> 8b 47 30 49 89 fd 49 89 f7 45 31 e4 48 8d 58 e8 48 8d 53
> > 18 4c
> > [ 38.586422] RSP: 0018:ffffc9000139f9d8 EFLAGS: 00010282
> > [ 38.592264] RAX: 0000000000000000 RBX: ffff888272aeac88 RCX: ffff888236f529e0
> > [ 38.600242] RDX: ffff888272aeac88 RSI: ffff888236f529e0 RDI: 0000000000000000
> > [ 38.608220] RBP: ffffc9000139fa00 R08: 0000000000000031 R09: 000000000000000e
> > [ 38.616198] R10: ffff888236f529e8 R11: ffff8882621f3440 R12: 0000000000000000
> > [ 38.624176] R13: ffff888236f529d0 R14: 0000000000000030 R15: ffff888236f529e0
> > [ 38.632153] FS: 00007cd9229ce700(0000) GS:ffff888276c80000(0000)
> > knlGS:0000000000000000
> > [ 38.641193] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > [ 38.647616] CR2: 0000000000000030 CR3: 00000002618e8004 CR4: 00000000003606e0
> > [ 38.655593] Call Trace:
> > [ 38.658329] drm_dp_mst_atomic_check+0x152/0x16d
> > [ 38.663484] intel_atomic_check+0xcfe/0x1e6f
> > [ 38.668259] ? trace_hardirqs_on+0x28/0x3d
> > [ 38.672835] ? intel_pipe_config_compare+0x1b38/0x1b38
> > [ 38.678580] drm_atomic_check_only+0x5ab/0x70f
> > [ 38.683547] ? drm_atomic_set_crtc_for_connector+0xf5/0x102
> > [ 38.689778] ? drm_atomic_helper_shutdown+0xb6/0xb6
> > [ 38.695221] drm_atomic_commit+0x18/0x53
> > [ 38.699604] drm_atomic_helper_set_config+0x5a/0x70
> > [ 38.705057] drm_mode_setcrtc+0x2ab/0x833
> > [ 38.709537] ? rcu_read_unlock+0x57/0x57
> > [ 38.713920] ? drm_mode_getcrtc+0x173/0x173
> > [ 38.718594] drm_ioctl+0x2e5/0x424
> > [ 38.722392] ? drm_mode_getcrtc+0x173/0x173
> > [ 38.727069] vfs_ioctl+0x21/0x2f
> > [ 38.730675] do_vfs_ioctl+0x5fb/0x61e
> > [ 38.734766] ksys_ioctl+0x55/0x75
> > [ 38.738469] __x64_sys_ioctl+0x1a/0x1e
> > [ 38.742659] do_syscall_64+0x5c/0x6d
> > [ 38.746653] entry_SYSCALL_64_after_hwframe+0x49/0xbe
> > [ 38.752298] RIP: 0033:0x7cd92552d497
> > [ 38.756291] Code: 8a 66 90 48 8b 05 d1 d9 2b 00 64 c7 00 26 00 00
> > 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00
> > 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d a1 d9 2b 00 f7 d8 64 89
> > 01 48
> > [ 38.777296] RSP: 002b:00007cd9229cd698 EFLAGS: 00000246 ORIG_RAX:
> > 0000000000000010
> > [ 38.785762] RAX: ffffffffffffffda RBX: 000020323373da80 RCX: 00007cd92552d497
> > [ 38.793740] RDX: 00007cd9229cd6d0 RSI: 00000000c06864a2 RDI: 000000000000001c
> > [ 38.801717] RBP: 00007cd9229cd6c0 R08: 0000000000000000 R09: 0000000000000000
> > [ 38.809693] R10: 0000000000000000 R11: 0000000000000246 R12: 000000000000001c
> > [ 38.817670] R13: 0000000000000000 R14: 00007cd9229cd6d0 R15: 00000000c06864a2
> > [ 38.825642] Modules linked in: xt_nat cdc_ether r8152 bridge stp
> > llc usbhid btusb btrtl btbcm btintel bluetooth asix usbnet
> > ecdh_generic ecc mii snd_soc_hdac_hdmi snd_soc_dmic xhci_pci xhci_hcd
> > snd_soc_skl snd_soc_sst_ipc snd_soc_sst_dsp snd_hda_ext_core
> > snd_intel_dspcfg snd_hda_core usbcore usb_common acpi_als kfifo_buf
> > industrialio xt_MASQUERADE iptable_nat nf_nat xt_mark fuse
> > ip6table_filter iwlmvm mac80211 r8169 realtek iwlwifi lzo_rle
> > lzo_compress zram cfg80211
> > [ 38.871839] CR2: 0000000000000030
> > [ 38.875542] ---[ end trace 6bb39ec52e30c7cb ]---
> > [ 38.886142] RIP: 0010:drm_dp_mst_atomic_check_bw_limit+0x11/0x102
> > [ 38.892957] Code: 05 ff cb bf 19 48 f7 f6 c3 0f 1f 44 00 00 55 b8
> > 0b 80 ff 0f 48 89 e5 5d c3 55 48 89 e5 41 57 41 56 41 55 41 54 4c 8d
> > 77 30 53 <48> 8b 47 30 49 89 fd 49 89 f7 45 31 e4 48 8d 58 e8 48 8d 53
> > 18 4c
> > [ 38.913964] RSP: 0018:ffffc9000139f9d8 EFLAGS: 00010282
> > [ 38.919804] RAX: 0000000000000000 RBX: ffff888272aeac88 RCX: ffff888236f529e0
> > [ 38.927784] RDX: ffff888272aeac88 RSI: ffff888236f529e0 RDI: 0000000000000000
> > [ 38.935765] RBP: ffffc9000139fa00 R08: 0000000000000031 R09: 000000000000000e
> > [ 38.943733] R10: ffff888236f529e8 R11: ffff8882621f3440 R12: 0000000000000000
> > [ 38.951712] R13: ffff888236f529d0 R14: 0000000000000030 R15: ffff888236f529e0
> > [ 38.959692] FS: 00007cd9229ce700(0000) GS:ffff888276c80000(0000)
> > knlGS:0000000000000000
> > [ 38.968730] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > [ 38.975144] CR2: 0000000000000030 CR3: 00000002618e8004 CR4: 00000000003606e0
> > [ 38.983121] Kernel panic - not syncing: Fatal exception
> > [ 38.988967] Kernel Offset: disabled
> > [ 38.998280] ---[ end Kernel panic - not syncing: Fatal exception ]---
> >
> >
> >
> >
> >
> >
> >> [why]
> >> Adding PBN attribute to drm_dp_vcpi_allocation structure to
> >> keep track of how much bandwidth each Port requires.
> >> Adding drm_dp_mst_atomic_check_bw_limit to verify that
> >> state's bandwidth needs doesn't exceed available bandwidth.
> >> The funtion is called in drm_dp_mst_atomic_check after
> >> drm_dp_mst_atomic_check_topology_state to fully verify that
> >> the proposed topology is supported.
> >>
> >> v2: Fixing some typos and indentations
> >>
> >> Reviewed-by: Lyude Paul <lyude@redhat.com>
> >> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> >> ---
> >> drivers/gpu/drm/drm_dp_mst_topology.c | 66 ++++++++++++++++++++++++++-
> >> include/drm/drm_dp_mst_helper.h | 1 +
> >> 2 files changed, 65 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
> >> index 7cd505e771ff..f8b72ac79c66 100644
> >> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> >> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> >> @@ -4052,7 +4052,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> >> {
> >> struct drm_dp_mst_topology_state *topology_state;
> >> struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
> >> - int prev_slots, req_slots;
> >> + int prev_slots, prev_bw, req_slots;
> >>
> >> topology_state = drm_atomic_get_mst_topology_state(state, mgr);
> >> if (IS_ERR(topology_state))
> >> @@ -4063,6 +4063,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> >> if (pos->port == port) {
> >> vcpi = pos;
> >> prev_slots = vcpi->vcpi;
> >> + prev_bw = vcpi->pbn;
> >>
> >> /*
> >> * This should never happen, unless the driver tries
> >> @@ -4078,8 +4079,10 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> >> break;
> >> }
> >> }
> >> - if (!vcpi)
> >> + if (!vcpi) {
> >> prev_slots = 0;
> >> + prev_bw = 0;
> >> + }
> >>
> >> if (pbn_div <= 0)
> >> pbn_div = mgr->pbn_div;
> >> @@ -4089,6 +4092,9 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> >> DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
> >> port->connector->base.id, port->connector->name,
> >> port, prev_slots, req_slots);
> >> + DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] PBN %d -> %d\n",
> >> + port->connector->base.id, port->connector->name,
> >> + port, prev_bw, pbn);
> >>
> >> /* Add the new allocation to the state */
> >> if (!vcpi) {
> >> @@ -4101,6 +4107,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> >> list_add(&vcpi->next, &topology_state->vcpis);
> >> }
> >> vcpi->vcpi = req_slots;
> >> + vcpi->pbn = pbn;
> >>
> >> return req_slots;
> >> }
> >> @@ -4677,6 +4684,58 @@ static void drm_dp_mst_destroy_state(struct drm_private_obj *obj,
> >> kfree(mst_state);
> >> }
> >>
> >> +static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
> >> + struct drm_dp_mst_branch *branch)
> >> +{
> >> + while (port->parent) {
> >> + if (port->parent == branch)
> >> + return true;
> >> +
> >> + if (port->parent->port_parent)
> >> + port = port->parent->port_parent;
> >> + else
> >> + break;
> >> + }
> >> + return false;
> >> +}
> >> +
> >> +static inline
> >> +int drm_dp_mst_atomic_check_bw_limit(struct drm_dp_mst_branch *branch,
> >> + struct drm_dp_mst_topology_state *mst_state)
> >> +{
> >> + struct drm_dp_mst_port *port;
> >> + struct drm_dp_vcpi_allocation *vcpi;
> >> + int pbn_limit = 0, pbn_used = 0;
> >> +
> >> + list_for_each_entry(port, &branch->ports, next) {
> >> + if (port->mstb)
> >> + if (drm_dp_mst_atomic_check_bw_limit(port->mstb, mst_state))
> >> + return -EINVAL;
> >> +
> >> + if (port->available_pbn > 0)
> >> + pbn_limit = port->available_pbn;
> >> + }
> >> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch has %d PBN available\n",
> >> + branch, pbn_limit);
> >> +
> >> + list_for_each_entry(vcpi, &mst_state->vcpis, next) {
> >> + if (!vcpi->pbn)
> >> + continue;
> >> +
> >> + if (drm_dp_mst_port_downstream_of_branch(vcpi->port, branch))
> >> + pbn_used += vcpi->pbn;
> >> + }
> >> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch used %d PBN\n",
> >> + branch, pbn_used);
> >> +
> >> + if (pbn_used > pbn_limit) {
> >> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] No available bandwidth\n",
> >> + branch);
> >> + return -EINVAL;
> >> + }
> >> + return 0;
> >> +}
> >> +
> >> static inline int
> >> drm_dp_mst_atomic_check_topology_state(struct drm_dp_mst_topology_mgr *mgr,
> >> struct drm_dp_mst_topology_state *mst_state)
> >> @@ -4808,6 +4867,9 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
> >> ret = drm_dp_mst_atomic_check_topology_state(mgr, mst_state);
> >> if (ret)
> >> break;
> >> + ret = drm_dp_mst_atomic_check_bw_limit(mgr->mst_primary, mst_state);
> >> + if (ret)
> >> + break;
> >> }
> >>
> >> return ret;
> >> diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
> >> index 830c94b7f45d..2919d9776af3 100644
> >> --- a/include/drm/drm_dp_mst_helper.h
> >> +++ b/include/drm/drm_dp_mst_helper.h
> >> @@ -502,6 +502,7 @@ struct drm_dp_payload {
> >> struct drm_dp_vcpi_allocation {
> >> struct drm_dp_mst_port *port;
> >> int vcpi;
> >> + int pbn;
> >> bool dsc_enabled;
> >> struct list_head next;
> >> };
> >> --
> >> 2.17.1
> >>
> >> _______________________________________________
> >> dri-devel mailing list
> >> dri-devel@lists.freedesktop.org
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=02%7C01%7Cmikita.lipski%40amd.com%7C2b736cb4c0f1456691ec08d79b5f4c69%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637148705931074877&sdata=s4q0ni0H%2FiPgonlMMK9Od7UK5M%2FC%2F0rsQEGsr1FP0XU%3D&reserved=0
>
> --
> Thanks,
> Mikita Lipski
> Software Engineer 2, AMD
> mikita.lipski@amd.com
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v9 12/18] drm/dp_mst: Add branch bandwidth validation to MST atomic check
2020-01-17 15:39 ` Sean Paul
@ 2020-01-17 20:26 ` Lyude Paul
0 siblings, 0 replies; 30+ messages in thread
From: Lyude Paul @ 2020-01-17 20:26 UTC (permalink / raw)
To: Sean Paul, Mikita Lipski
Cc: Alex Deucher, Mikita Lipski, dri-devel, amd-gfx list
fwiw - https://patchwork.freedesktop.org/patch/349111/ is the proper fix that
I was talking about, we should probably go with that one instead if you
haven't already pushed this
On Fri, 2020-01-17 at 10:39 -0500, Sean Paul wrote:
> On Fri, Jan 17, 2020 at 10:26 AM Mikita Lipski <mlipski@amd.com> wrote:
> >
> >
> > On 1/17/20 10:09 AM, Sean Paul wrote:
> > > On Fri, Dec 13, 2019 at 3:09 PM <mikita.lipski@amd.com> wrote:
> > > > From: Mikita Lipski <mikita.lipski@amd.com>
> > > >
> > >
> > > Hi Mikita,
> > > Unfortunately this patch causes a crash on my i915 device when I
> > > unplug my MST hub. The panic is below.
> >
> > Hi Sean,
> >
> > I thought this issue was fixed by Wayne Lin in
> > https://patchwork.freedesktop.org/patch/346736/?series=71388&rev=1
> > but now I checked it seems it never got pushed. I will resend Wayne's
> > patch once again.
> >
>
> No need to resend, I can push Wayne's patch.
>
> Thanks for the pointer,
>
> Sean
>
> > Thanks
> > Mikita
> > > [ 38.514014] BUG: kernel NULL pointer dereference, address:
> > > 0000000000000030
> > > [ 38.521801] #PF: supervisor read access in kernel mode
> > > [ 38.527556] #PF: error_code(0x0000) - not-present page
> > > [ 38.533299] PGD 0 P4D 0
> > > [ 38.536127] Oops: 0000 [#1] PREEMPT SMP PTI
> > > [ 38.540798] CPU: 1 PID: 1324 Comm: DrmThread Not tainted
> > > 5.5.0-rc6-02273-g9bb4096398e7 #36
> > > [ 38.550040] Hardware name: Google Fizz/Fizz, BIOS
> > > Google_Fizz.10139.39.0 01/04/2018
> > > [ 38.558606] RIP: 0010:drm_dp_mst_atomic_check_bw_limit+0x11/0x102
> > > [ 38.565418] Code: 05 ff cb bf 19 48 f7 f6 c3 0f 1f 44 00 00 55 b8
> > > 0b 80 ff 0f 48 89 e5 5d c3 55 48 89 e5 41 57 41 56 41 55 41 54 4c 8d
> > > 77 30 53 <48> 8b 47 30 49 89 fd 49 89 f7 45 31 e4 48 8d 58 e8 48 8d 53
> > > 18 4c
> > > [ 38.586422] RSP: 0018:ffffc9000139f9d8 EFLAGS: 00010282
> > > [ 38.592264] RAX: 0000000000000000 RBX: ffff888272aeac88 RCX:
> > > ffff888236f529e0
> > > [ 38.600242] RDX: ffff888272aeac88 RSI: ffff888236f529e0 RDI:
> > > 0000000000000000
> > > [ 38.608220] RBP: ffffc9000139fa00 R08: 0000000000000031 R09:
> > > 000000000000000e
> > > [ 38.616198] R10: ffff888236f529e8 R11: ffff8882621f3440 R12:
> > > 0000000000000000
> > > [ 38.624176] R13: ffff888236f529d0 R14: 0000000000000030 R15:
> > > ffff888236f529e0
> > > [ 38.632153] FS: 00007cd9229ce700(0000) GS:ffff888276c80000(0000)
> > > knlGS:0000000000000000
> > > [ 38.641193] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > > [ 38.647616] CR2: 0000000000000030 CR3: 00000002618e8004 CR4:
> > > 00000000003606e0
> > > [ 38.655593] Call Trace:
> > > [ 38.658329] drm_dp_mst_atomic_check+0x152/0x16d
> > > [ 38.663484] intel_atomic_check+0xcfe/0x1e6f
> > > [ 38.668259] ? trace_hardirqs_on+0x28/0x3d
> > > [ 38.672835] ? intel_pipe_config_compare+0x1b38/0x1b38
> > > [ 38.678580] drm_atomic_check_only+0x5ab/0x70f
> > > [ 38.683547] ? drm_atomic_set_crtc_for_connector+0xf5/0x102
> > > [ 38.689778] ? drm_atomic_helper_shutdown+0xb6/0xb6
> > > [ 38.695221] drm_atomic_commit+0x18/0x53
> > > [ 38.699604] drm_atomic_helper_set_config+0x5a/0x70
> > > [ 38.705057] drm_mode_setcrtc+0x2ab/0x833
> > > [ 38.709537] ? rcu_read_unlock+0x57/0x57
> > > [ 38.713920] ? drm_mode_getcrtc+0x173/0x173
> > > [ 38.718594] drm_ioctl+0x2e5/0x424
> > > [ 38.722392] ? drm_mode_getcrtc+0x173/0x173
> > > [ 38.727069] vfs_ioctl+0x21/0x2f
> > > [ 38.730675] do_vfs_ioctl+0x5fb/0x61e
> > > [ 38.734766] ksys_ioctl+0x55/0x75
> > > [ 38.738469] __x64_sys_ioctl+0x1a/0x1e
> > > [ 38.742659] do_syscall_64+0x5c/0x6d
> > > [ 38.746653] entry_SYSCALL_64_after_hwframe+0x49/0xbe
> > > [ 38.752298] RIP: 0033:0x7cd92552d497
> > > [ 38.756291] Code: 8a 66 90 48 8b 05 d1 d9 2b 00 64 c7 00 26 00 00
> > > 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00
> > > 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d a1 d9 2b 00 f7 d8 64 89
> > > 01 48
> > > [ 38.777296] RSP: 002b:00007cd9229cd698 EFLAGS: 00000246 ORIG_RAX:
> > > 0000000000000010
> > > [ 38.785762] RAX: ffffffffffffffda RBX: 000020323373da80 RCX:
> > > 00007cd92552d497
> > > [ 38.793740] RDX: 00007cd9229cd6d0 RSI: 00000000c06864a2 RDI:
> > > 000000000000001c
> > > [ 38.801717] RBP: 00007cd9229cd6c0 R08: 0000000000000000 R09:
> > > 0000000000000000
> > > [ 38.809693] R10: 0000000000000000 R11: 0000000000000246 R12:
> > > 000000000000001c
> > > [ 38.817670] R13: 0000000000000000 R14: 00007cd9229cd6d0 R15:
> > > 00000000c06864a2
> > > [ 38.825642] Modules linked in: xt_nat cdc_ether r8152 bridge stp
> > > llc usbhid btusb btrtl btbcm btintel bluetooth asix usbnet
> > > ecdh_generic ecc mii snd_soc_hdac_hdmi snd_soc_dmic xhci_pci xhci_hcd
> > > snd_soc_skl snd_soc_sst_ipc snd_soc_sst_dsp snd_hda_ext_core
> > > snd_intel_dspcfg snd_hda_core usbcore usb_common acpi_als kfifo_buf
> > > industrialio xt_MASQUERADE iptable_nat nf_nat xt_mark fuse
> > > ip6table_filter iwlmvm mac80211 r8169 realtek iwlwifi lzo_rle
> > > lzo_compress zram cfg80211
> > > [ 38.871839] CR2: 0000000000000030
> > > [ 38.875542] ---[ end trace 6bb39ec52e30c7cb ]---
> > > [ 38.886142] RIP: 0010:drm_dp_mst_atomic_check_bw_limit+0x11/0x102
> > > [ 38.892957] Code: 05 ff cb bf 19 48 f7 f6 c3 0f 1f 44 00 00 55 b8
> > > 0b 80 ff 0f 48 89 e5 5d c3 55 48 89 e5 41 57 41 56 41 55 41 54 4c 8d
> > > 77 30 53 <48> 8b 47 30 49 89 fd 49 89 f7 45 31 e4 48 8d 58 e8 48 8d 53
> > > 18 4c
> > > [ 38.913964] RSP: 0018:ffffc9000139f9d8 EFLAGS: 00010282
> > > [ 38.919804] RAX: 0000000000000000 RBX: ffff888272aeac88 RCX:
> > > ffff888236f529e0
> > > [ 38.927784] RDX: ffff888272aeac88 RSI: ffff888236f529e0 RDI:
> > > 0000000000000000
> > > [ 38.935765] RBP: ffffc9000139fa00 R08: 0000000000000031 R09:
> > > 000000000000000e
> > > [ 38.943733] R10: ffff888236f529e8 R11: ffff8882621f3440 R12:
> > > 0000000000000000
> > > [ 38.951712] R13: ffff888236f529d0 R14: 0000000000000030 R15:
> > > ffff888236f529e0
> > > [ 38.959692] FS: 00007cd9229ce700(0000) GS:ffff888276c80000(0000)
> > > knlGS:0000000000000000
> > > [ 38.968730] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > > [ 38.975144] CR2: 0000000000000030 CR3: 00000002618e8004 CR4:
> > > 00000000003606e0
> > > [ 38.983121] Kernel panic - not syncing: Fatal exception
> > > [ 38.988967] Kernel Offset: disabled
> > > [ 38.998280] ---[ end Kernel panic - not syncing: Fatal exception ]---
> > >
> > >
> > >
> > >
> > >
> > >
> > > > [why]
> > > > Adding PBN attribute to drm_dp_vcpi_allocation structure to
> > > > keep track of how much bandwidth each Port requires.
> > > > Adding drm_dp_mst_atomic_check_bw_limit to verify that
> > > > state's bandwidth needs doesn't exceed available bandwidth.
> > > > The funtion is called in drm_dp_mst_atomic_check after
> > > > drm_dp_mst_atomic_check_topology_state to fully verify that
> > > > the proposed topology is supported.
> > > >
> > > > v2: Fixing some typos and indentations
> > > >
> > > > Reviewed-by: Lyude Paul <lyude@redhat.com>
> > > > Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> > > > ---
> > > > drivers/gpu/drm/drm_dp_mst_topology.c | 66
> > > > ++++++++++++++++++++++++++-
> > > > include/drm/drm_dp_mst_helper.h | 1 +
> > > > 2 files changed, 65 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> > > > b/drivers/gpu/drm/drm_dp_mst_topology.c
> > > > index 7cd505e771ff..f8b72ac79c66 100644
> > > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> > > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> > > > @@ -4052,7 +4052,7 @@ int drm_dp_atomic_find_vcpi_slots(struct
> > > > drm_atomic_state *state,
> > > > {
> > > > struct drm_dp_mst_topology_state *topology_state;
> > > > struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
> > > > - int prev_slots, req_slots;
> > > > + int prev_slots, prev_bw, req_slots;
> > > >
> > > > topology_state = drm_atomic_get_mst_topology_state(state,
> > > > mgr);
> > > > if (IS_ERR(topology_state))
> > > > @@ -4063,6 +4063,7 @@ int drm_dp_atomic_find_vcpi_slots(struct
> > > > drm_atomic_state *state,
> > > > if (pos->port == port) {
> > > > vcpi = pos;
> > > > prev_slots = vcpi->vcpi;
> > > > + prev_bw = vcpi->pbn;
> > > >
> > > > /*
> > > > * This should never happen, unless the
> > > > driver tries
> > > > @@ -4078,8 +4079,10 @@ int drm_dp_atomic_find_vcpi_slots(struct
> > > > drm_atomic_state *state,
> > > > break;
> > > > }
> > > > }
> > > > - if (!vcpi)
> > > > + if (!vcpi) {
> > > > prev_slots = 0;
> > > > + prev_bw = 0;
> > > > + }
> > > >
> > > > if (pbn_div <= 0)
> > > > pbn_div = mgr->pbn_div;
> > > > @@ -4089,6 +4092,9 @@ int drm_dp_atomic_find_vcpi_slots(struct
> > > > drm_atomic_state *state,
> > > > DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d ->
> > > > %d\n",
> > > > port->connector->base.id, port->connector-
> > > > >name,
> > > > port, prev_slots, req_slots);
> > > > + DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] PBN %d ->
> > > > %d\n",
> > > > + port->connector->base.id, port->connector-
> > > > >name,
> > > > + port, prev_bw, pbn);
> > > >
> > > > /* Add the new allocation to the state */
> > > > if (!vcpi) {
> > > > @@ -4101,6 +4107,7 @@ int drm_dp_atomic_find_vcpi_slots(struct
> > > > drm_atomic_state *state,
> > > > list_add(&vcpi->next, &topology_state->vcpis);
> > > > }
> > > > vcpi->vcpi = req_slots;
> > > > + vcpi->pbn = pbn;
> > > >
> > > > return req_slots;
> > > > }
> > > > @@ -4677,6 +4684,58 @@ static void drm_dp_mst_destroy_state(struct
> > > > drm_private_obj *obj,
> > > > kfree(mst_state);
> > > > }
> > > >
> > > > +static bool drm_dp_mst_port_downstream_of_branch(struct
> > > > drm_dp_mst_port *port,
> > > > + struct
> > > > drm_dp_mst_branch *branch)
> > > > +{
> > > > + while (port->parent) {
> > > > + if (port->parent == branch)
> > > > + return true;
> > > > +
> > > > + if (port->parent->port_parent)
> > > > + port = port->parent->port_parent;
> > > > + else
> > > > + break;
> > > > + }
> > > > + return false;
> > > > +}
> > > > +
> > > > +static inline
> > > > +int drm_dp_mst_atomic_check_bw_limit(struct drm_dp_mst_branch
> > > > *branch,
> > > > + struct drm_dp_mst_topology_state
> > > > *mst_state)
> > > > +{
> > > > + struct drm_dp_mst_port *port;
> > > > + struct drm_dp_vcpi_allocation *vcpi;
> > > > + int pbn_limit = 0, pbn_used = 0;
> > > > +
> > > > + list_for_each_entry(port, &branch->ports, next) {
> > > > + if (port->mstb)
> > > > + if (drm_dp_mst_atomic_check_bw_limit(port-
> > > > >mstb, mst_state))
> > > > + return -EINVAL;
> > > > +
> > > > + if (port->available_pbn > 0)
> > > > + pbn_limit = port->available_pbn;
> > > > + }
> > > > + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch has %d PBN
> > > > available\n",
> > > > + branch, pbn_limit);
> > > > +
> > > > + list_for_each_entry(vcpi, &mst_state->vcpis, next) {
> > > > + if (!vcpi->pbn)
> > > > + continue;
> > > > +
> > > > + if (drm_dp_mst_port_downstream_of_branch(vcpi->port,
> > > > branch))
> > > > + pbn_used += vcpi->pbn;
> > > > + }
> > > > + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch used %d PBN\n",
> > > > + branch, pbn_used);
> > > > +
> > > > + if (pbn_used > pbn_limit) {
> > > > + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] No available
> > > > bandwidth\n",
> > > > + branch);
> > > > + return -EINVAL;
> > > > + }
> > > > + return 0;
> > > > +}
> > > > +
> > > > static inline int
> > > > drm_dp_mst_atomic_check_topology_state(struct
> > > > drm_dp_mst_topology_mgr *mgr,
> > > > struct
> > > > drm_dp_mst_topology_state *mst_state)
> > > > @@ -4808,6 +4867,9 @@ int drm_dp_mst_atomic_check(struct
> > > > drm_atomic_state *state)
> > > > ret = drm_dp_mst_atomic_check_topology_state(mgr,
> > > > mst_state);
> > > > if (ret)
> > > > break;
> > > > + ret = drm_dp_mst_atomic_check_bw_limit(mgr-
> > > > >mst_primary, mst_state);
> > > > + if (ret)
> > > > + break;
> > > > }
> > > >
> > > > return ret;
> > > > diff --git a/include/drm/drm_dp_mst_helper.h
> > > > b/include/drm/drm_dp_mst_helper.h
> > > > index 830c94b7f45d..2919d9776af3 100644
> > > > --- a/include/drm/drm_dp_mst_helper.h
> > > > +++ b/include/drm/drm_dp_mst_helper.h
> > > > @@ -502,6 +502,7 @@ struct drm_dp_payload {
> > > > struct drm_dp_vcpi_allocation {
> > > > struct drm_dp_mst_port *port;
> > > > int vcpi;
> > > > + int pbn;
> > > > bool dsc_enabled;
> > > > struct list_head next;
> > > > };
> > > > --
> > > > 2.17.1
> > > >
> > > > _______________________________________________
> > > > dri-devel mailing list
> > > > dri-devel@lists.freedesktop.org
> > > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=02%7C01%7Cmikita.lipski%40amd.com%7C2b736cb4c0f1456691ec08d79b5f4c69%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637148705931074877&sdata=s4q0ni0H%2FiPgonlMMK9Od7UK5M%2FC%2F0rsQEGsr1FP0XU%3D&reserved=0
> >
> > --
> > Thanks,
> > Mikita Lipski
> > Software Engineer 2, AMD
> > mikita.lipski@amd.com
--
Cheers,
Lyude Paul
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v9 13/18] drm/dp_mst: Rename drm_dp_mst_atomic_check_topology_state
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (11 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 12/18] drm/dp_mst: Add branch bandwidth validation to MST atomic check mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 14/18] drm/amd/display: Add PBN per slot calculation for DSC mikita.lipski
` (4 subsequent siblings)
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Mikita Lipski, dri-devel
From: Mikita Lipski <mikita.lipski@amd.com>
[why]
drm_dp_mst_atomic_check_topology_state() should be renamed
to reflect more specific type of check. Since it is verifying
payload allocation limit it should be renamed into
drm_dp_mst_atomic_check_vcpi_alloc_limit()
Cc: Lyude Paul <lyude@redhat.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index f8b72ac79c66..ce21662f6144 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4737,8 +4737,8 @@ int drm_dp_mst_atomic_check_bw_limit(struct drm_dp_mst_branch *branch,
}
static inline int
-drm_dp_mst_atomic_check_topology_state(struct drm_dp_mst_topology_mgr *mgr,
- struct drm_dp_mst_topology_state *mst_state)
+drm_dp_mst_atomic_check_vcpi_alloc_limit(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state)
{
struct drm_dp_vcpi_allocation *vcpi;
int avail_slots = 63, payload_count = 0;
@@ -4864,7 +4864,7 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
int i, ret = 0;
for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
- ret = drm_dp_mst_atomic_check_topology_state(mgr, mst_state);
+ ret = drm_dp_mst_atomic_check_vcpi_alloc_limit(mgr, mst_state);
if (ret)
break;
ret = drm_dp_mst_atomic_check_bw_limit(mgr->mst_primary, mst_state);
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 14/18] drm/amd/display: Add PBN per slot calculation for DSC
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (12 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 13/18] drm/dp_mst: Rename drm_dp_mst_atomic_check_topology_state mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-20 21:44 ` Lyude Paul
2019-12-20 22:50 ` Leo
2019-12-13 20:08 ` [PATCH v9 15/18] drm/amd/display: MST DSC compute fair share mikita.lipski
` (3 subsequent siblings)
17 siblings, 2 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Mikita Lipski, Harry Wentland, dri-devel
From: Mikita Lipski <mikita.lipski@amd.com>
[why]
Need to calculate VCPI slots differently for DSC
to take in account current link rate, link count
and FEC.
[how]
Add helper to get pbn_div from dc_link
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Lyude Paul <lyude@redhat.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ++++++++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 7557edee7db0..c376c8ccd391 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -491,3 +491,11 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
aconnector->connector_id);
}
+int dm_mst_get_pbn_divider(struct dc_link *link)
+{
+ if (!link)
+ return 0;
+
+ return dc_link_bandwidth_kbps(link,
+ dc_link_get_link_cap(link)) / (8 * 1000 * 54);
+}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 2da851b40042..a553ea046185 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -29,6 +29,8 @@
struct amdgpu_display_manager;
struct amdgpu_dm_connector;
+int dm_mst_get_pbn_divider(struct dc_link *link);
+
void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
struct amdgpu_dm_connector *aconnector);
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v9 14/18] drm/amd/display: Add PBN per slot calculation for DSC
2019-12-13 20:08 ` [PATCH v9 14/18] drm/amd/display: Add PBN per slot calculation for DSC mikita.lipski
@ 2019-12-20 21:44 ` Lyude Paul
2019-12-20 22:50 ` Leo
1 sibling, 0 replies; 30+ messages in thread
From: Lyude Paul @ 2019-12-20 21:44 UTC (permalink / raw)
To: mikita.lipski, amd-gfx; +Cc: Harry Wentland, dri-devel
Acked-by: Lyude Paul <lyude@redhat.com>
On Fri, 2019-12-13 at 15:08 -0500, mikita.lipski@amd.com wrote:
> From: Mikita Lipski <mikita.lipski@amd.com>
>
> [why]
> Need to calculate VCPI slots differently for DSC
> to take in account current link rate, link count
> and FEC.
> [how]
> Add helper to get pbn_div from dc_link
>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ++++++++
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 2 ++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 7557edee7db0..c376c8ccd391 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -491,3 +491,11 @@ void amdgpu_dm_initialize_dp_connector(struct
> amdgpu_display_manager *dm,
> aconnector->connector_id);
> }
>
> +int dm_mst_get_pbn_divider(struct dc_link *link)
> +{
> + if (!link)
> + return 0;
> +
> + return dc_link_bandwidth_kbps(link,
> + dc_link_get_link_cap(link)) / (8 * 1000 * 54);
> +}
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> index 2da851b40042..a553ea046185 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> @@ -29,6 +29,8 @@
> struct amdgpu_display_manager;
> struct amdgpu_dm_connector;
>
> +int dm_mst_get_pbn_divider(struct dc_link *link);
> +
> void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
> struct amdgpu_dm_connector
> *aconnector);
>
--
Cheers,
Lyude Paul
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v9 14/18] drm/amd/display: Add PBN per slot calculation for DSC
2019-12-13 20:08 ` [PATCH v9 14/18] drm/amd/display: Add PBN per slot calculation for DSC mikita.lipski
2019-12-20 21:44 ` Lyude Paul
@ 2019-12-20 22:50 ` Leo
1 sibling, 0 replies; 30+ messages in thread
From: Leo @ 2019-12-20 22:50 UTC (permalink / raw)
To: mikita.lipski, amd-gfx; +Cc: dri-devel
On 2019-12-13 3:08 p.m., mikita.lipski@amd.com wrote:
> From: Mikita Lipski <mikita.lipski@amd.com>
>
> [why]
> Need to calculate VCPI slots differently for DSC
> to take in account current link rate, link count
> and FEC.
> [how]
> Add helper to get pbn_div from dc_link
>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ++++++++
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 2 ++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 7557edee7db0..c376c8ccd391 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -491,3 +491,11 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
> aconnector->connector_id);
> }
>
> +int dm_mst_get_pbn_divider(struct dc_link *link)
> +{
> + if (!link)
> + return 0;
> +
> + return dc_link_bandwidth_kbps(link,
> + dc_link_get_link_cap(link)) / (8 * 1000 * 54);
Had to take a look at the DP spec to understand this conversion here, section 2.6.4.1.
LGTM,
Reviewed-by: Leo Li <sunpeng.li@amd.com>
> +}
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> index 2da851b40042..a553ea046185 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> @@ -29,6 +29,8 @@
> struct amdgpu_display_manager;
> struct amdgpu_dm_connector;
>
> +int dm_mst_get_pbn_divider(struct dc_link *link);
> +
> void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
> struct amdgpu_dm_connector *aconnector);
>
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v9 15/18] drm/amd/display: MST DSC compute fair share
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (13 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 14/18] drm/amd/display: Add PBN per slot calculation for DSC mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-20 21:44 ` Lyude Paul
2019-12-13 20:08 ` [PATCH v9 16/18] drm/amd/display: Recalculate VCPI slots for new DSC connectors mikita.lipski
` (2 subsequent siblings)
17 siblings, 1 reply; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Manasi Navare, David Francis, Mikita Lipski, dri-devel
From: David Francis <David.Francis@amd.com>
If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network
Implement an algorithm to determine the correct DSC config
for each stream
The algorithm:
This
[ ] ( )
represents the range of bandwidths possible for a given stream.
The [] area represents the range of DSC configs, and the ()
represents no DSC. The bandwidth used increases from left to right.
First, try disabling DSC on all streams
[ ] (|)
[ ] (|)
Check this against the bandwidth limits of the link and each branch
(including each endpoint). If it passes, the job is done
Second, try maximum DSC compression on all streams
that support DSC
[| ] ( )
[| ] ( )
If this does not pass, then enabling this combination of streams
is impossible
Otherwise, divide the remaining bandwidth evenly amongst the streams
[ | ] ( )
[ | ] ( )
If one or more of the streams reach minimum compression, evenly
divide the reamining bandwidth amongst the remaining streams
[ |] ( )
[ |] ( )
[ | ] ( )
[ | ] ( )
If all streams can reach minimum compression, disable compression
greedily
[ |] ( )
[ |] ( )
[ ] (|)
Perform this algorithm on each full update, on each MST link
with at least one DSC stream on it
After the configs are computed, call
dcn20_add_dsc_to_stream_resource on each stream with DSC enabled.
It is only after all streams are created that we can know which
of them will need DSC.
Do all of this at the end of amdgpu atomic check. If it fails,
fail check; This combination of timings cannot be supported.
v2: Use drm_dp_mst_atomic_check to validate bw for certain dsc
configurations
v3: Use dc_dsc_policy structure to get min and max bpp rate
for DSC configuration
Cc: Lyude Paul <lyude@redhat.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 364 ++++++++++++++++++
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 +
5 files changed, 376 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 753a79734817..93a230d956ee 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8095,6 +8095,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
+ goto fail;
+
if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
ret = -EINVAL;
goto fail;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index c376c8ccd391..6d13d1c33530 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -40,6 +40,10 @@
#if defined(CONFIG_DEBUG_FS)
#include "amdgpu_dm_debugfs.h"
#endif
+
+
+#include "dc/dcn20/dcn20_resource.h"
+
/* #define TRACE_DPCD */
#ifdef TRACE_DPCD
@@ -499,3 +503,363 @@ int dm_mst_get_pbn_divider(struct dc_link *link)
return dc_link_bandwidth_kbps(link,
dc_link_get_link_cap(link)) / (8 * 1000 * 54);
}
+
+struct dsc_mst_fairness_params {
+ struct dc_crtc_timing *timing;
+ struct dc_sink *sink;
+ struct dc_dsc_bw_range bw_range;
+ bool compression_possible;
+ struct drm_dp_mst_port *port;
+};
+
+struct dsc_mst_fairness_vars {
+ int pbn;
+ bool dsc_enabled;
+ int bpp_x16;
+};
+
+static int kbps_to_peak_pbn(int kbps)
+{
+ u64 peak_kbps = kbps;
+
+ peak_kbps *= 1006;
+ peak_kbps /= 1000;
+ return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
+}
+
+static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
+ struct dsc_mst_fairness_vars *vars,
+ int count)
+{
+ int i;
+
+ for (i = 0; i < count; i++) {
+ memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
+ if (vars[i].dsc_enabled && dc_dsc_compute_config(
+ params[i].sink->ctx->dc->res_pool->dscs[0],
+ ¶ms[i].sink->sink_dsc_caps.dsc_dec_caps,
+ params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
+ 0,
+ params[i].timing,
+ ¶ms[i].timing->dsc_cfg)) {
+ params[i].timing->flags.DSC = 1;
+ params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
+ } else {
+ params[i].timing->flags.DSC = 0;
+ }
+ }
+}
+
+static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
+{
+ struct dc_dsc_config dsc_config;
+ u64 kbps;
+
+ kbps = (u64)pbn * 994 * 8 * 54 / 64;
+ dc_dsc_compute_config(
+ param.sink->ctx->dc->res_pool->dscs[0],
+ ¶m.sink->sink_dsc_caps.dsc_dec_caps,
+ param.sink->ctx->dc->debug.dsc_min_slice_height_override,
+ (int) kbps, param.timing, &dsc_config);
+
+ return dsc_config.bits_per_pixel;
+}
+
+static void increase_dsc_bpp(struct drm_atomic_state *state,
+ struct dc_link *dc_link,
+ struct dsc_mst_fairness_params *params,
+ struct dsc_mst_fairness_vars *vars,
+ int count)
+{
+ int i;
+ bool bpp_increased[MAX_PIPES];
+ int initial_slack[MAX_PIPES];
+ int min_initial_slack;
+ int next_index;
+ int remaining_to_increase = 0;
+ int pbn_per_timeslot;
+ int link_timeslots_used;
+ int fair_pbn_alloc;
+
+ for (i = 0; i < count; i++) {
+ if (vars[i].dsc_enabled) {
+ initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
+ bpp_increased[i] = false;
+ remaining_to_increase += 1;
+ } else {
+ initial_slack[i] = 0;
+ bpp_increased[i] = true;
+ }
+ }
+
+ pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
+ dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
+
+ while (remaining_to_increase) {
+ next_index = -1;
+ min_initial_slack = -1;
+ for (i = 0; i < count; i++) {
+ if (!bpp_increased[i]) {
+ if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
+ min_initial_slack = initial_slack[i];
+ next_index = i;
+ }
+ }
+ }
+
+ if (next_index == -1)
+ break;
+
+ link_timeslots_used = 0;
+
+ for (i = 0; i < count; i++)
+ link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
+
+ fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
+
+ if (initial_slack[next_index] > fair_pbn_alloc) {
+ vars[next_index].pbn += fair_pbn_alloc;
+ drm_dp_atomic_find_vcpi_slots(state,
+ params[next_index].port->mgr,
+ params[next_index].port,
+ vars[next_index].pbn,
+ dm_mst_get_pbn_divider(dc_link));
+ if (!drm_dp_mst_atomic_check(state)) {
+ vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
+ } else {
+ vars[next_index].pbn -= fair_pbn_alloc;
+ drm_dp_atomic_find_vcpi_slots(state,
+ params[next_index].port->mgr,
+ params[next_index].port,
+ vars[next_index].pbn,
+ dm_mst_get_pbn_divider(dc_link));
+ }
+ } else {
+ vars[next_index].pbn += initial_slack[next_index];
+ drm_dp_atomic_find_vcpi_slots(state,
+ params[next_index].port->mgr,
+ params[next_index].port,
+ vars[next_index].pbn,
+ dm_mst_get_pbn_divider(dc_link));
+ if (!drm_dp_mst_atomic_check(state)) {
+ vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
+ } else {
+ vars[next_index].pbn -= initial_slack[next_index];
+ drm_dp_atomic_find_vcpi_slots(state,
+ params[next_index].port->mgr,
+ params[next_index].port,
+ vars[next_index].pbn,
+ dm_mst_get_pbn_divider(dc_link));
+ }
+ }
+
+ bpp_increased[next_index] = true;
+ remaining_to_increase--;
+ }
+}
+
+static void try_disable_dsc(struct drm_atomic_state *state,
+ struct dc_link *dc_link,
+ struct dsc_mst_fairness_params *params,
+ struct dsc_mst_fairness_vars *vars,
+ int count)
+{
+ int i;
+ bool tried[MAX_PIPES];
+ int kbps_increase[MAX_PIPES];
+ int max_kbps_increase;
+ int next_index;
+ int remaining_to_try = 0;
+
+ for (i = 0; i < count; i++) {
+ if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
+ kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
+ tried[i] = false;
+ remaining_to_try += 1;
+ } else {
+ kbps_increase[i] = 0;
+ tried[i] = true;
+ }
+ }
+
+ while (remaining_to_try) {
+ next_index = -1;
+ max_kbps_increase = -1;
+ for (i = 0; i < count; i++) {
+ if (!tried[i]) {
+ if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
+ max_kbps_increase = kbps_increase[i];
+ next_index = i;
+ }
+ }
+ }
+
+ if (next_index == -1)
+ break;
+
+ vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
+ drm_dp_atomic_find_vcpi_slots(state,
+ params[next_index].port->mgr,
+ params[next_index].port,
+ vars[next_index].pbn,
+ 0);
+
+ if (!drm_dp_mst_atomic_check(state)) {
+ vars[next_index].dsc_enabled = false;
+ vars[next_index].bpp_x16 = 0;
+ } else {
+ vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
+ drm_dp_atomic_find_vcpi_slots(state,
+ params[next_index].port->mgr,
+ params[next_index].port,
+ vars[next_index].pbn,
+ dm_mst_get_pbn_divider(dc_link));
+ }
+
+ tried[next_index] = true;
+ remaining_to_try--;
+ }
+}
+
+static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
+ struct dc_state *dc_state,
+ struct dc_link *dc_link)
+{
+ int i;
+ struct dc_stream_state *stream;
+ struct dsc_mst_fairness_params params[MAX_PIPES];
+ struct dsc_mst_fairness_vars vars[MAX_PIPES];
+ struct amdgpu_dm_connector *aconnector;
+ int count = 0;
+
+ memset(params, 0, sizeof(params));
+
+ /* Set up params */
+ for (i = 0; i < dc_state->stream_count; i++) {
+ struct dc_dsc_policy dsc_policy = {0};
+
+ stream = dc_state->streams[i];
+
+ if (stream->link != dc_link)
+ continue;
+
+ stream->timing.flags.DSC = 0;
+
+ params[count].timing = &stream->timing;
+ params[count].sink = stream->sink;
+ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+ params[count].port = aconnector->port;
+ params[count].compression_possible = stream->sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported;
+ dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
+ if (!dc_dsc_compute_bandwidth_range(
+ stream->sink->ctx->dc->res_pool->dscs[0],
+ stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
+ dsc_policy.min_target_bpp,
+ dsc_policy.max_target_bpp,
+ &stream->sink->sink_dsc_caps.dsc_dec_caps,
+ &stream->timing, ¶ms[count].bw_range))
+ params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
+
+ count++;
+ }
+ /* Try no compression */
+ for (i = 0; i < count; i++) {
+ vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
+ vars[i].dsc_enabled = false;
+ vars[i].bpp_x16 = 0;
+ drm_dp_atomic_find_vcpi_slots(state,
+ params[i].port->mgr,
+ params[i].port,
+ vars[i].pbn,
+ 0);
+ }
+ if (!drm_dp_mst_atomic_check(state)) {
+ set_dsc_configs_from_fairness_vars(params, vars, count);
+ return true;
+ }
+
+ /* Try max compression */
+ for (i = 0; i < count; i++) {
+ if (params[i].compression_possible) {
+ vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
+ vars[i].dsc_enabled = true;
+ vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
+ drm_dp_atomic_find_vcpi_slots(state,
+ params[i].port->mgr,
+ params[i].port,
+ vars[i].pbn,
+ dm_mst_get_pbn_divider(dc_link));
+ } else {
+ vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
+ vars[i].dsc_enabled = false;
+ vars[i].bpp_x16 = 0;
+ drm_dp_atomic_find_vcpi_slots(state,
+ params[i].port->mgr,
+ params[i].port,
+ vars[i].pbn,
+ 0);
+ }
+ }
+ if (drm_dp_mst_atomic_check(state))
+ return false;
+
+ /* Optimize degree of compression */
+ increase_dsc_bpp(state, dc_link, params, vars, count);
+
+ try_disable_dsc(state, dc_link, params, vars, count);
+
+ set_dsc_configs_from_fairness_vars(params, vars, count);
+
+ return true;
+}
+
+bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
+ struct dc_state *dc_state)
+{
+ int i, j;
+ struct dc_stream_state *stream;
+ bool computed_streams[MAX_PIPES];
+ struct amdgpu_dm_connector *aconnector;
+
+ for (i = 0; i < dc_state->stream_count; i++)
+ computed_streams[i] = false;
+
+ for (i = 0; i < dc_state->stream_count; i++) {
+ stream = dc_state->streams[i];
+
+ if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
+ continue;
+
+ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+
+ if (!aconnector || !aconnector->dc_sink)
+ continue;
+
+ if (!aconnector->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
+ continue;
+
+ if (computed_streams[i])
+ continue;
+
+ mutex_lock(&aconnector->mst_mgr.lock);
+ if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
+ mutex_unlock(&aconnector->mst_mgr.lock);
+ return false;
+ }
+ mutex_unlock(&aconnector->mst_mgr.lock);
+
+ for (j = 0; j < dc_state->stream_count; j++) {
+ if (dc_state->streams[j]->link == stream->link)
+ computed_streams[j] = true;
+ }
+ }
+
+ for (i = 0; i < dc_state->stream_count; i++) {
+ stream = dc_state->streams[i];
+
+ if (stream->timing.flags.DSC == 1)
+ dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);
+ }
+
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index a553ea046185..d451ce9cecc0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -34,4 +34,7 @@ int dm_mst_get_pbn_divider(struct dc_link *link);
void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
struct amdgpu_dm_connector *aconnector);
+
+bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
+ struct dc_state *dc_state);
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 47adcd4555ec..b1935f5d9cb8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1564,7 +1564,7 @@ static void release_dsc(struct resource_context *res_ctx,
-static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
struct dc_state *dc_ctx,
struct dc_stream_state *dc_stream)
{
@@ -1579,6 +1579,9 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
if (pipe_ctx->stream != dc_stream)
continue;
+ if (pipe_ctx->stream_res.dsc)
+ continue;
+
acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
/* The number of DSCs can be less than the number of pipes */
@@ -1627,7 +1630,7 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx,
/* Get a DSC if required and available */
if (result == DC_OK && dc_stream->timing.flags.DSC)
- result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
+ result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
if (result == DC_OK)
result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index 840ca66c34e1..f5893840b79b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -157,6 +157,7 @@ void dcn20_calculate_dlg_params(
enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);
enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state);
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v9 15/18] drm/amd/display: MST DSC compute fair share
2019-12-13 20:08 ` [PATCH v9 15/18] drm/amd/display: MST DSC compute fair share mikita.lipski
@ 2019-12-20 21:44 ` Lyude Paul
0 siblings, 0 replies; 30+ messages in thread
From: Lyude Paul @ 2019-12-20 21:44 UTC (permalink / raw)
To: mikita.lipski, amd-gfx; +Cc: Manasi Navare, David Francis, dri-devel
Acked-by: Lyude Paul <lyude@redhat.com>
On Fri, 2019-12-13 at 15:08 -0500, mikita.lipski@amd.com wrote:
> From: David Francis <David.Francis@amd.com>
>
> If there is limited link bandwidth on a MST network,
> it must be divided fairly between the streams on that network
>
> Implement an algorithm to determine the correct DSC config
> for each stream
>
> The algorithm:
> This
> [ ] ( )
> represents the range of bandwidths possible for a given stream.
> The [] area represents the range of DSC configs, and the ()
> represents no DSC. The bandwidth used increases from left to right.
>
> First, try disabling DSC on all streams
> [ ] (|)
> [ ] (|)
> Check this against the bandwidth limits of the link and each branch
> (including each endpoint). If it passes, the job is done
>
> Second, try maximum DSC compression on all streams
> that support DSC
> [| ] ( )
> [| ] ( )
> If this does not pass, then enabling this combination of streams
> is impossible
>
> Otherwise, divide the remaining bandwidth evenly amongst the streams
> [ | ] ( )
> [ | ] ( )
>
> If one or more of the streams reach minimum compression, evenly
> divide the reamining bandwidth amongst the remaining streams
> [ |] ( )
> [ |] ( )
> [ | ] ( )
> [ | ] ( )
>
> If all streams can reach minimum compression, disable compression
> greedily
> [ |] ( )
> [ |] ( )
> [ ] (|)
>
> Perform this algorithm on each full update, on each MST link
> with at least one DSC stream on it
>
> After the configs are computed, call
> dcn20_add_dsc_to_stream_resource on each stream with DSC enabled.
> It is only after all streams are created that we can know which
> of them will need DSC.
>
> Do all of this at the end of amdgpu atomic check. If it fails,
> fail check; This combination of timings cannot be supported.
>
> v2: Use drm_dp_mst_atomic_check to validate bw for certain dsc
> configurations
>
> v3: Use dc_dsc_policy structure to get min and max bpp rate
> for DSC configuration
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +
> .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 364 ++++++++++++++++++
> .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 +
> .../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +-
> .../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 +
> 5 files changed, 376 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 753a79734817..93a230d956ee 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -8095,6 +8095,9 @@ static int amdgpu_dm_atomic_check(struct drm_device
> *dev,
> if (ret)
> goto fail;
>
> + if (!compute_mst_dsc_configs_for_state(state, dm_state-
> >context))
> + goto fail;
> +
> if (dc_validate_global_state(dc, dm_state->context, false) !=
> DC_OK) {
> ret = -EINVAL;
> goto fail;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index c376c8ccd391..6d13d1c33530 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -40,6 +40,10 @@
> #if defined(CONFIG_DEBUG_FS)
> #include "amdgpu_dm_debugfs.h"
> #endif
> +
> +
> +#include "dc/dcn20/dcn20_resource.h"
> +
> /* #define TRACE_DPCD */
>
> #ifdef TRACE_DPCD
> @@ -499,3 +503,363 @@ int dm_mst_get_pbn_divider(struct dc_link *link)
> return dc_link_bandwidth_kbps(link,
> dc_link_get_link_cap(link)) / (8 * 1000 * 54);
> }
> +
> +struct dsc_mst_fairness_params {
> + struct dc_crtc_timing *timing;
> + struct dc_sink *sink;
> + struct dc_dsc_bw_range bw_range;
> + bool compression_possible;
> + struct drm_dp_mst_port *port;
> +};
> +
> +struct dsc_mst_fairness_vars {
> + int pbn;
> + bool dsc_enabled;
> + int bpp_x16;
> +};
> +
> +static int kbps_to_peak_pbn(int kbps)
> +{
> + u64 peak_kbps = kbps;
> +
> + peak_kbps *= 1006;
> + peak_kbps /= 1000;
> + return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
> +}
> +
> +static void set_dsc_configs_from_fairness_vars(struct
> dsc_mst_fairness_params *params,
> + struct dsc_mst_fairness_vars *vars,
> + int count)
> +{
> + int i;
> +
> + for (i = 0; i < count; i++) {
> + memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing-
> >dsc_cfg));
> + if (vars[i].dsc_enabled && dc_dsc_compute_config(
> + params[i].sink->ctx->dc->res_pool-
> >dscs[0],
> + ¶ms[i].sink-
> >sink_dsc_caps.dsc_dec_caps,
> + params[i].sink->ctx->dc-
> >debug.dsc_min_slice_height_override,
> + 0,
> + params[i].timing,
> + ¶ms[i].timing->dsc_cfg)) {
> + params[i].timing->flags.DSC = 1;
> + params[i].timing->dsc_cfg.bits_per_pixel =
> vars[i].bpp_x16;
> + } else {
> + params[i].timing->flags.DSC = 0;
> + }
> + }
> +}
> +
> +static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
> +{
> + struct dc_dsc_config dsc_config;
> + u64 kbps;
> +
> + kbps = (u64)pbn * 994 * 8 * 54 / 64;
> + dc_dsc_compute_config(
> + param.sink->ctx->dc->res_pool->dscs[0],
> + ¶m.sink->sink_dsc_caps.dsc_dec_caps,
> + param.sink->ctx->dc-
> >debug.dsc_min_slice_height_override,
> + (int) kbps, param.timing, &dsc_config);
> +
> + return dsc_config.bits_per_pixel;
> +}
> +
> +static void increase_dsc_bpp(struct drm_atomic_state *state,
> + struct dc_link *dc_link,
> + struct dsc_mst_fairness_params *params,
> + struct dsc_mst_fairness_vars *vars,
> + int count)
> +{
> + int i;
> + bool bpp_increased[MAX_PIPES];
> + int initial_slack[MAX_PIPES];
> + int min_initial_slack;
> + int next_index;
> + int remaining_to_increase = 0;
> + int pbn_per_timeslot;
> + int link_timeslots_used;
> + int fair_pbn_alloc;
> +
> + for (i = 0; i < count; i++) {
> + if (vars[i].dsc_enabled) {
> + initial_slack[i] =
> kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
> + bpp_increased[i] = false;
> + remaining_to_increase += 1;
> + } else {
> + initial_slack[i] = 0;
> + bpp_increased[i] = true;
> + }
> + }
> +
> + pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
> + dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
> +
> + while (remaining_to_increase) {
> + next_index = -1;
> + min_initial_slack = -1;
> + for (i = 0; i < count; i++) {
> + if (!bpp_increased[i]) {
> + if (min_initial_slack == -1 ||
> min_initial_slack > initial_slack[i]) {
> + min_initial_slack = initial_slack[i];
> + next_index = i;
> + }
> + }
> + }
> +
> + if (next_index == -1)
> + break;
> +
> + link_timeslots_used = 0;
> +
> + for (i = 0; i < count; i++)
> + link_timeslots_used += DIV_ROUND_UP(vars[i].pbn,
> pbn_per_timeslot);
> +
> + fair_pbn_alloc = (63 - link_timeslots_used) /
> remaining_to_increase * pbn_per_timeslot;
> +
> + if (initial_slack[next_index] > fair_pbn_alloc) {
> + vars[next_index].pbn += fair_pbn_alloc;
> + drm_dp_atomic_find_vcpi_slots(state,
> + params[next_index].port-
> >mgr,
> + params[next_index].port,
> + vars[next_index].pbn,
> + dm_mst_get_pbn_divider(d
> c_link));
> + if (!drm_dp_mst_atomic_check(state)) {
> + vars[next_index].bpp_x16 =
> bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
> + } else {
> + vars[next_index].pbn -= fair_pbn_alloc;
> + drm_dp_atomic_find_vcpi_slots(state,
> + params[next_index].port-
> >mgr,
> + params[next_index].port,
> + vars[next_index].pbn,
> + dm_mst_get_pbn_divider(d
> c_link));
> + }
> + } else {
> + vars[next_index].pbn += initial_slack[next_index];
> + drm_dp_atomic_find_vcpi_slots(state,
> + params[next_index].port-
> >mgr,
> + params[next_index].port,
> + vars[next_index].pbn,
> + dm_mst_get_pbn_divider(d
> c_link));
> + if (!drm_dp_mst_atomic_check(state)) {
> + vars[next_index].bpp_x16 =
> params[next_index].bw_range.max_target_bpp_x16;
> + } else {
> + vars[next_index].pbn -=
> initial_slack[next_index];
> + drm_dp_atomic_find_vcpi_slots(state,
> + params[next_index].port-
> >mgr,
> + params[next_index].port,
> + vars[next_index].pbn,
> + dm_mst_get_pbn_divider(d
> c_link));
> + }
> + }
> +
> + bpp_increased[next_index] = true;
> + remaining_to_increase--;
> + }
> +}
> +
> +static void try_disable_dsc(struct drm_atomic_state *state,
> + struct dc_link *dc_link,
> + struct dsc_mst_fairness_params *params,
> + struct dsc_mst_fairness_vars *vars,
> + int count)
> +{
> + int i;
> + bool tried[MAX_PIPES];
> + int kbps_increase[MAX_PIPES];
> + int max_kbps_increase;
> + int next_index;
> + int remaining_to_try = 0;
> +
> + for (i = 0; i < count; i++) {
> + if (vars[i].dsc_enabled && vars[i].bpp_x16 ==
> params[i].bw_range.max_target_bpp_x16) {
> + kbps_increase[i] = params[i].bw_range.stream_kbps -
> params[i].bw_range.max_kbps;
> + tried[i] = false;
> + remaining_to_try += 1;
> + } else {
> + kbps_increase[i] = 0;
> + tried[i] = true;
> + }
> + }
> +
> + while (remaining_to_try) {
> + next_index = -1;
> + max_kbps_increase = -1;
> + for (i = 0; i < count; i++) {
> + if (!tried[i]) {
> + if (max_kbps_increase == -1 ||
> max_kbps_increase < kbps_increase[i]) {
> + max_kbps_increase = kbps_increase[i];
> + next_index = i;
> + }
> + }
> + }
> +
> + if (next_index == -1)
> + break;
> +
> + vars[next_index].pbn =
> kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
> + drm_dp_atomic_find_vcpi_slots(state,
> + params[next_index].port->mgr,
> + params[next_index].port,
> + vars[next_index].pbn,
> + 0);
> +
> + if (!drm_dp_mst_atomic_check(state)) {
> + vars[next_index].dsc_enabled = false;
> + vars[next_index].bpp_x16 = 0;
> + } else {
> + vars[next_index].pbn =
> kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
> + drm_dp_atomic_find_vcpi_slots(state,
> + params[next_index].port->mgr,
> + params[next_index].port,
> + vars[next_index].pbn,
> + dm_mst_get_pbn_divider(dc_link))
> ;
> + }
> +
> + tried[next_index] = true;
> + remaining_to_try--;
> + }
> +}
> +
> +static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state
> *state,
> + struct dc_state *dc_state,
> + struct dc_link *dc_link)
> +{
> + int i;
> + struct dc_stream_state *stream;
> + struct dsc_mst_fairness_params params[MAX_PIPES];
> + struct dsc_mst_fairness_vars vars[MAX_PIPES];
> + struct amdgpu_dm_connector *aconnector;
> + int count = 0;
> +
> + memset(params, 0, sizeof(params));
> +
> + /* Set up params */
> + for (i = 0; i < dc_state->stream_count; i++) {
> + struct dc_dsc_policy dsc_policy = {0};
> +
> + stream = dc_state->streams[i];
> +
> + if (stream->link != dc_link)
> + continue;
> +
> + stream->timing.flags.DSC = 0;
> +
> + params[count].timing = &stream->timing;
> + params[count].sink = stream->sink;
> + aconnector = (struct amdgpu_dm_connector *)stream-
> >dm_stream_context;
> + params[count].port = aconnector->port;
> + params[count].compression_possible = stream->sink-
> >sink_dsc_caps.dsc_dec_caps.is_dsc_supported;
> + dc_dsc_get_policy_for_timing(params[count].timing,
> &dsc_policy);
> + if (!dc_dsc_compute_bandwidth_range(
> + stream->sink->ctx->dc->res_pool->dscs[0],
> + stream->sink->ctx->dc-
> >debug.dsc_min_slice_height_override,
> + dsc_policy.min_target_bpp,
> + dsc_policy.max_target_bpp,
> + &stream->sink->sink_dsc_caps.dsc_dec_caps,
> + &stream->timing, ¶ms[count].bw_range))
> + params[count].bw_range.stream_kbps =
> dc_bandwidth_in_kbps_from_timing(&stream->timing);
> +
> + count++;
> + }
> + /* Try no compression */
> + for (i = 0; i < count; i++) {
> + vars[i].pbn =
> kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
> + vars[i].dsc_enabled = false;
> + vars[i].bpp_x16 = 0;
> + drm_dp_atomic_find_vcpi_slots(state,
> + params[i].port->mgr,
> + params[i].port,
> + vars[i].pbn,
> + 0);
> + }
> + if (!drm_dp_mst_atomic_check(state)) {
> + set_dsc_configs_from_fairness_vars(params, vars, count);
> + return true;
> + }
> +
> + /* Try max compression */
> + for (i = 0; i < count; i++) {
> + if (params[i].compression_possible) {
> + vars[i].pbn =
> kbps_to_peak_pbn(params[i].bw_range.min_kbps);
> + vars[i].dsc_enabled = true;
> + vars[i].bpp_x16 =
> params[i].bw_range.min_target_bpp_x16;
> + drm_dp_atomic_find_vcpi_slots(state,
> + params[i].port->mgr,
> + params[i].port,
> + vars[i].pbn,
> + dm_mst_get_pbn_divider(dc_link))
> ;
> + } else {
> + vars[i].pbn =
> kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
> + vars[i].dsc_enabled = false;
> + vars[i].bpp_x16 = 0;
> + drm_dp_atomic_find_vcpi_slots(state,
> + params[i].port->mgr,
> + params[i].port,
> + vars[i].pbn,
> + 0);
> + }
> + }
> + if (drm_dp_mst_atomic_check(state))
> + return false;
> +
> + /* Optimize degree of compression */
> + increase_dsc_bpp(state, dc_link, params, vars, count);
> +
> + try_disable_dsc(state, dc_link, params, vars, count);
> +
> + set_dsc_configs_from_fairness_vars(params, vars, count);
> +
> + return true;
> +}
> +
> +bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
> + struct dc_state *dc_state)
> +{
> + int i, j;
> + struct dc_stream_state *stream;
> + bool computed_streams[MAX_PIPES];
> + struct amdgpu_dm_connector *aconnector;
> +
> + for (i = 0; i < dc_state->stream_count; i++)
> + computed_streams[i] = false;
> +
> + for (i = 0; i < dc_state->stream_count; i++) {
> + stream = dc_state->streams[i];
> +
> + if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
> + continue;
> +
> + aconnector = (struct amdgpu_dm_connector *)stream-
> >dm_stream_context;
> +
> + if (!aconnector || !aconnector->dc_sink)
> + continue;
> +
> + if (!aconnector->dc_sink-
> >sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
> + continue;
> +
> + if (computed_streams[i])
> + continue;
> +
> + mutex_lock(&aconnector->mst_mgr.lock);
> + if (!compute_mst_dsc_configs_for_link(state, dc_state, stream-
> >link)) {
> + mutex_unlock(&aconnector->mst_mgr.lock);
> + return false;
> + }
> + mutex_unlock(&aconnector->mst_mgr.lock);
> +
> + for (j = 0; j < dc_state->stream_count; j++) {
> + if (dc_state->streams[j]->link == stream->link)
> + computed_streams[j] = true;
> + }
> + }
> +
> + for (i = 0; i < dc_state->stream_count; i++) {
> + stream = dc_state->streams[i];
> +
> + if (stream->timing.flags.DSC == 1)
> + dcn20_add_dsc_to_stream_resource(stream->ctx->dc,
> dc_state, stream);
> + }
> +
> + return true;
> +}
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> index a553ea046185..d451ce9cecc0 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> @@ -34,4 +34,7 @@ int dm_mst_get_pbn_divider(struct dc_link *link);
> void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
> struct amdgpu_dm_connector
> *aconnector);
>
> +
> +bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
> + struct dc_state *dc_state);
> #endif
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index 47adcd4555ec..b1935f5d9cb8 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -1564,7 +1564,7 @@ static void release_dsc(struct resource_context
> *res_ctx,
>
>
>
> -static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
> +enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
> struct dc_state *dc_ctx,
> struct dc_stream_state *dc_stream)
> {
> @@ -1579,6 +1579,9 @@ static enum dc_status
> add_dsc_to_stream_resource(struct dc *dc,
> if (pipe_ctx->stream != dc_stream)
> continue;
>
> + if (pipe_ctx->stream_res.dsc)
> + continue;
> +
> acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc,
> i);
>
> /* The number of DSCs can be less than the number of pipes */
> @@ -1627,7 +1630,7 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc,
> struct dc_state *new_ctx,
>
> /* Get a DSC if required and available */
> if (result == DC_OK && dc_stream->timing.flags.DSC)
> - result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
> + result = dcn20_add_dsc_to_stream_resource(dc, new_ctx,
> dc_stream);
>
> if (result == DC_OK)
> result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> index 840ca66c34e1..f5893840b79b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> @@ -157,6 +157,7 @@ void dcn20_calculate_dlg_params(
>
> enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct
> dc_state *context, struct dc_stream_state *stream);
> enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state
> *new_ctx, struct dc_stream_state *dc_stream);
> +enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct
> dc_state *dc_ctx, struct dc_stream_state *dc_stream);
> enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state
> *new_ctx, struct dc_stream_state *dc_stream);
> enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state
> *plane_state);
>
--
Cheers,
Lyude Paul
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v9 16/18] drm/amd/display: Recalculate VCPI slots for new DSC connectors
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (14 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 15/18] drm/amd/display: MST DSC compute fair share mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-20 21:41 ` Lyude Paul
2019-12-13 20:08 ` [PATCH v9 17/18] drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs mikita.lipski
2019-12-13 20:08 ` [PATCH v9 18/18] drm/amd/display: Trigger modesets on MST DSC connectors mikita.lipski
17 siblings, 1 reply; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Mikita Lipski, dri-devel
From: Mikita Lipski <mikita.lipski@amd.com>
[why]
Since for DSC MST connector's PBN is claculated differently
due to compression, we have to recalculate both PBN and
VCPI slots for that connector.
[how]
The function iterates through all the active streams to
find, which have DSC enabled, then recalculates PBN for
it and calls drm_dp_helper_update_vcpi_slots_for_dsc to
update connector's VCPI slots.
v2: - use drm_dp_mst_atomic_enable_dsc per port to
enable/disable DSC
v3: - Iterate through connector states from the state passed
- On each connector state get stream from dc_state,
instead CRTC state
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 76 +++++++++++++++++--
1 file changed, 71 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 93a230d956ee..2ac3a2f0b452 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4986,6 +4986,69 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
.atomic_check = dm_encoder_helper_atomic_check
};
+static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
+ struct dc_state *dc_state)
+{
+ struct dc_stream_state *stream = NULL;
+ struct drm_connector *connector;
+ struct drm_connector_state *new_con_state, *old_con_state;
+ struct amdgpu_dm_connector *aconnector;
+ struct dm_connector_state *dm_conn_state;
+ int i, j, clock, bpp;
+ int vcpi, pbn_div, pbn = 0;
+
+ for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
+
+ aconnector = to_amdgpu_dm_connector(connector);
+
+ if (!aconnector->port)
+ continue;
+
+ if (!new_con_state || !new_con_state->crtc)
+ continue;
+
+ dm_conn_state = to_dm_connector_state(new_con_state);
+
+ for (j = 0; j < dc_state->stream_count; j++) {
+ stream = dc_state->streams[j];
+ if (!stream)
+ continue;
+
+ if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector)
+ break;
+
+ stream = NULL;
+ }
+
+ if (!stream)
+ continue;
+
+ if (stream->timing.flags.DSC != 1) {
+ drm_dp_mst_atomic_enable_dsc(state,
+ aconnector->port,
+ dm_conn_state->pbn,
+ 0,
+ false);
+ continue;
+ }
+
+ pbn_div = dm_mst_get_pbn_divider(stream->link);
+ bpp = stream->timing.dsc_cfg.bits_per_pixel;
+ clock = stream->timing.pix_clk_100hz / 10;
+ pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
+ vcpi = drm_dp_mst_atomic_enable_dsc(state,
+ aconnector->port,
+ pbn, pbn_div,
+ true);
+ if (vcpi < 0)
+ return vcpi;
+
+ dm_conn_state->pbn = pbn;
+ dm_conn_state->vcpi_slots = vcpi;
+ }
+ return 0;
+}
+
static void dm_drm_plane_reset(struct drm_plane *plane)
{
struct dm_plane_state *amdgpu_state = NULL;
@@ -8022,11 +8085,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
- /* Perform validation of MST topology in the state*/
- ret = drm_dp_mst_atomic_check(state);
- if (ret)
- goto fail;
-
if (state->legacy_cursor_update) {
/*
* This is a fast cursor update coming from the plane update
@@ -8098,6 +8156,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
goto fail;
+ ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
+ if (ret)
+ goto fail;
+
if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
ret = -EINVAL;
goto fail;
@@ -8126,6 +8188,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
dc_retain_state(old_dm_state->context);
}
}
+ /* Perform validation of MST topology in the state*/
+ ret = drm_dp_mst_atomic_check(state);
+ if (ret)
+ goto fail;
/* Store the overall update type for use later in atomic check. */
for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v9 16/18] drm/amd/display: Recalculate VCPI slots for new DSC connectors
2019-12-13 20:08 ` [PATCH v9 16/18] drm/amd/display: Recalculate VCPI slots for new DSC connectors mikita.lipski
@ 2019-12-20 21:41 ` Lyude Paul
2019-12-23 19:05 ` Mikita Lipski
0 siblings, 1 reply; 30+ messages in thread
From: Lyude Paul @ 2019-12-20 21:41 UTC (permalink / raw)
To: mikita.lipski, amd-gfx; +Cc: dri-devel
So I reviewed this already but realized I made a very silly mistake, comments
down below:
On Fri, 2019-12-13 at 15:08 -0500, mikita.lipski@amd.com wrote:
> From: Mikita Lipski <mikita.lipski@amd.com>
>
> [why]
> Since for DSC MST connector's PBN is claculated differently
> due to compression, we have to recalculate both PBN and
> VCPI slots for that connector.
>
> [how]
> The function iterates through all the active streams to
> find, which have DSC enabled, then recalculates PBN for
> it and calls drm_dp_helper_update_vcpi_slots_for_dsc to
> update connector's VCPI slots.
>
> v2: - use drm_dp_mst_atomic_enable_dsc per port to
> enable/disable DSC
>
> v3: - Iterate through connector states from the state passed
> - On each connector state get stream from dc_state,
> instead CRTC state
>
> Reviewed-by: Lyude Paul <lyude@redhat.com>
> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 76 +++++++++++++++++--
> 1 file changed, 71 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 93a230d956ee..2ac3a2f0b452 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4986,6 +4986,69 @@ const struct drm_encoder_helper_funcs
> amdgpu_dm_encoder_helper_funcs = {
> .atomic_check = dm_encoder_helper_atomic_check
> };
>
> +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> + struct dc_state *dc_state)
> +{
> + struct dc_stream_state *stream = NULL;
> + struct drm_connector *connector;
> + struct drm_connector_state *new_con_state, *old_con_state;
> + struct amdgpu_dm_connector *aconnector;
> + struct dm_connector_state *dm_conn_state;
> + int i, j, clock, bpp;
> + int vcpi, pbn_div, pbn = 0;
> +
> + for_each_oldnew_connector_in_state(state, connector, old_con_state,
> new_con_state, i) {
> +
> + aconnector = to_amdgpu_dm_connector(connector);
> +
> + if (!aconnector->port)
> + continue;
> +
> + if (!new_con_state || !new_con_state->crtc)
> + continue;
> +
> + dm_conn_state = to_dm_connector_state(new_con_state);
> +
> + for (j = 0; j < dc_state->stream_count; j++) {
> + stream = dc_state->streams[j];
> + if (!stream)
> + continue;
> +
> + if ((struct amdgpu_dm_connector*)stream-
> >dm_stream_context == aconnector)
> + break;
> +
> + stream = NULL;
> + }
> +
> + if (!stream)
> + continue;
> +
> + if (stream->timing.flags.DSC != 1) {
> + drm_dp_mst_atomic_enable_dsc(state,
> + aconnector->port,
> + dm_conn_state->pbn,
> + 0,
> + false);
> + continue;
> + }
> +
> + pbn_div = dm_mst_get_pbn_divider(stream->link);
> + bpp = stream->timing.dsc_cfg.bits_per_pixel;
> + clock = stream->timing.pix_clk_100hz / 10;
> + pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
> + vcpi = drm_dp_mst_atomic_enable_dsc(state,
> + aconnector->port,
> + pbn, pbn_div,
> + true);
> + if (vcpi < 0)
> + return vcpi;
> +
> + dm_conn_state->pbn = pbn;
> + dm_conn_state->vcpi_slots = vcpi;
> + }
> + return 0;
> +}
> +
> static void dm_drm_plane_reset(struct drm_plane *plane)
> {
> struct dm_plane_state *amdgpu_state = NULL;
> @@ -8022,11 +8085,6 @@ static int amdgpu_dm_atomic_check(struct drm_device
> *dev,
> if (ret)
> goto fail;
>
> - /* Perform validation of MST topology in the state*/
> - ret = drm_dp_mst_atomic_check(state);
> - if (ret)
> - goto fail;
> -
> if (state->legacy_cursor_update) {
> /*
> * This is a fast cursor update coming from the plane update
> @@ -8098,6 +8156,10 @@ static int amdgpu_dm_atomic_check(struct drm_device
> *dev,
> if (!compute_mst_dsc_configs_for_state(state, dm_state-
> >context))
> goto fail;
>
> + ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state-
> >context);
> + if (ret)
> + goto fail;
> +
> if (dc_validate_global_state(dc, dm_state->context, false) !=
> DC_OK) {
> ret = -EINVAL;
> goto fail;
> @@ -8126,6 +8188,10 @@ static int amdgpu_dm_atomic_check(struct drm_device
> *dev,
> dc_retain_state(old_dm_state->context);
> }
> }
> + /* Perform validation of MST topology in the state*/
> + ret = drm_dp_mst_atomic_check(state);
> + if (ret)
> + goto fail;
I realized that we actually should make it so that we actually expose a
version of drm_dp_mst_atomic_check() which allows you to manually specify a
drm_dp_mst_topology_state, because otherwise we're checking the bandwidth caps
of _ALL_ enabled topologies which could cause us to fail just because another
topology's new state doesn't meet the bandwidth requirements yet because we
haven't readjusted it for the fair share compute algorithm.
Also, I think we should probably differentiate in the atomic check functions
between failing an atomic check for a topology state because it doesn't meet
the bandwidth requirements we set, vs. a topology state failing atomic check
for other reasons (temporary deadlock, too many payloads, etc.). So basically-
we should return -ENOSPC when we fail because of a bandwidth (including VCPI
slot allocation) issue.
>
> /* Store the overall update type for use later in atomic check. */
> for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
--
Cheers,
Lyude Paul
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v9 16/18] drm/amd/display: Recalculate VCPI slots for new DSC connectors
2019-12-20 21:41 ` Lyude Paul
@ 2019-12-23 19:05 ` Mikita Lipski
0 siblings, 0 replies; 30+ messages in thread
From: Mikita Lipski @ 2019-12-23 19:05 UTC (permalink / raw)
To: Lyude Paul, mikita.lipski, amd-gfx; +Cc: dri-devel
On 12/20/19 4:41 PM, Lyude Paul wrote:
> So I reviewed this already but realized I made a very silly mistake, comments
> down below:
>
> On Fri, 2019-12-13 at 15:08 -0500, mikita.lipski@amd.com wrote:
>> From: Mikita Lipski <mikita.lipski@amd.com>
>>
>> [why]
>> Since for DSC MST connector's PBN is claculated differently
>> due to compression, we have to recalculate both PBN and
>> VCPI slots for that connector.
>>
>> [how]
>> The function iterates through all the active streams to
>> find, which have DSC enabled, then recalculates PBN for
>> it and calls drm_dp_helper_update_vcpi_slots_for_dsc to
>> update connector's VCPI slots.
>>
>> v2: - use drm_dp_mst_atomic_enable_dsc per port to
>> enable/disable DSC
>>
>> v3: - Iterate through connector states from the state passed
>> - On each connector state get stream from dc_state,
>> instead CRTC state
>>
>> Reviewed-by: Lyude Paul <lyude@redhat.com>
>> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
>> ---
>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 76 +++++++++++++++++--
>> 1 file changed, 71 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 93a230d956ee..2ac3a2f0b452 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -4986,6 +4986,69 @@ const struct drm_encoder_helper_funcs
>> amdgpu_dm_encoder_helper_funcs = {
>> .atomic_check = dm_encoder_helper_atomic_check
>> };
>>
>> +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
>> + struct dc_state *dc_state)
>> +{
>> + struct dc_stream_state *stream = NULL;
>> + struct drm_connector *connector;
>> + struct drm_connector_state *new_con_state, *old_con_state;
>> + struct amdgpu_dm_connector *aconnector;
>> + struct dm_connector_state *dm_conn_state;
>> + int i, j, clock, bpp;
>> + int vcpi, pbn_div, pbn = 0;
>> +
>> + for_each_oldnew_connector_in_state(state, connector, old_con_state,
>> new_con_state, i) {
>> +
>> + aconnector = to_amdgpu_dm_connector(connector);
>> +
>> + if (!aconnector->port)
>> + continue;
>> +
>> + if (!new_con_state || !new_con_state->crtc)
>> + continue;
>> +
>> + dm_conn_state = to_dm_connector_state(new_con_state);
>> +
>> + for (j = 0; j < dc_state->stream_count; j++) {
>> + stream = dc_state->streams[j];
>> + if (!stream)
>> + continue;
>> +
>> + if ((struct amdgpu_dm_connector*)stream-
>>> dm_stream_context == aconnector)
>> + break;
>> +
>> + stream = NULL;
>> + }
>> +
>> + if (!stream)
>> + continue;
>> +
>> + if (stream->timing.flags.DSC != 1) {
>> + drm_dp_mst_atomic_enable_dsc(state,
>> + aconnector->port,
>> + dm_conn_state->pbn,
>> + 0,
>> + false);
>> + continue;
>> + }
>> +
>> + pbn_div = dm_mst_get_pbn_divider(stream->link);
>> + bpp = stream->timing.dsc_cfg.bits_per_pixel;
>> + clock = stream->timing.pix_clk_100hz / 10;
>> + pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
>> + vcpi = drm_dp_mst_atomic_enable_dsc(state,
>> + aconnector->port,
>> + pbn, pbn_div,
>> + true);
>> + if (vcpi < 0)
>> + return vcpi;
>> +
>> + dm_conn_state->pbn = pbn;
>> + dm_conn_state->vcpi_slots = vcpi;
>> + }
>> + return 0;
>> +}
>> +
>> static void dm_drm_plane_reset(struct drm_plane *plane)
>> {
>> struct dm_plane_state *amdgpu_state = NULL;
>> @@ -8022,11 +8085,6 @@ static int amdgpu_dm_atomic_check(struct drm_device
>> *dev,
>> if (ret)
>> goto fail;
>>
>> - /* Perform validation of MST topology in the state*/
>> - ret = drm_dp_mst_atomic_check(state);
>> - if (ret)
>> - goto fail;
>> -
>> if (state->legacy_cursor_update) {
>> /*
>> * This is a fast cursor update coming from the plane update
>> @@ -8098,6 +8156,10 @@ static int amdgpu_dm_atomic_check(struct drm_device
>> *dev,
>> if (!compute_mst_dsc_configs_for_state(state, dm_state-
>>> context))
>> goto fail;
>>
>> + ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state-
>>> context);
>> + if (ret)
>> + goto fail;
>> +
>> if (dc_validate_global_state(dc, dm_state->context, false) !=
>> DC_OK) {
>> ret = -EINVAL;
>> goto fail;
>> @@ -8126,6 +8188,10 @@ static int amdgpu_dm_atomic_check(struct drm_device
>> *dev,
>> dc_retain_state(old_dm_state->context);
>> }
>> }
>> + /* Perform validation of MST topology in the state*/
>> + ret = drm_dp_mst_atomic_check(state);
>> + if (ret)
>> + goto fail;
>
> I realized that we actually should make it so that we actually expose a
> version of drm_dp_mst_atomic_check() which allows you to manually specify a
> drm_dp_mst_topology_state, because otherwise we're checking the bandwidth caps
> of _ALL_ enabled topologies which could cause us to fail just because another
> topology's new state doesn't meet the bandwidth requirements yet because we
> haven't readjusted it for the fair share compute algorithm.
>
But wouldn't we want to fail the whole atomic check even if one of the
topology states fails?
We call compute_mst_dsc_configs_for_state() function before
drm_dp_mst_atomic_check(), and during it driver will attmpt different
compression configurations untill drm_dp_mst_atomic_check() passes
because we call drm_dp_mst_atomic_check() inside
compute_mst_dsc_configs_for_state() every time configuration is readjusted.
> Also, I think we should probably differentiate in the atomic check functions
> between failing an atomic check for a topology state because it doesn't meet
> the bandwidth requirements we set, vs. a topology state failing atomic check
> for other reasons (temporary deadlock, too many payloads, etc.). So basically-
> we should return -ENOSPC when we fail because of a bandwidth (including VCPI
> slot allocation) issue.
>
Thanks, I will update drm_dp_mst_atomic_check_bw_limit() to return
appropriate error values on bw failure.
>>
>> /* Store the overall update type for use later in atomic check. */
>> for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
--
Thanks,
Mikita Lipski
Software Engineer, AMD
mikita.lipski@amd.com
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v9 17/18] drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (15 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 16/18] drm/amd/display: Recalculate VCPI slots for new DSC connectors mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
2019-12-13 20:08 ` [PATCH v9 18/18] drm/amd/display: Trigger modesets on MST DSC connectors mikita.lipski
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Mikita Lipski, dri-devel
From: Mikita Lipski <mikita.lipski@amd.com>
[why]
Whenever a connector on an MST network is changed or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not change timing.
[how]
Adding helper to trigger modesets on MST DSC connectors
by setting mode_changed flag on CRTCs in the same topology
as affected connector
v2: use drm_dp_mst_dsc_aux_for_port function to verify
if the port is DSC capable
v3: - added _must_check attribute
- removed topology manager check
- fix typos and indentations
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 61 +++++++++++++++++++++++++++
include/drm/drm_dp_mst_helper.h | 3 ++
2 files changed, 64 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index ce21662f6144..ec90323949fc 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4775,6 +4775,67 @@ drm_dp_mst_atomic_check_vcpi_alloc_limit(struct drm_dp_mst_topology_mgr *mgr,
return 0;
}
+/**
+ * drm_dp_mst_add_affected_dsc_crtcs
+ * @state: Pointer to the new struct drm_dp_mst_topology_state
+ * @port: Port pointer of connector with new state
+ *
+ * Whenever there is a change in mst topology
+ * DSC configuration would have to be recalculated
+ * therefore we need to trigger modeset on all affected
+ * CRTCs in that topology
+ *
+ * See also:
+ * drm_dp_mst_atomic_enable_dsc()
+ */
+int drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state, struct drm_dp_mst_topology_mgr *mgr)
+{
+ struct drm_dp_mst_topology_state *mst_state;
+ struct drm_dp_vcpi_allocation *pos;
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *crtc_state;
+
+ mst_state = drm_atomic_get_mst_topology_state(state, mgr);
+
+ if (IS_ERR(mst_state))
+ return -EINVAL;
+
+ list_for_each_entry(pos, &mst_state->vcpis, next) {
+
+ connector = pos->port->connector;
+
+ if (!connector)
+ return -EINVAL;
+
+ conn_state = drm_atomic_get_connector_state(state, connector);
+
+ if (IS_ERR(conn_state))
+ return PTR_ERR(conn_state);
+
+ crtc = conn_state->crtc;
+
+ if (WARN_ON(!crtc))
+ return -EINVAL;
+
+ if (!drm_dp_mst_dsc_aux_for_port(pos->port))
+ continue;
+
+ crtc_state = drm_atomic_get_crtc_state(mst_state->base.state, crtc);
+
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ DRM_DEBUG_ATOMIC("[MST MGR:%p] Setting mode_changed flag on CRTC %p\n",
+ mgr, crtc);
+
+ crtc_state->mode_changed = true;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_mst_add_affected_dsc_crtcs);
+
/**
* drm_dp_mst_atomic_enable_dsc - Set DSC Enable Flag to On/Off
* @state: Pointer to the new drm_atomic_state
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 2919d9776af3..942575de86a0 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -780,6 +780,9 @@ int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
int pbn, int pbn_div,
bool enable);
int __must_check
+drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr);
+int __must_check
drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port);
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH v9 18/18] drm/amd/display: Trigger modesets on MST DSC connectors
2019-12-13 20:08 [PATCH v9 00/18] DSC MST support for DRM and AMDGPU mikita.lipski
` (16 preceding siblings ...)
2019-12-13 20:08 ` [PATCH v9 17/18] drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs mikita.lipski
@ 2019-12-13 20:08 ` mikita.lipski
17 siblings, 0 replies; 30+ messages in thread
From: mikita.lipski @ 2019-12-13 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: David Francis, Mikita Lipski, dri-devel
From: Mikita Lipski <mikita.lipski@amd.com>
Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not change timing.
Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
for each crtc that shares a MST topology with that stream and
supports DSC, add that crtc (and all affected connectors and
planes) to the atomic state and set mode_changed on its state
v2: Do this check only on Navi and before adding connectors
and planes on modesetting crtcs
v3: Call the drm_dp_mst_add_affected_dsc_crtcs() to update
all affected CRTCs
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2ac3a2f0b452..909665427110 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7930,6 +7930,29 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
return ret;
}
+static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
+{
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state;
+ struct amdgpu_dm_connector *aconnector = NULL;
+ int i;
+ for_each_new_connector_in_state(state, connector, conn_state, i) {
+ if (conn_state->crtc != crtc)
+ continue;
+
+ aconnector = to_amdgpu_dm_connector(connector);
+ if (!aconnector->port)
+ aconnector = NULL;
+ else
+ break;
+ }
+
+ if (!aconnector)
+ return 0;
+
+ return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_mgr);
+}
+
/**
* amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
* @dev: The DRM device
@@ -7982,6 +8005,16 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ if (adev->asic_type >= CHIP_NAVI10) {
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
+ ret = add_affected_mst_dsc_crtcs(state, crtc);
+ if (ret)
+ goto fail;
+ }
+ }
+ }
+
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
!new_crtc_state->color_mgmt_changed &&
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread