* [PATCH 2/3] drm/amdgpu/atomfirmware: update to latest integratedinfotable
2020-06-25 22:04 [PATCH 1/3] drm/amdgpu/atomfirmware: fix vram_info fetching for renoir Alex Deucher
@ 2020-06-25 22:04 ` Alex Deucher
2020-06-25 22:04 ` [PATCH 3/3] drm/amdgpu/atomfirmware: update vram info handling for renoir Alex Deucher
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2020-06-25 22:04 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Used for renoir.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/include/atomfirmware.h | 78 ++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index b852248b2da8..c2544c81dfb2 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1116,6 +1116,35 @@ struct atom_14nm_combphy_tmds_vs_set
uint8_t margin_deemph_lane0__deemph_sel_val;
};
+struct atom_DCN_dpphy_dvihdmi_tuningset
+{
+ uint32_t max_symclk_in10khz;
+ uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
+ uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
+ uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
+ uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
+ uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
+ uint8_t reserved1;
+ uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
+ uint8_t reserved2;
+};
+
+struct atom_DCN_dpphy_dp_setting{
+ uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
+ uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
+ uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
+ uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
+ uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
+};
+
+struct atom_DCN_dpphy_dp_tuningset{
+ uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
+ uint8_t version;
+ uint16_t table_size; // size of atom_14nm_dpphy_dp_setting
+ uint16_t reserved;
+ struct atom_DCN_dpphy_dp_setting dptunings[10];
+};
+
struct atom_i2c_reg_info {
uint8_t ucI2cRegIndex;
uint8_t ucI2cRegVal;
@@ -1178,6 +1207,55 @@ struct atom_integrated_system_info_v1_11
uint32_t reserved[66];
};
+struct atom_integrated_system_info_v1_12
+{
+ struct atom_common_table_header table_header;
+ uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
+ uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
+ uint32_t system_config;
+ uint32_t cpucapinfo;
+ uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
+ uint16_t gpuclk_ss_type;
+ uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
+ uint16_t lvds_ss_rate_10hz;
+ uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
+ uint16_t hdmi_ss_rate_10hz;
+ uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
+ uint16_t dvi_ss_rate_10hz;
+ uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
+ uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
+ uint16_t backlight_pwm_hz; // pwm frequency in hz
+ uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
+ uint8_t umachannelnumber; // number of memory channels
+ uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //
+ uint8_t pwr_on_de_to_vary_bl;
+ uint8_t pwr_down_vary_bloff_to_de;
+ uint8_t pwr_down_de_to_digoff;
+ uint8_t pwr_off_delay;
+ uint8_t pwr_on_vary_bl_to_blon;
+ uint8_t pwr_down_bloff_to_vary_bloff;
+ uint8_t min_allowed_bl_level;
+ uint8_t htc_hyst_limit;
+ uint8_t htc_tmp_limit;
+ uint8_t reserved1;
+ uint8_t reserved2;
+ struct atom_external_display_connection_info extdispconninfo;
+ struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset;
+ struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset;
+ struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset;
+ struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set
+ struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set
+ struct atom_camera_data camera_info;
+ struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
+ struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
+ struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
+ struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
+ struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set
+ struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set
+ struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
+ struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
+ uint32_t reserved[63];
+};
// system_config
enum atom_system_vbiosmisc_def{
--
2.25.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] drm/amdgpu/atomfirmware: update vram info handling for renoir
2020-06-25 22:04 [PATCH 1/3] drm/amdgpu/atomfirmware: fix vram_info fetching for renoir Alex Deucher
2020-06-25 22:04 ` [PATCH 2/3] drm/amdgpu/atomfirmware: update to latest integratedinfotable Alex Deucher
@ 2020-06-25 22:04 ` Alex Deucher
2020-07-01 5:33 ` [PATCH 1/3] drm/amdgpu/atomfirmware: fix vram_info fetching " Alex Deucher
2020-07-01 10:03 ` Quan, Evan
3 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2020-06-25 22:04 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Add support for integrated_system_info table v12. Use the actual
v12 structure.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 4b8aad1c0b51..1279053324f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -111,6 +111,7 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
union igp_info {
struct atom_integrated_system_info_v1_11 v11;
+ struct atom_integrated_system_info_v1_12 v12;
};
union umc_info {
@@ -206,7 +207,6 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
(mode_info->atom_context->bios + data_offset);
switch (crev) {
case 11:
- case 12:
mem_channel_number = igp_info->v11.umachannelnumber;
/* channel width is 64 */
if (vram_width)
@@ -215,6 +215,15 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
if (vram_type)
*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
break;
+ case 12:
+ mem_channel_number = igp_info->v12.umachannelnumber;
+ /* channel width is 64 */
+ if (vram_width)
+ *vram_width = mem_channel_number * 64;
+ mem_type = igp_info->v12.memorytype;
+ if (vram_type)
+ *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+ break;
default:
return -EINVAL;
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 1/3] drm/amdgpu/atomfirmware: fix vram_info fetching for renoir
2020-06-25 22:04 [PATCH 1/3] drm/amdgpu/atomfirmware: fix vram_info fetching for renoir Alex Deucher
2020-06-25 22:04 ` [PATCH 2/3] drm/amdgpu/atomfirmware: update to latest integratedinfotable Alex Deucher
2020-06-25 22:04 ` [PATCH 3/3] drm/amdgpu/atomfirmware: update vram info handling for renoir Alex Deucher
@ 2020-07-01 5:33 ` Alex Deucher
2020-07-01 10:03 ` Quan, Evan
3 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2020-07-01 5:33 UTC (permalink / raw)
To: amd-gfx list; +Cc: Alex Deucher
Ping on this series?
On Thu, Jun 25, 2020 at 6:05 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> Renoir uses integrated_system_info table v12. The table
> has the same layout as v11 with respect to this data. Just
> reuse the existing code for v12 for stable.
>
> Fixes incorrectly reported vram info in the driver output.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> index e249b22fef54..4b8aad1c0b51 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> @@ -206,6 +206,7 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
> (mode_info->atom_context->bios + data_offset);
> switch (crev) {
> case 11:
> + case 12:
> mem_channel_number = igp_info->v11.umachannelnumber;
> /* channel width is 64 */
> if (vram_width)
> --
> 2.25.4
>
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^ permalink raw reply [flat|nested] 5+ messages in thread* RE: [PATCH 1/3] drm/amdgpu/atomfirmware: fix vram_info fetching for renoir
2020-06-25 22:04 [PATCH 1/3] drm/amdgpu/atomfirmware: fix vram_info fetching for renoir Alex Deucher
` (2 preceding siblings ...)
2020-07-01 5:33 ` [PATCH 1/3] drm/amdgpu/atomfirmware: fix vram_info fetching " Alex Deucher
@ 2020-07-01 10:03 ` Quan, Evan
3 siblings, 0 replies; 5+ messages in thread
From: Quan, Evan @ 2020-07-01 10:03 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Deucher, Alexander
[AMD Official Use Only - Internal Distribution Only]
Series is acked-by: Evan Quan <evan.quan@amd.com>
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Friday, June 26, 2020 6:05 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: [PATCH 1/3] drm/amdgpu/atomfirmware: fix vram_info fetching for renoir
Renoir uses integrated_system_info table v12. The table has the same layout as v11 with respect to this data. Just reuse the existing code for v12 for stable.
Fixes incorrectly reported vram info in the driver output.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index e249b22fef54..4b8aad1c0b51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -206,6 +206,7 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
(mode_info->atom_context->bios + data_offset);
switch (crev) {
case 11:
+case 12:
mem_channel_number = igp_info->v11.umachannelnumber;
/* channel width is 64 */
if (vram_width)
--
2.25.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread