* [PATCH 1/5] drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2)
@ 2020-10-14 7:18 Evan Quan
2020-10-14 7:18 ` [PATCH 2/5] drm/amdgpu: add interface for setting ASPM Evan Quan
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Evan Quan @ 2020-10-14 7:18 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
For entering UMD stable Pstate, the operations to enter rlc_safe
mode, disable mgcg_perfmon and disable PCIE aspm are needed. And
the opposite operations should be performed on UMD stable Pstate
exiting.
V2: take those ASICs(CI/SI/VI) which may not support this into
consideration
Change-Id: Iff4aa465fd16f55a4f4de8ee0503997b204f8f9d
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ece1b41a31f9..f8f3e375c93e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -623,6 +623,8 @@ struct amdgpu_asic_funcs {
bool (*supports_baco)(struct amdgpu_device *adev);
/* pre asic_init quirks */
void (*pre_asic_init)(struct amdgpu_device *adev);
+ /* enter/exit umd stable pstate */
+ int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
};
/*
@@ -1168,6 +1170,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
+#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
+ ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f78749bc8760..92869eb297d8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1415,6 +1415,7 @@ static int smu_enable_umd_pstate(void *handle,
AMD_CG_STATE_UNGATE);
smu_gfx_ulv_control(smu, false);
smu_deep_sleep_control(smu, false);
+ amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
@@ -1422,6 +1423,7 @@ static int smu_enable_umd_pstate(void *handle,
if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
*level = smu_dpm_ctx->saved_dpm_level;
smu_dpm_ctx->enable_umd_pstate = false;
+ amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
smu_deep_sleep_control(smu, true);
smu_gfx_ulv_control(smu, true);
amdgpu_device_ip_set_clockgating_state(smu->adev,
--
2.28.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/5] drm/amdgpu: add interface for setting ASPM
2020-10-14 7:18 [PATCH 1/5] drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2) Evan Quan
@ 2020-10-14 7:18 ` Evan Quan
2020-10-14 7:18 ` [PATCH 3/5] drm/amdgpu: add interface for setting MGCG perfmon Evan Quan
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Evan Quan @ 2020-10-14 7:18 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
Support NAVI10 ASPM setting.
Change-Id: I0c9410951e23b1d4a30bf8e373431dcb16a4573b
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 39 ++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index 483834a62436..e62cc0e1a5ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -87,6 +87,8 @@ struct amdgpu_nbio_funcs {
void (*query_ras_error_count)(struct amdgpu_device *adev,
void *ras_error_status);
int (*ras_late_init)(struct amdgpu_device *adev);
+ void (*enable_aspm)(struct amdgpu_device *adev,
+ bool enable);
};
struct amdgpu_nbio {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..e0048806afaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -28,10 +28,12 @@
#include "nbio/nbio_2_3_offset.h"
#include "nbio/nbio_2_3_sh_mask.h"
#include <uapi/linux/kfd_ioctl.h>
+#include <linux/pci.h>
#define smnPCIE_CONFIG_CNTL 0x11180044
#define smnCPM_CONTROL 0x11180460
#define smnPCIE_CNTL2 0x11180070
+#define smnPCIE_LC_CNTL 0x11140280
#define mmBIF_SDMA2_DOORBELL_RANGE 0x01d6
#define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX 2
@@ -312,6 +314,42 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
}
+#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1
+#define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT 0x00000009 // 1=1us, 9=1ms
+#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT 0x0000000E // 4ms
+
+static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
+
+ if (enable) {
+ /* Disable ASPM L0s/L1 first */
+ data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
+
+ data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
+
+ if (pci_is_thunderbolt_attached(adev->pdev))
+ data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+ else
+ data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+
+ data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+ } else {
+ /* Disbale ASPM L1 */
+ data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
+ /* Disable ASPM TxL0s */
+ data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
+ /* Disable ACPI L1 */
+ data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+ }
+
+ if (def != data)
+ WREG32_PCIE(smnPCIE_LC_CNTL, data);
+}
+
const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
.get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
@@ -332,4 +370,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
.ih_control = nbio_v2_3_ih_control,
.init_registers = nbio_v2_3_init_registers,
.remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
+ .enable_aspm = nbio_v2_3_enable_aspm,
};
--
2.28.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/5] drm/amdgpu: add interface for setting MGCG perfmon
2020-10-14 7:18 [PATCH 1/5] drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2) Evan Quan
2020-10-14 7:18 ` [PATCH 2/5] drm/amdgpu: add interface for setting ASPM Evan Quan
@ 2020-10-14 7:18 ` Evan Quan
2020-10-14 7:18 ` [PATCH 4/5] drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2) Evan Quan
2020-10-14 7:18 ` [PATCH 5/5] drm/amd/pm: properly setting GPO feature on UMD pstate entering/exiting Evan Quan
3 siblings, 0 replies; 6+ messages in thread
From: Evan Quan @ 2020-10-14 7:18 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
Enable Navi1X MGCG perfmon setting.
Change-Id: Ifc860a798becbe372f974f7eb537a4a57ac4943f
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 258498cbf1eb..190753930b11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -218,6 +218,7 @@ struct amdgpu_gfx_funcs {
void (*reset_ras_error_count) (struct amdgpu_device *adev);
void (*init_spm_golden)(struct amdgpu_device *adev);
void (*query_ras_error_status) (struct amdgpu_device *adev);
+ void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
};
struct sq_work {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 9d31f9339e02..df787c86b538 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4272,6 +4272,21 @@ static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
nv_grbm_select(adev, me, pipe, q, vm);
}
+static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data, def;
+
+ data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
+
+ if (enable)
+ data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
+ else
+ data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
+
+ if (data != def)
+ WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
+}
static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
@@ -4281,6 +4296,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
+ .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
};
static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
--
2.28.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/5] drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2)
2020-10-14 7:18 [PATCH 1/5] drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2) Evan Quan
2020-10-14 7:18 ` [PATCH 2/5] drm/amdgpu: add interface for setting ASPM Evan Quan
2020-10-14 7:18 ` [PATCH 3/5] drm/amdgpu: add interface for setting MGCG perfmon Evan Quan
@ 2020-10-14 7:18 ` Evan Quan
2020-10-14 7:18 ` [PATCH 5/5] drm/amd/pm: properly setting GPO feature on UMD pstate entering/exiting Evan Quan
3 siblings, 0 replies; 6+ messages in thread
From: Evan Quan @ 2020-10-14 7:18 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
Fulfill Navi gfx and pcie settings on umd pstate switching.
V2: temporarily skip the pcie ASPM setting considering the ASPM function
is not fully enabled yet
Change-Id: I8d746d4c25f890665feeffddf64164ed2b1f5ccc
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 47bd79c9e6ea..de0bf92ffa29 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -742,6 +742,29 @@ static void nv_pre_asic_init(struct amdgpu_device *adev)
{
}
+static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
+ bool enter)
+{
+ if (enter)
+ amdgpu_gfx_rlc_enter_safe_mode(adev);
+ else
+ amdgpu_gfx_rlc_exit_safe_mode(adev);
+
+ if (adev->gfx.funcs->update_perfmon_mgcg)
+ adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
+
+ /*
+ * The ASPM function is not fully enabled and verified on
+ * Navi yet. Temporarily skip this until ASPM enabled.
+ */
+#if 0
+ if (adev->nbio.funcs->enable_aspm)
+ adev->nbio.funcs->enable_aspm(adev, !enter);
+#endif
+
+ return 0;
+}
+
static const struct amdgpu_asic_funcs nv_asic_funcs =
{
.read_disabled_bios = &nv_read_disabled_bios,
@@ -762,6 +785,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
.get_pcie_replay_count = &nv_get_pcie_replay_count,
.supports_baco = &nv_asic_supports_baco,
.pre_asic_init = &nv_pre_asic_init,
+ .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
};
static int nv_common_early_init(void *handle)
--
2.28.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/5] drm/amd/pm: properly setting GPO feature on UMD pstate entering/exiting
2020-10-14 7:18 [PATCH 1/5] drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2) Evan Quan
` (2 preceding siblings ...)
2020-10-14 7:18 ` [PATCH 4/5] drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2) Evan Quan
@ 2020-10-14 7:18 ` Evan Quan
2020-10-14 19:59 ` Alex Deucher
3 siblings, 1 reply; 6+ messages in thread
From: Evan Quan @ 2020-10-14 7:18 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
Disable/enable the GPO feature on UMD pstate entering/exiting.
Change-Id: I4bd4b560b945227044df918c9066ffbbc17728ca
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 22 +++++++++++++++++++
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 +
5 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index f21d8dcac9ae..32f3738a6a6f 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -574,6 +574,7 @@ struct pptable_funcs {
int (*get_fan_parameters)(struct smu_context *smu);
int (*post_init)(struct smu_context *smu);
void (*interrupt_work)(struct smu_context *smu);
+ int (*gpo_control)(struct smu_context *smu, bool enablement);
};
typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index b1a18fbb7682..f6403881f265 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -184,6 +184,7 @@
__SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \
__SMU_DUMMY_MAP(PowerUpCvip), \
__SMU_DUMMY_MAP(PowerDownCvip), \
+ __SMU_DUMMY_MAP(SetGpoFeaturePMask), \
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 92869eb297d8..18e0db34a3ee 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1407,6 +1407,7 @@ static int smu_enable_umd_pstate(void *handle,
if (*level & profile_mode_mask) {
smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
smu_dpm_ctx->enable_umd_pstate = true;
+ smu_gpo_control(smu, false);
amdgpu_device_ip_set_powergating_state(smu->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_UNGATE);
@@ -1432,6 +1433,7 @@ static int smu_enable_umd_pstate(void *handle,
amdgpu_device_ip_set_powergating_state(smu->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_GATE);
+ smu_gpo_control(smu, true);
}
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index c27806fd07e0..71cb000306a4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -127,6 +127,7 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
+ MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
};
static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
@@ -2714,6 +2715,26 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
NULL);
}
+static int sienna_cichlid_gpo_control(struct smu_context *smu,
+ bool enablement)
+{
+ int ret = 0;
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
+ if (enablement)
+ ret = smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_SetGpoFeaturePMask,
+ GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
+ NULL);
+ else
+ ret = smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_SetGpoFeaturePMask,
+ 0,
+ NULL);
+ }
+
+ return ret;
+}
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -2795,6 +2816,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.deep_sleep_control = smu_v11_0_deep_sleep_control,
.get_fan_parameters = sienna_cichlid_get_fan_parameters,
.interrupt_work = smu_v11_0_interrupt_work,
+ .gpo_control = sienna_cichlid_gpo_control,
};
void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
index c7e1fe5f442d..f7be2d1a0ff2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
@@ -89,6 +89,7 @@
#define smu_deep_sleep_control(smu, enablement) smu_ppt_funcs(deep_sleep_control, 0, smu, enablement)
#define smu_get_fan_parameters(smu) smu_ppt_funcs(get_fan_parameters, 0, smu)
#define smu_post_init(smu) smu_ppt_funcs(post_init, 0, smu)
+#define smu_gpo_control(smu, enablement) smu_ppt_funcs(gpo_control, 0, smu, enablement)
#endif
#endif
--
2.28.0
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* Re: [PATCH 5/5] drm/amd/pm: properly setting GPO feature on UMD pstate entering/exiting
2020-10-14 7:18 ` [PATCH 5/5] drm/amd/pm: properly setting GPO feature on UMD pstate entering/exiting Evan Quan
@ 2020-10-14 19:59 ` Alex Deucher
0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2020-10-14 19:59 UTC (permalink / raw)
To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list
On Wed, Oct 14, 2020 at 3:18 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Disable/enable the GPO feature on UMD pstate entering/exiting.
>
> Change-Id: I4bd4b560b945227044df918c9066ffbbc17728ca
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 +
> drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 +
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 22 +++++++++++++++++++
> drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 +
> 5 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index f21d8dcac9ae..32f3738a6a6f 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -574,6 +574,7 @@ struct pptable_funcs {
> int (*get_fan_parameters)(struct smu_context *smu);
> int (*post_init)(struct smu_context *smu);
> void (*interrupt_work)(struct smu_context *smu);
> + int (*gpo_control)(struct smu_context *smu, bool enablement);
> };
>
> typedef enum {
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
> index b1a18fbb7682..f6403881f265 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
> @@ -184,6 +184,7 @@
> __SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \
> __SMU_DUMMY_MAP(PowerUpCvip), \
> __SMU_DUMMY_MAP(PowerDownCvip), \
> + __SMU_DUMMY_MAP(SetGpoFeaturePMask), \
>
> #undef __SMU_DUMMY_MAP
> #define __SMU_DUMMY_MAP(type) SMU_MSG_##type
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 92869eb297d8..18e0db34a3ee 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1407,6 +1407,7 @@ static int smu_enable_umd_pstate(void *handle,
> if (*level & profile_mode_mask) {
> smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
> smu_dpm_ctx->enable_umd_pstate = true;
> + smu_gpo_control(smu, false);
> amdgpu_device_ip_set_powergating_state(smu->adev,
> AMD_IP_BLOCK_TYPE_GFX,
> AMD_PG_STATE_UNGATE);
> @@ -1432,6 +1433,7 @@ static int smu_enable_umd_pstate(void *handle,
> amdgpu_device_ip_set_powergating_state(smu->adev,
> AMD_IP_BLOCK_TYPE_GFX,
> AMD_PG_STATE_GATE);
> + smu_gpo_control(smu, true);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index c27806fd07e0..71cb000306a4 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -127,6 +127,7 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
> MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
> MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
> MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
> + MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
> };
>
> static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
> @@ -2714,6 +2715,26 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
> NULL);
> }
>
> +static int sienna_cichlid_gpo_control(struct smu_context *smu,
> + bool enablement)
> +{
> + int ret = 0;
> +
> + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
> + if (enablement)
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> + SMU_MSG_SetGpoFeaturePMask,
> + GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
> + NULL);
> + else
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> + SMU_MSG_SetGpoFeaturePMask,
> + 0,
> + NULL);
> + }
> +
> + return ret;
> +}
> static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
> .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
> .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
> @@ -2795,6 +2816,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
> .deep_sleep_control = smu_v11_0_deep_sleep_control,
> .get_fan_parameters = sienna_cichlid_get_fan_parameters,
> .interrupt_work = smu_v11_0_interrupt_work,
> + .gpo_control = sienna_cichlid_gpo_control,
> };
>
> void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
> index c7e1fe5f442d..f7be2d1a0ff2 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
> @@ -89,6 +89,7 @@
> #define smu_deep_sleep_control(smu, enablement) smu_ppt_funcs(deep_sleep_control, 0, smu, enablement)
> #define smu_get_fan_parameters(smu) smu_ppt_funcs(get_fan_parameters, 0, smu)
> #define smu_post_init(smu) smu_ppt_funcs(post_init, 0, smu)
> +#define smu_gpo_control(smu, enablement) smu_ppt_funcs(gpo_control, 0, smu, enablement)
>
> #endif
> #endif
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-10-14 19:59 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-14 7:18 [PATCH 1/5] drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2) Evan Quan
2020-10-14 7:18 ` [PATCH 2/5] drm/amdgpu: add interface for setting ASPM Evan Quan
2020-10-14 7:18 ` [PATCH 3/5] drm/amdgpu: add interface for setting MGCG perfmon Evan Quan
2020-10-14 7:18 ` [PATCH 4/5] drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2) Evan Quan
2020-10-14 7:18 ` [PATCH 5/5] drm/amd/pm: properly setting GPO feature on UMD pstate entering/exiting Evan Quan
2020-10-14 19:59 ` Alex Deucher
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