From: Qingqing Zhuo <qingqing.zhuo@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
Bhawanpreet.Lakha@amd.com, Hugo Hu <hugo.hu@amd.com>
Subject: [PATCH 13/25] drm/amd/display: correct eDP T9 delay
Date: Tue, 27 Oct 2020 16:52:22 -0400 [thread overview]
Message-ID: <20201027205234.8239-14-qingqing.zhuo@amd.com> (raw)
In-Reply-To: <20201027205234.8239-1-qingqing.zhuo@amd.com>
From: Hugo Hu <hugo.hu@amd.com>
[Why]
The current end of T9 delay is relay on polling
sink status by DPCD. But the polling for sink
status change after NoVideoStream_flag set to 0.
[How]
Add function edp_add_delay_for_T9 to add T9 delay.
Move the sink status polling after blank.
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_hwss.c | 13 ++++++++-----
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 ++++++++--------
drivers/gpu/drm/amd/display/dc/inc/link_hwss.h | 1 +
3 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 11a619befb42..124ce215fca5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -156,6 +156,13 @@ void dp_enable_link_phy(
dp_receiver_power_ctrl(link, true);
}
+void edp_add_delay_for_T9(struct dc_link *link)
+{
+ if (link->local_sink &&
+ link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
+ udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
+}
+
bool edp_receiver_ready_T9(struct dc_link *link)
{
unsigned int tries = 0;
@@ -165,7 +172,7 @@ bool edp_receiver_ready_T9(struct dc_link *link)
result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
- /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
+ /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
if (result == DC_OK && edpRev >= DP_EDP_12) {
do {
sinkstatus = 1;
@@ -178,10 +185,6 @@ bool edp_receiver_ready_T9(struct dc_link *link)
} while (++tries < 50);
}
- if (link->local_sink &&
- link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
- udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
-
return result;
}
bool edp_receiver_ready_T7(struct dc_link *link)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 3ac6c7b65a45..9f56887029ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -992,8 +992,6 @@ void dce110_edp_backlight_control(
link_transmitter_control(ctx->dc_bios, &cntl);
-
-
if (enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_POST_T7_DELAY);
@@ -1004,7 +1002,7 @@ void dce110_edp_backlight_control(
/*edp 1.2*/
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
- edp_receiver_ready_T9(link);
+ edp_add_delay_for_T9(link);
if (!enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_PRE_T11_DELAY);
@@ -1145,12 +1143,14 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
- /*
- * After output is idle pattern some sinks need time to recognize the stream
- * has changed or they enter protection state and hang.
- */
- if (!dc_is_embedded_signal(pipe_ctx->stream->signal))
+ if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
+ /*
+ * After output is idle pattern some sinks need time to recognize the stream
+ * has changed or they enter protection state and hang.
+ */
msleep(60);
+ } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
+ edp_receiver_ready_T9(link);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 9af7ee5bc8ee..33590a728fc5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -51,6 +51,7 @@ void dp_enable_link_phy(
const struct dc_link_settings *link_settings);
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
+void edp_add_delay_for_T9(struct dc_link *link);
bool edp_receiver_ready_T9(struct dc_link *link);
bool edp_receiver_ready_T7(struct dc_link *link);
--
2.17.1
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next prev parent reply other threads:[~2020-10-27 20:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-27 20:52 [PATCH 00/25] DC Patches Nov 2nd, 2020 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 01/25] drm/amd/display: Fix compilation error Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 02/25] drm/amd/display: Add MPC memory shutdown support for DCN3 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 03/25] drm/amd/display: only check available pipe to disable vbios mode Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 04/25] drm/amd/display: Force prefetch mode to 0 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 05/25] drm/amd/display: Keep GSL for full updates with planes that flip VSYNC Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 06/25] drm/amd/display: [FW Promotion] Release 0.0.39 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 07/25] drm/amd/display: stop top_mgr when type change to non-MST during s3 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 08/25] drm/amd/display: Blank HUBP during pixel data blank for DCN30 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 09/25] drm/amd/display: 3.2.109 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 10/25] drm/amd/display: fail instead of div by zero/bugcheck Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 11/25] drm/amd/display: Update panel register Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 12/25] drm/amd/display: Add OPTC memory low power support Qingqing Zhuo
2020-10-27 20:52 ` Qingqing Zhuo [this message]
2020-10-27 20:52 ` [PATCH 14/25] drm/amd/display: Update connector on DSC property change Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 15/25] drm/amd/display: Reset flip_immediate to topmost plane Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 16/25] drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 17/25] drm/amd/display: Do not warn NULL dc_sink if forcing connector Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 18/25] drm/amd/display: Calculate CRC on specific frame region Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 19/25] drm/amd/display: WA to ensure MUX chip gets SUPPORTED_LINK_RATES of eDP Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 20/25] drm/amd/display: Revert HUBP blank behaviour for now Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 21/25] drm/amd/display: set hdcp1 wa re-auth delay to 200ms Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 22/25] drm/amd/display: Add missing pflip irq Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 23/25] drm/amd/display: [FW Promotion] Release 0.0.40 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 24/25] drm/amd/display: 3.2.110 Qingqing Zhuo
2020-10-27 20:52 ` [PATCH 25/25] drm/amd/display: fix recout calculation for left side clip Qingqing Zhuo
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