* [PATCH] drm/amd/amdgpu: Add rev_id workaround logic for SRIOV setup
@ 2020-10-27 22:01 Bokun Zhang
2020-11-09 2:26 ` Liu, Monk
0 siblings, 1 reply; 2+ messages in thread
From: Bokun Zhang @ 2020-10-27 22:01 UTC (permalink / raw)
To: amd-gfx; +Cc: Bokun Zhang
- When we are under SRIOV setup, the rev_id cannot be read
properly. Therefore, we will return default value for it
Change-Id: I188d8e1b77f97c2eb29ef01aaf9ff9ea396a51c2
Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index e0048806afaa..04c152843601 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -53,8 +53,20 @@ static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
{
- u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev)) {
+ /* workaround on rev_id for sriov
+ * guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
+ * as a consequence, the rev_id and external_rev_id are wrong.
+ *
+ * workaround it by hardcoding the rev_id to 0,
+ * (which is the default value)
+ */
+ return 0;
+ }
+ tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.25.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Add rev_id workaround logic for SRIOV setup
2020-10-27 22:01 [PATCH] drm/amd/amdgpu: Add rev_id workaround logic for SRIOV setup Bokun Zhang
@ 2020-11-09 2:26 ` Liu, Monk
0 siblings, 0 replies; 2+ messages in thread
From: Liu, Monk @ 2020-11-09 2:26 UTC (permalink / raw)
To: Zhang, Bokun, amd-gfx; +Cc: Zhang, Bokun
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Monk Liu <monk.liu@amd.com>
_____________________________________
Monk Liu|GPU Virtualization Team |AMD
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Bokun Zhang
Sent: Wednesday, October 28, 2020 6:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Bokun <Bokun.Zhang@amd.com>
Subject: [PATCH] drm/amd/amdgpu: Add rev_id workaround logic for SRIOV setup
- When we are under SRIOV setup, the rev_id cannot be read
properly. Therefore, we will return default value for it
Change-Id: I188d8e1b77f97c2eb29ef01aaf9ff9ea396a51c2
Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index e0048806afaa..04c152843601 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -53,8 +53,20 @@ static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) {
-u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+u32 tmp;
+
+if (amdgpu_sriov_vf(adev)) {
+/* workaround on rev_id for sriov
+* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
+* as a consequence, the rev_id and external_rev_id are wrong.
+*
+* workaround it by hardcoding the rev_id to 0,
+* (which is the default value)
+*/
+return 0;
+}
+tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.25.1
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