* [PATCH 1/3] drm:amdgpu: check before setting hw priority
@ 2020-11-09 18:12 Nirmoy Das
2020-11-09 18:12 ` [PATCH 2/3] drm/amdgpu: fix compute queue priority if num_kcq is less than 4 Nirmoy Das
2020-11-09 18:12 ` [PATCH 3/3] drm/amdgpu: enable only one compute queue for raven Nirmoy Das
0 siblings, 2 replies; 6+ messages in thread
From: Nirmoy Das @ 2020-11-09 18:12 UTC (permalink / raw)
To: amd-gfx
Cc: Guchun.Chen, felix.kuehling, Aaron.Liu, Nirmoy Das,
alexander.deucher, Christian.Koenig
Check validity of drm_gpu_scheduler before setting hw priority.
Also fix a minor indentation issue.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 0350205c4897..5e099f635040 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -504,9 +504,9 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
}
static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
- struct amdgpu_ctx_entity *aentity,
- int hw_ip,
- enum drm_sched_priority priority)
+ struct amdgpu_ctx_entity *aentity,
+ int hw_ip,
+ enum drm_sched_priority priority)
{
struct amdgpu_device *adev = ctx->adev;
unsigned int hw_prio;
@@ -523,6 +523,9 @@ static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX);
scheds = adev->gpu_sched[hw_ip][hw_prio].sched;
num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds;
+ if (!scheds || !num_scheds)
+ return;
+
drm_sched_entity_modify_sched(&aentity->entity, scheds,
num_scheds);
}
--
2.29.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] drm/amdgpu: fix compute queue priority if num_kcq is less than 4
2020-11-09 18:12 [PATCH 1/3] drm:amdgpu: check before setting hw priority Nirmoy Das
@ 2020-11-09 18:12 ` Nirmoy Das
2020-11-11 6:55 ` Felix Kuehling
2020-11-09 18:12 ` [PATCH 3/3] drm/amdgpu: enable only one compute queue for raven Nirmoy Das
1 sibling, 1 reply; 6+ messages in thread
From: Nirmoy Das @ 2020-11-09 18:12 UTC (permalink / raw)
To: amd-gfx
Cc: Guchun.Chen, felix.kuehling, Aaron.Liu, Nirmoy Das,
alexander.deucher, Christian.Koenig
Compute queues are configurable with module param, num_kcq.
amdgpu_gfx_is_high_priority_compute_queue was setting 1st 4 queues to
high priority queue leaving a null drm scheduler in
adev->gpu_sched[hw_ip]["normal_prio"].sched if num_kcq < 5.
This patch tries to fix it by alternating compute queue priority between
normal and high priority.
Fixes: 33abcb1f5a1719b1c (drm/amdgpu: set compute queue priority at mqd_init)
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 10 +++++++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 ++++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++++--
5 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index e584f48f3b54..97a8f786cf85 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -193,10 +193,14 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
}
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
- int queue)
+ int pipe, int queue)
{
- /* Policy: make queue 0 of each pipe as high priority compute queue */
- return (queue == 0);
+ bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
+ int cond;
+ /* Policy: alternate between normal and high priority */
+ cond = multipipe_policy ? pipe : queue;
+
+ return ((cond % 2) != 0);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 786eb4aa7314..671d4b37c397 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -374,7 +374,7 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
int pipe, int queue);
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
- int queue);
+ int pipe, int queue);
int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
int pipe, int queue);
void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8c3bad3dfc01..da5a139c7022 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4472,7 +4472,8 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
+ ring->pipe;
- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
+ ring->queue) ?
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
/* type-2 packets are deprecated on MEC, use type-3 instead */
r = amdgpu_ring_init(adev, ring, 1024,
@@ -6507,7 +6508,8 @@ static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct
struct amdgpu_device *adev = ring->adev;
if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
- if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
+ ring->queue)) {
mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
mqd->cp_hqd_queue_priority =
AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index c3fff49e6514..5e6d15f44560 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1923,7 +1923,8 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
+ ring->pipe;
- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
+ ring->queue) ?
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
/* type-2 packets are deprecated on MEC, use type-3 instead */
r = amdgpu_ring_init(adev, ring, 1024,
@@ -4441,7 +4442,8 @@ static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *m
struct amdgpu_device *adev = ring->adev;
if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
- if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
+ ring->queue)) {
mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
mqd->cp_hqd_queue_priority =
AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3d6fb5a514c8..5d53baadd6f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2228,7 +2228,8 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
+ ring->pipe;
- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
+ ring->queue) ?
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
/* type-2 packets are deprecated on MEC, use type-3 instead */
return amdgpu_ring_init(adev, ring, 1024,
@@ -3383,7 +3384,9 @@ static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *m
struct amdgpu_device *adev = ring->adev;
if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
- if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
+ if (amdgpu_gfx_is_high_priority_compute_queue(adev,
+ ring->pipe,
+ ring->queue)) {
mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
mqd->cp_hqd_queue_priority =
AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
--
2.29.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] drm/amdgpu: enable only one compute queue for raven
2020-11-09 18:12 [PATCH 1/3] drm:amdgpu: check before setting hw priority Nirmoy Das
2020-11-09 18:12 ` [PATCH 2/3] drm/amdgpu: fix compute queue priority if num_kcq is less than 4 Nirmoy Das
@ 2020-11-09 18:12 ` Nirmoy Das
2020-11-09 18:57 ` Alex Deucher
1 sibling, 1 reply; 6+ messages in thread
From: Nirmoy Das @ 2020-11-09 18:12 UTC (permalink / raw)
To: amd-gfx
Cc: Guchun.Chen, felix.kuehling, Aaron.Liu, Nirmoy Das,
alexander.deucher, Christian.Koenig
Because of firmware bug, Raven asics can't handle jobs
scheduled to multiple compute queues. So enable only one
compute queue till we have a firmware fix.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 97a8f786cf85..9352fcb77fe9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -812,6 +812,13 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
{
if (amdgpu_num_kcq == -1) {
+ /* raven firmware currently can not load balance jobs
+ * among multiple compute queues. Enable only one
+ * compute queue till we have a firmware fix.
+ */
+ if (adev->asic_type == CHIP_RAVEN)
+ return 1;
+
return 8;
} else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
--
2.29.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu: enable only one compute queue for raven
2020-11-09 18:12 ` [PATCH 3/3] drm/amdgpu: enable only one compute queue for raven Nirmoy Das
@ 2020-11-09 18:57 ` Alex Deucher
2020-11-10 15:14 ` Nirmoy
0 siblings, 1 reply; 6+ messages in thread
From: Alex Deucher @ 2020-11-09 18:57 UTC (permalink / raw)
To: Nirmoy Das
Cc: Chen, Guchun, Kuehling, Felix, Aaron Liu, amd-gfx list, Deucher,
Alexander, Christian Koenig
On Mon, Nov 9, 2020 at 1:12 PM Nirmoy Das <nirmoy.das@amd.com> wrote:
>
> Because of firmware bug, Raven asics can't handle jobs
> scheduled to multiple compute queues. So enable only one
> compute queue till we have a firmware fix.
>
> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 97a8f786cf85..9352fcb77fe9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -812,6 +812,13 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
> int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
> {
> if (amdgpu_num_kcq == -1) {
> + /* raven firmware currently can not load balance jobs
> + * among multiple compute queues. Enable only one
> + * compute queue till we have a firmware fix.
> + */
> + if (adev->asic_type == CHIP_RAVEN)
> + return 1;
> +
I think this is fine as a workaround for now, but it would be worth
checking is the issues are only between queues on the same pipe or
pipes on an MEC. E.g., can we safely enable one queue per MEC? What
about one queue per pipe?
Alex
> return 8;
> } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
> dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
> --
> 2.29.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu: enable only one compute queue for raven
2020-11-09 18:57 ` Alex Deucher
@ 2020-11-10 15:14 ` Nirmoy
0 siblings, 0 replies; 6+ messages in thread
From: Nirmoy @ 2020-11-10 15:14 UTC (permalink / raw)
To: Alex Deucher, Nirmoy Das
Cc: Chen, Guchun, Kuehling, Felix, Aaron Liu, amd-gfx list, Deucher,
Alexander, Christian Koenig
On 11/9/20 7:57 PM, Alex Deucher wrote:
> On Mon, Nov 9, 2020 at 1:12 PM Nirmoy Das <nirmoy.das@amd.com> wrote:
>> Because of firmware bug, Raven asics can't handle jobs
>> scheduled to multiple compute queues. So enable only one
>> compute queue till we have a firmware fix.
>>
>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> index 97a8f786cf85..9352fcb77fe9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> @@ -812,6 +812,13 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
>> int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
>> {
>> if (amdgpu_num_kcq == -1) {
>> + /* raven firmware currently can not load balance jobs
>> + * among multiple compute queues. Enable only one
>> + * compute queue till we have a firmware fix.
>> + */
>> + if (adev->asic_type == CHIP_RAVEN)
>> + return 1;
>> +
Hi Alex,
> I think this is fine as a workaround for now, but it would be worth
> checking is the issues are only between queues on the same pipe or
> pipes on an MEC. E.g., can we safely enable one queue per MEC? What
> about one queue per pipe?
Guchun/Aaron's test machine with a recent VBIOS(113-PICASSO-117) seems to
pass amdgpu_test with one compute queue.
I can reproduce the compute queue hang even with one queue.
With all queue enabled, the issue seems to appear much faster.
So I think those above cases won't change anything with my test
machine which is running older VBIOS(113-PICASSO-115).
I will try to find a test machine with latest VBIOS to test your
suggestions.
Regards,
Nirmoy
>
> Alex
>
>
>> return 8;
>> } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
>> dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
>> --
>> 2.29.0
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cnirmoy.das%40amd.com%7C5fee9c8359df4f41653508d884e162b3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637405450853281240%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=EKGmSryJhXMhWpo2XeT%2FTThcuv99%2BPAZ8MV%2Ff6sgmfo%3D&reserved=0
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/3] drm/amdgpu: fix compute queue priority if num_kcq is less than 4
2020-11-09 18:12 ` [PATCH 2/3] drm/amdgpu: fix compute queue priority if num_kcq is less than 4 Nirmoy Das
@ 2020-11-11 6:55 ` Felix Kuehling
0 siblings, 0 replies; 6+ messages in thread
From: Felix Kuehling @ 2020-11-11 6:55 UTC (permalink / raw)
To: Nirmoy Das, amd-gfx
Cc: alexander.deucher, Christian.Koenig, Guchun.Chen, Aaron.Liu
Am 2020-11-09 um 1:12 p.m. schrieb Nirmoy Das:
> Compute queues are configurable with module param, num_kcq.
> amdgpu_gfx_is_high_priority_compute_queue was setting 1st 4 queues to
> high priority queue leaving a null drm scheduler in
> adev->gpu_sched[hw_ip]["normal_prio"].sched if num_kcq < 5.
>
> This patch tries to fix it by alternating compute queue priority between
> normal and high priority.
>
> Fixes: 33abcb1f5a1719b1c (drm/amdgpu: set compute queue priority at mqd_init)
>
> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
This patch is
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 10 +++++++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++++--
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 ++++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++++--
> 5 files changed, 21 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index e584f48f3b54..97a8f786cf85 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -193,10 +193,14 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
> }
>
> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> - int queue)
> + int pipe, int queue)
> {
> - /* Policy: make queue 0 of each pipe as high priority compute queue */
> - return (queue == 0);
> + bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
> + int cond;
> + /* Policy: alternate between normal and high priority */
> + cond = multipipe_policy ? pipe : queue;
> +
> + return ((cond % 2) != 0);
>
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 786eb4aa7314..671d4b37c397 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -374,7 +374,7 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
> bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
> int pipe, int queue);
> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> - int queue);
> + int pipe, int queue);
> int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
> int pipe, int queue);
> void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 8c3bad3dfc01..da5a139c7022 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4472,7 +4472,8 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> + ring->pipe;
> - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
> + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
> + ring->queue) ?
> AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> r = amdgpu_ring_init(adev, ring, 1024,
> @@ -6507,7 +6508,8 @@ static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct
> struct amdgpu_device *adev = ring->adev;
>
> if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> - if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
> + ring->queue)) {
> mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> mqd->cp_hqd_queue_priority =
> AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index c3fff49e6514..5e6d15f44560 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1923,7 +1923,8 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> + ring->pipe;
>
> - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
> + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
> + ring->queue) ?
> AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> r = amdgpu_ring_init(adev, ring, 1024,
> @@ -4441,7 +4442,8 @@ static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *m
> struct amdgpu_device *adev = ring->adev;
>
> if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> - if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
> + ring->queue)) {
> mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> mqd->cp_hqd_queue_priority =
> AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 3d6fb5a514c8..5d53baadd6f5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2228,7 +2228,8 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> + ring->pipe;
> - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
> + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
> + ring->queue) ?
> AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> return amdgpu_ring_init(adev, ring, 1024,
> @@ -3383,7 +3384,9 @@ static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *m
> struct amdgpu_device *adev = ring->adev;
>
> if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> - if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev,
> + ring->pipe,
> + ring->queue)) {
> mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> mqd->cp_hqd_queue_priority =
> AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-11-11 6:55 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-09 18:12 [PATCH 1/3] drm:amdgpu: check before setting hw priority Nirmoy Das
2020-11-09 18:12 ` [PATCH 2/3] drm/amdgpu: fix compute queue priority if num_kcq is less than 4 Nirmoy Das
2020-11-11 6:55 ` Felix Kuehling
2020-11-09 18:12 ` [PATCH 3/3] drm/amdgpu: enable only one compute queue for raven Nirmoy Das
2020-11-09 18:57 ` Alex Deucher
2020-11-10 15:14 ` Nirmoy
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