AMD-GFX Archive on lore.kernel.org
 help / color / Atom feed
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Sung Lee <Sung.Lee@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Anson.Jacob@amd.com, Aurabindo.Pillai@amd.com,
	Bhawanpreet.Lakha@amd.com, Hugo Hu <hugo.hu@amd.com>,
	bindu.r@amd.com
Subject: [PATCH 07/19] drm/amd/display: treat memory as a single-channel for asymmetric memory v2
Date: Fri, 16 Apr 2021 10:34:05 -0400
Message-ID: <20210416143417.611019-8-aurabindo.pillai@amd.com> (raw)
In-Reply-To: <20210416143417.611019-1-aurabindo.pillai@amd.com>

From: Hugo Hu <hugo.hu@amd.com>

Previous change had been reverted since it caused hang.
Remake change to avoid defect.

[Why]
1. Driver use umachannelnumber to calculate watermarks for stutter.
In asymmetric memory config, the actual bandwidth is less than
dual-channel. The bandwidth should be the same as single-channel.
2. We found single rank dimm need additional delay time for stutter.

[How]
Get information from each DIMM. Treat memory config as a single-channel
for asymmetric memory in bandwidth calculating.
Add additional delay time for single rank dimm.

Fixes: 8a3e4b2516 ("drm/amd/display: System black screen hangs on driver load")
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 48 ++++++++++++++++++-
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +
 2 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 73e8878b03b6..a06e86853bb9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -769,6 +769,43 @@ static struct wm_table ddr4_wm_table_rn = {
 	}
 };
 
+static struct wm_table ddr4_1R_wm_table_rn = {
+	.entries = {
+		{
+			.wm_inst = WM_A,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 13.90,
+			.sr_enter_plus_exit_time_us = 14.80,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_B,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 13.90,
+			.sr_enter_plus_exit_time_us = 14.80,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_C,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 13.90,
+			.sr_enter_plus_exit_time_us = 14.80,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_D,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 13.90,
+			.sr_enter_plus_exit_time_us = 14.80,
+			.valid = true,
+		},
+	}
+};
+
 static struct wm_table lpddr4_wm_table_rn = {
 	.entries = {
 		{
@@ -953,8 +990,12 @@ void rn_clk_mgr_construct(
 		} else {
 			if (is_green_sardine)
 				rn_bw_params.wm_table = ddr4_wm_table_gs;
-			else
-				rn_bw_params.wm_table = ddr4_wm_table_rn;
+			else {
+				if (ctx->dc->config.is_single_rank_dimm)
+					rn_bw_params.wm_table = ddr4_1R_wm_table_rn;
+				else
+					rn_bw_params.wm_table = ddr4_wm_table_rn;
+			}
 		}
 		/* Saved clocks configured at boot for debug purposes */
 		rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
@@ -972,6 +1013,9 @@ void rn_clk_mgr_construct(
 		if (status == PP_SMU_RESULT_OK &&
 		    ctx->dc_bios && ctx->dc_bios->integrated_info) {
 			rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
+			/* treat memory config as single channel if memory is asymmetrics. */
+			if (ctx->dc->config.is_asymmetric_memory)
+				clk_mgr->base.bw_params->num_channels = 1;
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 82a324a618db..870cd7c6a387 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -308,6 +308,8 @@ struct dc_config {
 #endif
 	uint64_t vblank_alignment_dto_params;
 	uint8_t  vblank_alignment_max_frame_time_diff;
+	bool is_asymmetric_memory;
+	bool is_single_rank_dimm;
 };
 
 enum visual_confirm {
-- 
2.31.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply index

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-16 14:33 [PATCH 00/19] DC Patches for 2021 April 19 Aurabindo Pillai
2021-04-16 14:33 ` [PATCH 01/19] drm/amd/display: fixed divide by zero kernel crash during dsc enablement Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 02/19] drm/amd/display: Add DSC check to seamless boot validation Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 03/19] drm/amd/display: update hdcp display using correct CP type Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 04/19] drm/amd/display: add handling for hdcp2 rx id list validation Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 05/19] drm/amd/display: disable seamless boot for external DP Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 06/19] drm/amd/display: removed unused function dc_link_reallocate_mst_payload Aurabindo Pillai
2021-04-16 14:34 ` Aurabindo Pillai [this message]
2021-04-16 14:34 ` [PATCH 08/19] drm/amd/display: Fix FreeSync when RGB MPO in use Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 09/19] drm/amd/display: Unconditionally clear training pattern set after lt Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 10/19] drm/amd/display: Add link rate optimization logs for ILR Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 11/19] drm/amd/display: Always poll for rxstatus in authenticate Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 12/19] drm/amd/display: Fixed typo in function name Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 13/19] drm/amd/display: force CP to DESIRED when removing display Aurabindo Pillai
2021-04-19 15:42   ` Pillai, Aurabindo
2021-04-16 14:34 ` [PATCH 14/19] drm/amd/display: fix HDCP drm prop update for MST Aurabindo Pillai
2021-04-19 15:42   ` Pillai, Aurabindo
2021-04-16 14:34 ` [PATCH 15/19] drm/amd/display: Fix call to pass bpp in 16ths of a bit Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 16/19] drm/amd/display: Report Proper Quantization Range in AVI Infoframe Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 17/19] drm/amd/display: add helper for enabling mst stream features Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 18/19] drm/amd/display: [FW Promotion] Release 0.0.62 Aurabindo Pillai
2021-04-16 14:34 ` [PATCH 19/19] drm/amd/display: 3.2.132 Aurabindo Pillai
2021-04-19 15:45 ` [PATCH 00/19] DC Patches for 2021 April 19 Wheeler, Daniel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210416143417.611019-8-aurabindo.pillai@amd.com \
    --to=aurabindo.pillai@amd.com \
    --cc=Anson.Jacob@amd.com \
    --cc=Bhawanpreet.Lakha@amd.com \
    --cc=Eryk.Brol@amd.com \
    --cc=Harry.Wentland@amd.com \
    --cc=Qingqing.Zhuo@amd.com \
    --cc=Rodrigo.Siqueira@amd.com \
    --cc=Sung.Lee@amd.com \
    --cc=Sunpeng.Li@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=bindu.r@amd.com \
    --cc=hugo.hu@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

AMD-GFX Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/amd-gfx/0 amd-gfx/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 amd-gfx amd-gfx/ https://lore.kernel.org/amd-gfx \
		amd-gfx@lists.freedesktop.org
	public-inbox-index amd-gfx

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.freedesktop.lists.amd-gfx


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git