* [PATCH 00/16] DC Patches April 23, 2021
@ 2021-04-23 2:36 Wayne Lin
2021-04-23 2:36 ` [PATCH 01/16] drm/amd/display: Add new case to get spread spectrum info Wayne Lin
` (16 more replies)
0 siblings, 17 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:36 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai, Wayne Lin,
Bhawanpreet.Lakha, bindu.r
This DC patchset brings along following fixes:
* [FW Promotion] Release 0.0.63
* fix HDCP reset sequence on reinitialize
* Fix BSOD with NULL check
* Added multi instance support for ABM
* Revert wait vblank on update dpp clock
* skip program clock when allow seamless boot
* Add new DP_SEC registers for programming SDP Line number
* Add SE_DCN3_REG_LIST for control SDP num
* Add new case to get spread spectrum info
* fix wrong statement in mst hpd debugfs
* Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lock
* Expose internal display flag via debugfs
* take max dsc stream bandwidth overhead into account
* ddc resource data need to be initialized
* avoid to authentication when DEVICE_COUNT=0
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 22 +++-
.../drm/amd/display/dc/bios/bios_parser2.c | 2 +
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 10 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +--
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +++-
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 5 +-
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 30 +++++
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
.../drm/amd/display/dc/dcn21/dcn21_hwseq.c | 2 +-
.../dc/dcn30/dcn30_dio_stream_encoder.h | 4 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 2 +-
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 113 ++++++++++++++----
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 43 -------
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 2 -
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 88 ++++++++++++--
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 1 -
.../display/modules/hdcp/hdcp1_execution.c | 5 +
.../display/modules/hdcp/hdcp2_execution.c | 5 +
20 files changed, 260 insertions(+), 118 deletions(-)
--
2.17.1
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 01/16] drm/amd/display: Add new case to get spread spectrum info
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
@ 2021-04-23 2:36 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 02/16] drm/amd/display: fix HDCP reset sequence on reinitialize Wayne Lin
` (15 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:36 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai, Michael Strauss,
Bhawanpreet.Lakha, bindu.r
From: Michael Strauss <michael.strauss@amd.com>
[WHY]
New minor revision needs to be handled
[HOW]
Add switch case and assert to catch missing switch cases in the future
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index d79f4fe06c47..49126a0f66af 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -836,8 +836,10 @@ static enum bp_result bios_parser_get_spread_spectrum_info(
return get_ss_info_v4_1(bp, signal, index, ss_info);
case 2:
case 3:
+ case 4:
return get_ss_info_v4_2(bp, signal, index, ss_info);
default:
+ ASSERT(0);
break;
}
break;
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 02/16] drm/amd/display: fix HDCP reset sequence on reinitialize
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
2021-04-23 2:36 ` [PATCH 01/16] drm/amd/display: Add new case to get spread spectrum info Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 03/16] drm/amd/display: Revert wait vblank on update dpp clock Wayne Lin
` (14 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Brandon Syu, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Brandon Syu <Brandon.Syu@amd.com>
[why]
When setup is called after hdcp has already setup,
it would cause to disable HDCP flow won’t execute.
[how]
Don't clean up hdcp content to be 0.
Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index 68a6481d7f8f..b963226e8af4 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -260,7 +260,6 @@ enum mod_hdcp_status mod_hdcp_setup(struct mod_hdcp *hdcp,
struct mod_hdcp_output output;
enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
- memset(hdcp, 0, sizeof(struct mod_hdcp));
memset(&output, 0, sizeof(output));
hdcp->config = *config;
HDCP_TOP_INTERFACE_TRACE(hdcp);
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 03/16] drm/amd/display: Revert wait vblank on update dpp clock
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
2021-04-23 2:36 ` [PATCH 01/16] drm/amd/display: Add new case to get spread spectrum info Wayne Lin
2021-04-23 2:37 ` [PATCH 02/16] drm/amd/display: fix HDCP reset sequence on reinitialize Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 04/16] drm/amd/display: skip program clock when allow seamless boot Wayne Lin
` (13 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Lewis Huang, Eryk.Brol, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Lewis Huang <Lewis.Huang@amd.com>
[Why]
This change only fix dpp clock switch to lower case.
New solution later can fix both case, which is "dc: skip
program clock when allow seamless boot"
[How]
This reverts commit "dc: wait vblank when stream enabled
and update dpp clock"
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 10 +---------
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 -------------
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
3 files changed, 1 insertion(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index a06e86853bb9..49d19fdd750b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -128,7 +128,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
struct dc *dc = clk_mgr_base->ctx->dc;
- int display_count, i;
+ int display_count;
bool update_dppclk = false;
bool update_dispclk = false;
bool dpp_clock_lowered = false;
@@ -210,14 +210,6 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base->clks.dppclk_khz,
safe_to_lower);
- for (i = 0; i < context->stream_count; i++) {
- if (context->streams[i]->signal == SIGNAL_TYPE_EDP &&
- context->streams[i]->apply_seamless_boot_optimization) {
- dc_wait_for_vblank(dc, context->streams[i]);
- break;
- }
- }
-
clk_mgr_base->clks.actual_dppclk_khz =
rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4713f09bcbf1..e57df2f6f824 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3219,19 +3219,6 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
}
}
-void dc_wait_for_vblank(struct dc *dc, struct dc_stream_state *stream)
-{
- int i;
-
- for (i = 0; i < dc->res_pool->pipe_count; i++)
- if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
- struct timing_generator *tg =
- dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
- tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
- break;
- }
-}
-
void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
{
info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 100d434f7a03..65f801b50686 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -719,7 +719,6 @@ void dc_init_callbacks(struct dc *dc,
void dc_deinit_callbacks(struct dc *dc);
void dc_destroy(struct dc **dc);
-void dc_wait_for_vblank(struct dc *dc, struct dc_stream_state *stream);
/*******************************************************************************
* Surface Interfaces
******************************************************************************/
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 04/16] drm/amd/display: skip program clock when allow seamless boot
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (2 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 03/16] drm/amd/display: Revert wait vblank on update dpp clock Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 05/16] drm/amd/display: Expose internal display flag via debugfs Wayne Lin
` (12 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Lewis Huang, Eryk.Brol, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Lewis Huang <Lewis.Huang@amd.com>
[Why]
Driver program dpp clock calculate by pipe split config but hw config is single pipe.
[How]
Skip programming clock when allow seamless boot.
After porgramming pipe config, seamless boot flag will be clear.
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f4374d83662a..931fbb4d6169 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1206,14 +1206,25 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
{
const struct dc *dc = link->dc;
bool ret;
+ bool can_apply_seamless_boot = false;
+ int i;
+
+ for (i = 0; i < dc->current_state->stream_count; i++) {
+ if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
+ can_apply_seamless_boot = true;
+ break;
+ }
+ }
/* get out of low power state */
- clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
+ if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
+ clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
ret = dc_link_detect_helper(link, reason);
/* Go back to power optimized state */
- clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
+ if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
+ clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
return ret;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 05/16] drm/amd/display: Expose internal display flag via debugfs
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (3 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 04/16] drm/amd/display: skip program clock when allow seamless boot Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 06/16] drm/amd/display: ddc resource data need to be initialized Wayne Lin
` (11 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Stylon Wang, Eryk.Brol, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Stylon Wang <stylon.wang@amd.com>
[Why & How]
Add a per-connector debugfs entry to expose internal display flag,
which is indication that the display is "internally connected"
and not hotpluggable.
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 ++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 529545045a3e..656bc8f00a42 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -925,6 +925,22 @@ static int hdcp_sink_capability_show(struct seq_file *m, void *data)
return 0;
}
#endif
+
+/*
+ * Returns whether the connected display is internal and not hotpluggable.
+ * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
+ */
+static int internal_display_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+ struct dc_link *link = aconnector->dc_link;
+
+ seq_printf(m, "Internal: %u\n", link->is_internal_display);
+
+ return 0;
+}
+
/* function description
*
* generic SDP message access for testing
@@ -2369,6 +2385,7 @@ DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
#ifdef CONFIG_DRM_AMD_DC_HDCP
DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
#endif
+DEFINE_SHOW_ATTRIBUTE(internal_display);
static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
.owner = THIS_MODULE,
@@ -2600,7 +2617,8 @@ static const struct {
} connector_debugfs_entries[] = {
{"force_yuv420_output", &force_yuv420_output_fops},
{"output_bpc", &output_bpc_fops},
- {"trigger_hotplug", &trigger_hotplug_debugfs_fops}
+ {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
+ {"internal_display", &internal_display_fops}
};
void connector_debugfs_init(struct amdgpu_dm_connector *connector)
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 06/16] drm/amd/display: ddc resource data need to be initialized
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (4 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 05/16] drm/amd/display: Expose internal display flag via debugfs Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 07/16] drm/amd/display: Added multi instance support for ABM Wayne Lin
` (10 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Yu-ting Shen, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Yu-ting Shen <Yu-ting.Shen@amd.com>
[WHY]
to initial ddc structure before we use them to avoid error checking.
[HOW]
add 0 as structure initialization value in DCN resource construct
Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 527e56c353cb..6a56a03cfba3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3667,7 +3667,7 @@ static bool dcn20_resource_construct(
int i;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
- struct ddc_service_init_data ddc_init_data;
+ struct ddc_service_init_data ddc_init_data = {0};
struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
struct _vcs_dpi_ip_params_st *loaded_ip =
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 4a5fa23d8e7b..45f96221a094 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2538,7 +2538,7 @@ static bool dcn30_resource_construct(
int i;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
- struct ddc_service_init_data ddc_init_data;
+ struct ddc_service_init_data ddc_init_data = {0};
uint32_t pipe_fuses = read_pipe_fuses(ctx);
uint32_t num_pipes = 0;
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 07/16] drm/amd/display: Added multi instance support for ABM
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (5 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 06/16] drm/amd/display: ddc resource data need to be initialized Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 08/16] drm/amd/display: Fix BSOD with NULL check Wayne Lin
` (9 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Jake Wang, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Jake Wang <haonan.wang2@amd.com>
[WHY & HOW]
ABM assumes only 1 eDP is connected. Refactored existing
ABM interface to support multiple instances.
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 30 +++++++
.../drm/amd/display/dc/dcn21/dcn21_hwseq.c | 2 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 79 +++++++++++++++++--
3 files changed, 105 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index eb1698d54a48..6939ca2e8212 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -56,11 +56,19 @@ static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
{
union dmub_rb_cmd cmd;
uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0;
+ uint32_t edp_id_count = dc->dc_edp_id_count;
+ int i;
+ uint8_t panel_mask = 0;
+
+ for (i = 0; i < edp_id_count; i++)
+ panel_mask |= 0x01 << i;
memset(&cmd, 0, sizeof(cmd));
cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM;
cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC;
cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = fractional_pwm;
+ cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
+ cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.panel_mask = panel_mask;
cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pwm_frac_data);
dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
@@ -135,11 +143,24 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t level)
{
union dmub_rb_cmd cmd;
struct dc_context *dc = abm->ctx;
+ struct dc_link *edp_links[MAX_NUM_EDP];
+ int i;
+ int edp_num;
+ uint8_t panel_mask = 0;
+
+ get_edp_links(dc->dc, edp_links, &edp_num);
+
+ for (i = 0; i < edp_num; i++) {
+ if (edp_links[i]->link_status.link_active)
+ panel_mask |= (0x01 << i);
+ }
memset(&cmd, 0, sizeof(cmd));
cmd.abm_set_level.header.type = DMUB_CMD__ABM;
cmd.abm_set_level.header.sub_type = DMUB_CMD__ABM_SET_LEVEL;
cmd.abm_set_level.abm_set_level_data.level = level;
+ cmd.abm_set_level.abm_set_level_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
+ cmd.abm_set_level.abm_set_level_data.panel_mask = panel_mask;
cmd.abm_set_level.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_level_data);
dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
@@ -155,6 +176,12 @@ static bool dmub_abm_init_config(struct abm *abm,
{
union dmub_rb_cmd cmd;
struct dc_context *dc = abm->ctx;
+ uint32_t edp_id_count = dc->dc_edp_id_count;
+ int i;
+ uint8_t panel_mask = 0;
+
+ for (i = 0; i < edp_id_count; i++)
+ panel_mask |= 0x01 << i;
// TODO: Optimize by only reading back final 4 bytes
dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);
@@ -168,6 +195,9 @@ static bool dmub_abm_init_config(struct abm *abm,
cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG;
cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;
cmd.abm_init_config.abm_init_config_data.bytes = bytes;
+ cmd.abm_init_config.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
+ cmd.abm_init_config.abm_init_config_data.panel_mask = panel_mask;
+
cmd.abm_init_config.header.payload_bytes = sizeof(struct dmub_cmd_abm_init_config_data);
dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
index 8fccee5a3036..69cc192a7e71 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
@@ -218,7 +218,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;
cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp;
cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_pwm_u16_16;
- cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_1;
+ cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 << panel_cntl->inst);
cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data);
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 4195ff10c514..82c6e8a8a7c9 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -121,14 +121,14 @@
#define TRACE_BUFFER_ENTRY_OFFSET 16
/**
- * ABM backlight control version legacy
+ * ABM control version legacy
*/
-#define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_UNKNOWN 0x0
+#define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
/**
- * ABM backlight control version with multi edp support
+ * ABM control version with multi edp support
*/
-#define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_1 0x1
+#define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
/**
* Physical framebuffer address location, 64-bit.
@@ -1637,7 +1637,7 @@ struct dmub_cmd_abm_set_backlight_data {
uint32_t backlight_user_level;
/**
- * Backlight data version.
+ * ABM control version.
*/
uint8_t version;
@@ -1677,6 +1677,23 @@ struct dmub_cmd_abm_set_level_data {
* Set current ABM operating/aggression level.
*/
uint32_t level;
+
+ /**
+ * ABM control version.
+ */
+ uint8_t version;
+
+ /**
+ * Panel Control HW instance mask.
+ * Bit 0 is Panel Control HW instance 0.
+ * Bit 1 is Panel Control HW instance 1.
+ */
+ uint8_t panel_mask;
+
+ /**
+ * Explicit padding to 4 byte boundary.
+ */
+ uint8_t pad[2];
};
/**
@@ -1702,6 +1719,23 @@ struct dmub_cmd_abm_set_ambient_level_data {
* Ambient light sensor reading from OS.
*/
uint32_t ambient_lux;
+
+ /**
+ * ABM control version.
+ */
+ uint8_t version;
+
+ /**
+ * Panel Control HW instance mask.
+ * Bit 0 is Panel Control HW instance 0.
+ * Bit 1 is Panel Control HW instance 1.
+ */
+ uint8_t panel_mask;
+
+ /**
+ * Explicit padding to 4 byte boundary.
+ */
+ uint8_t pad[2];
};
/**
@@ -1728,6 +1762,23 @@ struct dmub_cmd_abm_set_pwm_frac_data {
* TODO: Convert to uint8_t.
*/
uint32_t fractional_pwm;
+
+ /**
+ * ABM control version.
+ */
+ uint8_t version;
+
+ /**
+ * Panel Control HW instance mask.
+ * Bit 0 is Panel Control HW instance 0.
+ * Bit 1 is Panel Control HW instance 1.
+ */
+ uint8_t panel_mask;
+
+ /**
+ * Explicit padding to 4 byte boundary.
+ */
+ uint8_t pad[2];
};
/**
@@ -1758,6 +1809,24 @@ struct dmub_cmd_abm_init_config_data {
* Indirect buffer length.
*/
uint16_t bytes;
+
+
+ /**
+ * ABM control version.
+ */
+ uint8_t version;
+
+ /**
+ * Panel Control HW instance mask.
+ * Bit 0 is Panel Control HW instance 0.
+ * Bit 1 is Panel Control HW instance 1.
+ */
+ uint8_t panel_mask;
+
+ /**
+ * Explicit padding to 4 byte boundary.
+ */
+ uint8_t pad[2];
};
/**
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 08/16] drm/amd/display: Fix BSOD with NULL check
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (6 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 07/16] drm/amd/display: Added multi instance support for ABM Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 09/16] drm/amd/display: Add new DP_SEC registers for programming SDP Line number Wayne Lin
` (8 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Chris Park, Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Chris Park <Chris.Park@amd.com>
[Why]
CLK mgr is null for server settings.
[How]
Guard the function with NULL check.
Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e57df2f6f824..a869702d77af 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3274,7 +3274,7 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)
if (dc->debug.disable_idle_power_optimizations)
return;
- if (dc->clk_mgr->funcs->is_smu_present)
+ if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
return;
--
2.17.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 09/16] drm/amd/display: Add new DP_SEC registers for programming SDP Line number
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (7 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 08/16] drm/amd/display: Fix BSOD with NULL check Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 10/16] drm/amd/display: Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lock Wayne Lin
` (7 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Max.Tseng, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: "Max.Tseng" <Max.Tseng@amd.com>
[Why]
Add register for programming in new platform
Signed-off-by: Max.Tseng <Max.Tseng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
index 0b1755f1dea8..a8f49ecb84ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
@@ -169,7 +169,9 @@
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\
SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 10/16] drm/amd/display: Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lock
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (8 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 09/16] drm/amd/display: Add new DP_SEC registers for programming SDP Line number Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 11/16] drm/amd/display: fix wrong statement in mst hpd debugfs Wayne Lin
` (6 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai, Robin Chen,
Bhawanpreet.Lakha, bindu.r
From: Robin Chen <robin.chen@amd.com>
[Why]
It seems there's a typo to set MASTER_UPDATE_LOCK_DB_EN when disable
doublebuffer lock.
[How]
Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lock
Signed-off-by: Robin Chen <robin.chen@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index 8980c90b2277..ac478bdcfb2a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -97,7 +97,7 @@ void optc3_lock_doublebuffer_disable(struct timing_generator *optc)
MASTER_UPDATE_LOCK_DB_END_Y, 0);
REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
- REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 1);
+ REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0);
}
void optc3_lock(struct timing_generator *optc)
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 11/16] drm/amd/display: fix wrong statement in mst hpd debugfs
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (9 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 10/16] drm/amd/display: Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lock Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 12/16] drm/amd/display: take max dsc stream bandwidth overhead into account Wayne Lin
` (5 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai, Mikita Lipski,
Bhawanpreet.Lakha, bindu.r
From: Mikita Lipski <mikita.lipski@amd.com>
[why]
Previous statement would always evaluate to true
making it meaningless
[how]
Just check if a connector is MST by checking if its port exists.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 656bc8f00a42..8bf0b566612b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -3030,7 +3030,7 @@ static int trigger_hpd_mst_set(void *data, u64 val)
if (!aconnector->dc_link)
continue;
- if (!(aconnector->port && &aconnector->mst_port->mst_mgr))
+ if (!aconnector->mst_port)
continue;
link = aconnector->dc_link;
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 12/16] drm/amd/display: take max dsc stream bandwidth overhead into account
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (10 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 11/16] drm/amd/display: fix wrong statement in mst hpd debugfs Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 13/16] drm/amd/display: avoid to authentication when DEVICE_COUNT=0 Wayne Lin
` (4 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Wenjing Liu, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
As hardware team suggested that we need to add a max dsc bw overhead
into existing stream bandwidth when DSC is used.
The formula as below:
max_dsc_bw_overhead =
v_addressable * slice_count * 256 bit * pixel clock / v_total / h_total
effective stream bandwidth = pixel clock * bpp
stream bandwidth = effective stream bandwidth + dsc stream overhead
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 +-
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 5 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 113 ++++++++++++++----
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 43 -------
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 2 -
5 files changed, 94 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 931fbb4d6169..8bbed9c90c5d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3486,9 +3486,10 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
uint32_t kbps;
#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (timing->flags.DSC) {
- return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, timing->dsc_cfg.bits_per_pixel);
- }
+ if (timing->flags.DSC)
+ return dc_dsc_stream_bandwidth_in_kbps(timing,
+ timing->dsc_cfg.bits_per_pixel,
+ timing->dsc_cfg.num_slices_h);
#endif
switch (timing->display_color_depth) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index c51d2d961b7a..afddb8b7d3e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -78,7 +78,8 @@ bool dc_dsc_compute_config(
const struct dc_crtc_timing *timing,
struct dc_dsc_config *dsc_cfg);
-uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16);
+uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
+ uint32_t bpp_x16, uint32_t num_slices_h);
void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
uint32_t max_target_bpp_limit_override_x16,
@@ -88,6 +89,4 @@ void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);
-uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16);
-
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index be57088d185d..bfe3ad58070a 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -258,12 +258,58 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t value)
return (value + 9) / 10;
}
+static struct fixed31_32 compute_dsc_max_bandwidth_overhead(
+ const struct dc_crtc_timing *timing,
+ const int num_slices_h)
+{
+ struct fixed31_32 max_dsc_overhead;
+ struct fixed31_32 refresh_rate;
+
+ /* use target bpp that can take entire target bandwidth */
+ refresh_rate = dc_fixpt_from_int(timing->pix_clk_100hz);
+ refresh_rate = dc_fixpt_div_int(refresh_rate, timing->h_total);
+ refresh_rate = dc_fixpt_div_int(refresh_rate, timing->v_total);
+ refresh_rate = dc_fixpt_mul_int(refresh_rate, 100);
+
+ max_dsc_overhead = dc_fixpt_from_int(num_slices_h);
+ max_dsc_overhead = dc_fixpt_mul_int(max_dsc_overhead, timing->v_addressable);
+ max_dsc_overhead = dc_fixpt_mul_int(max_dsc_overhead, 256);
+ max_dsc_overhead = dc_fixpt_div_int(max_dsc_overhead, 1000);
+ max_dsc_overhead = dc_fixpt_mul(max_dsc_overhead, refresh_rate);
+
+ return max_dsc_overhead;
+}
+
+static uint32_t compute_bpp_x16_from_target_bandwidth(
+ const uint32_t bandwidth_in_kbps,
+ const struct dc_crtc_timing *timing,
+ const uint32_t num_slices_h,
+ const uint32_t bpp_increment_div)
+{
+ struct fixed31_32 overhead_in_kbps;
+ struct fixed31_32 effective_bandwidth_in_kbps;
+ struct fixed31_32 bpp_x16;
+
+ overhead_in_kbps = compute_dsc_max_bandwidth_overhead(
+ timing, num_slices_h);
+ effective_bandwidth_in_kbps = dc_fixpt_from_int(bandwidth_in_kbps);
+ effective_bandwidth_in_kbps = dc_fixpt_sub(effective_bandwidth_in_kbps,
+ overhead_in_kbps);
+ bpp_x16 = dc_fixpt_mul_int(effective_bandwidth_in_kbps, 10);
+ bpp_x16 = dc_fixpt_div_int(bpp_x16, timing->pix_clk_100hz);
+ bpp_x16 = dc_fixpt_from_int(dc_fixpt_floor(dc_fixpt_mul_int(bpp_x16, bpp_increment_div)));
+ bpp_x16 = dc_fixpt_div_int(bpp_x16, bpp_increment_div);
+ bpp_x16 = dc_fixpt_mul_int(bpp_x16, 16);
+ return dc_fixpt_floor(bpp_x16);
+}
+
/* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clock
* and uncompressed bandwidth.
*/
static void get_dsc_bandwidth_range(
const uint32_t min_bpp_x16,
const uint32_t max_bpp_x16,
+ const uint32_t num_slices_h,
const struct dsc_enc_caps *dsc_caps,
const struct dc_crtc_timing *timing,
struct dc_dsc_bw_range *range)
@@ -272,16 +318,20 @@ static void get_dsc_bandwidth_range(
range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing);
/* max dsc target bpp */
- range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, max_bpp_x16);
+ range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing,
+ max_bpp_x16, num_slices_h);
range->max_target_bpp_x16 = max_bpp_x16;
if (range->max_kbps > range->stream_kbps) {
/* max dsc target bpp is capped to native bandwidth */
range->max_kbps = range->stream_kbps;
- range->max_target_bpp_x16 = calc_dsc_bpp_x16(range->stream_kbps, timing->pix_clk_100hz, dsc_caps->bpp_increment_div);
+ range->max_target_bpp_x16 = compute_bpp_x16_from_target_bandwidth(
+ range->max_kbps, timing, num_slices_h,
+ dsc_caps->bpp_increment_div);
}
/* min dsc target bpp */
- range->min_kbps = dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, min_bpp_x16);
+ range->min_kbps = dc_dsc_stream_bandwidth_in_kbps(timing,
+ min_bpp_x16, num_slices_h);
range->min_target_bpp_x16 = min_bpp_x16;
if (range->min_kbps > range->max_kbps) {
/* min dsc target bpp is capped to max dsc bandwidth*/
@@ -290,7 +340,6 @@ static void get_dsc_bandwidth_range(
}
}
-
/* Decides if DSC should be used and calculates target bpp if it should, applying DSC policy.
*
* Returns:
@@ -303,6 +352,7 @@ static bool decide_dsc_target_bpp_x16(
const struct dsc_enc_caps *dsc_common_caps,
const int target_bandwidth_kbps,
const struct dc_crtc_timing *timing,
+ const int num_slices_h,
int *target_bpp_x16)
{
bool should_use_dsc = false;
@@ -311,7 +361,7 @@ static bool decide_dsc_target_bpp_x16(
memset(&range, 0, sizeof(range));
get_dsc_bandwidth_range(policy->min_target_bpp * 16, policy->max_target_bpp * 16,
- dsc_common_caps, timing, &range);
+ num_slices_h, dsc_common_caps, timing, &range);
if (!policy->enable_dsc_when_not_needed && target_bandwidth_kbps >= range.stream_kbps) {
/* enough bandwidth without dsc */
*target_bpp_x16 = 0;
@@ -327,7 +377,11 @@ static bool decide_dsc_target_bpp_x16(
should_use_dsc = true;
} else if (target_bandwidth_kbps >= range.min_kbps) {
/* use target bpp that can take entire target bandwidth */
- *target_bpp_x16 = calc_dsc_bpp_x16(target_bandwidth_kbps, timing->pix_clk_100hz, dsc_common_caps->bpp_increment_div);
+ *target_bpp_x16 = compute_bpp_x16_from_target_bandwidth(
+ range.max_kbps, timing, num_slices_h,
+ dsc_common_caps->bpp_increment_div);
+ if (*target_bpp_x16 < range.min_kbps)
+ *target_bpp_x16 = range.min_kbps;
should_use_dsc = true;
} else {
/* not enough bandwidth to fulfill minimum requirement */
@@ -531,18 +585,6 @@ static bool setup_dsc_config(
if (!is_dsc_possible)
goto done;
- if (target_bandwidth_kbps > 0) {
- is_dsc_possible = decide_dsc_target_bpp_x16(
- &policy,
- &dsc_common_caps,
- target_bandwidth_kbps,
- timing,
- &target_bpp);
- dsc_cfg->bits_per_pixel = target_bpp;
- }
- if (!is_dsc_possible)
- goto done;
-
sink_per_slice_throughput_mps = 0;
// Validate available DSC settings against the mode timing
@@ -690,6 +732,19 @@ static bool setup_dsc_config(
dsc_cfg->num_slices_v = pic_height/slice_height;
+ if (target_bandwidth_kbps > 0) {
+ is_dsc_possible = decide_dsc_target_bpp_x16(
+ &policy,
+ &dsc_common_caps,
+ target_bandwidth_kbps,
+ timing,
+ num_slices_h,
+ &target_bpp);
+ dsc_cfg->bits_per_pixel = target_bpp;
+ }
+ if (!is_dsc_possible)
+ goto done;
+
// Final decission: can we do DSC or not?
if (is_dsc_possible) {
// Fill out the rest of DSC settings
@@ -838,7 +893,8 @@ bool dc_dsc_compute_bandwidth_range(
dsc_min_slice_height_override, max_bpp_x16, &config);
if (is_dsc_possible)
- get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, &dsc_common_caps, timing, range);
+ get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16,
+ config.num_slices_h, &dsc_common_caps, timing, range);
return is_dsc_possible;
}
@@ -864,13 +920,20 @@ bool dc_dsc_compute_config(
return is_dsc_possible;
}
-uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16)
+uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
+ uint32_t bpp_x16, uint32_t num_slices_h)
{
- struct fixed31_32 link_bw_kbps;
- link_bw_kbps = dc_fixpt_from_int(pix_clk_100hz);
- link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
- link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, bpp_x16);
- return dc_fixpt_ceil(link_bw_kbps);
+ struct fixed31_32 overhead_in_kbps;
+ struct fixed31_32 bpp;
+ struct fixed31_32 actual_bandwidth_in_kbps;
+
+ overhead_in_kbps = compute_dsc_max_bandwidth_overhead(
+ timing, num_slices_h);
+ bpp = dc_fixpt_from_fraction(bpp_x16, 16);
+ actual_bandwidth_in_kbps = dc_fixpt_from_fraction(timing->pix_clk_100hz, 10);
+ actual_bandwidth_in_kbps = dc_fixpt_mul(actual_bandwidth_in_kbps, bpp);
+ actual_bandwidth_in_kbps = dc_fixpt_add(actual_bandwidth_in_kbps, overhead_in_kbps);
+ return dc_fixpt_ceil(actual_bandwidth_in_kbps);
}
void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, struct dc_dsc_policy *policy)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index c6a1cd80aeae..7b294f637881 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -284,26 +284,6 @@ static u32 _do_bytes_per_pixel_calc(int slice_width, u16 drm_bpp,
return bytes_per_pixel;
}
-static u32 _do_calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz,
- u32 bpp_increment_div)
-{
- u32 dsc_target_bpp_x16;
- float f_dsc_target_bpp;
- float f_stream_bandwidth_100bps;
- // bpp_increment_div is actually precision
- u32 precision = bpp_increment_div;
-
- f_stream_bandwidth_100bps = stream_bandwidth_kbps * 10.0f;
- f_dsc_target_bpp = f_stream_bandwidth_100bps / pix_clk_100hz;
-
- // Round down to the nearest precision stop to bring it into DSC spec
- // range
- dsc_target_bpp_x16 = (u32)(f_dsc_target_bpp * precision);
- dsc_target_bpp_x16 = (dsc_target_bpp_x16 * 16) / precision;
-
- return dsc_target_bpp_x16;
-}
-
/**
* calc_rc_params - reads the user's cmdline mode
* @rc: DC internal DSC parameters
@@ -367,26 +347,3 @@ u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps)
DC_FP_END();
return ret;
}
-
-/**
- * calc_dsc_bpp_x16 - retrieve the dsc bits per pixel
- * @stream_bandwidth_kbps:
- * @pix_clk_100hz:
- * @bpp_increment_div:
- *
- * Calculate the total of bits per pixel for DSC configuration.
- *
- * @note This calculation requires float point operation, most of it executes
- * under kernel_fpu_{begin,end}.
- */
-u32 calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz,
- u32 bpp_increment_div)
-{
- u32 dsc_bpp;
-
- DC_FP_START();
- dsc_bpp = _do_calc_dsc_bpp_x16(stream_bandwidth_kbps, pix_clk_100hz,
- bpp_increment_div);
- DC_FP_END();
- return dsc_bpp;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
index 8123827840c5..262f06afcbf9 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
@@ -79,8 +79,6 @@ typedef struct qp_entry qp_table[];
void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps);
u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps);
-u32 calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz,
- u32 bpp_increment_div);
#endif
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 13/16] drm/amd/display: avoid to authentication when DEVICE_COUNT=0
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (11 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 12/16] drm/amd/display: take max dsc stream bandwidth overhead into account Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 14/16] drm/amd/display: Add SE_DCN3_REG_LIST for control SDP num Wayne Lin
` (3 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Yu-ting Shen, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Yu-ting Shen <Yu-ting.Shen@amd.com>
[why]
we don't support authentication with DEVICE_COUNT=0
[how]
check value DEVICE_COUNT before doing authentication
Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c | 5 +++++
drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
index 2cbd931363bd..43e6f8b17e79 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
@@ -128,6 +128,11 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
{
+ /* Avoid device count == 0 to do authentication */
+ if (0 == get_device_count(hdcp)) {
+ return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE;
+ }
+
/* Some MST display may choose to report the internal panel as an HDCP RX.
* To update this condition with 1(because the immediate repeater's internal
* panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp).
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
index c1331facdcb4..117c6b45f718 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
@@ -207,6 +207,11 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
{
+ /* Avoid device count == 0 to do authentication */
+ if (0 == get_device_count(hdcp)) {
+ return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE;
+ }
+
/* Some MST display may choose to report the internal panel as an HDCP RX. */
/* To update this condition with 1(because the immediate repeater's internal */
/* panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp). */
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 14/16] drm/amd/display: Add SE_DCN3_REG_LIST for control SDP num
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (12 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 13/16] drm/amd/display: avoid to authentication when DEVICE_COUNT=0 Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 15/16] drm/amd/display: [FW Promotion] Release 0.0.63 Wayne Lin
` (2 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Max.Tseng, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: "Max.Tseng" <Max.Tseng@amd.com>
[Why] New platform. Need to add corresponding register control
Signed-off-by: Max.Tseng <Max.Tseng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
index a8f49ecb84ba..9566b9037458 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
@@ -85,7 +85,9 @@
SRI(DP_MSE_RATE_UPDATE, DP, id), \
SRI(DP_PIXEL_FORMAT, DP, id), \
SRI(DP_SEC_CNTL, DP, id), \
+ SRI(DP_SEC_CNTL1, DP, id), \
SRI(DP_SEC_CNTL2, DP, id), \
+ SRI(DP_SEC_CNTL5, DP, id), \
SRI(DP_SEC_CNTL6, DP, id), \
SRI(DP_STEER_FIFO, DP, id), \
SRI(DP_VID_M, DP, id), \
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 15/16] drm/amd/display: [FW Promotion] Release 0.0.63
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (13 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 14/16] drm/amd/display: Add SE_DCN3_REG_LIST for control SDP num Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 2:37 ` [PATCH 16/16] drm/amd/display: 3.2.133 Wayne Lin
2021-04-23 19:36 ` [PATCH 00/16] DC Patches April 23, 2021 Wheeler, Daniel
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Anthony Koo, Eryk.Brol, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 82c6e8a8a7c9..95fab1d3d7af 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x23db9b126
+#define DMUB_FW_VERSION_GIT_HASH 0x41548deb6
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 62
+#define DMUB_FW_VERSION_REVISION 63
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@@ -117,6 +117,8 @@
/* Maximum number of planes on any ASIC. */
#define DMUB_MAX_PLANES 6
+#define DMUB_MAX_SUBVP_STREAMS 2
+
/* Trace buffer offset for entry */
#define TRACE_BUFFER_ENTRY_OFFSET 16
@@ -328,7 +330,8 @@ union dmub_fw_boot_options {
uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
- uint32_t reserved : 26; /**< reserved */
+ uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */
+ uint32_t reserved : 25; /**< reserved */
} bits; /**< boot bits */
uint32_t all; /**< 32-bit access to bits */
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 16/16] drm/amd/display: 3.2.133
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (14 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 15/16] drm/amd/display: [FW Promotion] Release 0.0.63 Wayne Lin
@ 2021-04-23 2:37 ` Wayne Lin
2021-04-23 19:36 ` [PATCH 00/16] DC Patches April 23, 2021 Wheeler, Daniel
16 siblings, 0 replies; 18+ messages in thread
From: Wayne Lin @ 2021-04-23 2:37 UTC (permalink / raw)
To: amd-gfx
Cc: Aric Cyr, Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Anson.Jacob, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Aric Cyr <aric.cyr@amd.com>
This DC patchset brings along following fixes:
* [FW Promotion] Release 0.0.63
* fix HDCP reset sequence on reinitialize
* Fix BSOD with NULL check
* Added multi instance support for ABM
* Revert wait vblank on update dpp clock
* skip program clock when allow seamless boot
* Add new DP_SEC registers for programming SDP Line number
* Add SE_DCN3_REG_LIST for control SDP num
* Add new case to get spread spectrum info
* fix wrong statement in mst hpd debugfs
* Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lock
* Expose internal display flag via debugfs
* take max dsc stream bandwidth overhead into account
* ddc resource data need to be initialized
* avoid to authentication when DEVICE_COUNT=0
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 65f801b50686..dba2584e8986 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
/* forward declaration */
struct aux_payload;
-#define DC_VER "3.2.132"
+#define DC_VER "3.2.133"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.17.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* RE: [PATCH 00/16] DC Patches April 23, 2021
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
` (15 preceding siblings ...)
2021-04-23 2:37 ` [PATCH 16/16] drm/amd/display: 3.2.133 Wayne Lin
@ 2021-04-23 19:36 ` Wheeler, Daniel
16 siblings, 0 replies; 18+ messages in thread
From: Wheeler, Daniel @ 2021-04-23 19:36 UTC (permalink / raw)
To: Lin, Wayne, amd-gfx
Cc: Brol, Eryk, Li, Sun peng (Leo),
Lakha, Bhawanpreet, Zhuo, Qingqing, Siqueira, Rodrigo, Jacob,
Anson, Pillai, Aurabindo, Lin, Wayne, Wentland, Harry, R, Bindu
[AMD Public Use]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, on the following display types:
eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Sapphire Pulse RX5700XT on the following display types:
4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Reference AMD RX6800 on the following display types:
4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz on all systems.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Technologist | AMD
SW Display------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook | Twitter | amd.com
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Wayne Lin
Sent: April 22, 2021 10:37 PM
To: amd-gfx@lists.freedesktop.org
Cc: Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Jacob, Anson <Anson.Jacob@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; R, Bindu <Bindu.R@amd.com>
Subject: [PATCH 00/16] DC Patches April 23, 2021
This DC patchset brings along following fixes:
* [FW Promotion] Release 0.0.63
* fix HDCP reset sequence on reinitialize
* Fix BSOD with NULL check
* Added multi instance support for ABM
* Revert wait vblank on update dpp clock
* skip program clock when allow seamless boot
* Add new DP_SEC registers for programming SDP Line number
* Add SE_DCN3_REG_LIST for control SDP num
* Add new case to get spread spectrum info
* fix wrong statement in mst hpd debugfs
* Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lock
* Expose internal display flag via debugfs
* take max dsc stream bandwidth overhead into account
* ddc resource data need to be initialized
* avoid to authentication when DEVICE_COUNT=0
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 22 +++-
.../drm/amd/display/dc/bios/bios_parser2.c | 2 +
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 10 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +--
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +++-
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 5 +-
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 30 +++++
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
.../drm/amd/display/dc/dcn21/dcn21_hwseq.c | 2 +-
.../dc/dcn30/dcn30_dio_stream_encoder.h | 4 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 2 +-
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 113 ++++++++++++++----
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 43 -------
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 2 -
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 88 ++++++++++++--
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 1 -
.../display/modules/hdcp/hdcp1_execution.c | 5 +
.../display/modules/hdcp/hdcp2_execution.c | 5 +
20 files changed, 260 insertions(+), 118 deletions(-)
--
2.17.1
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-- links below jump to the message on this page --
2021-04-23 2:36 [PATCH 00/16] DC Patches April 23, 2021 Wayne Lin
2021-04-23 2:36 ` [PATCH 01/16] drm/amd/display: Add new case to get spread spectrum info Wayne Lin
2021-04-23 2:37 ` [PATCH 02/16] drm/amd/display: fix HDCP reset sequence on reinitialize Wayne Lin
2021-04-23 2:37 ` [PATCH 03/16] drm/amd/display: Revert wait vblank on update dpp clock Wayne Lin
2021-04-23 2:37 ` [PATCH 04/16] drm/amd/display: skip program clock when allow seamless boot Wayne Lin
2021-04-23 2:37 ` [PATCH 05/16] drm/amd/display: Expose internal display flag via debugfs Wayne Lin
2021-04-23 2:37 ` [PATCH 06/16] drm/amd/display: ddc resource data need to be initialized Wayne Lin
2021-04-23 2:37 ` [PATCH 07/16] drm/amd/display: Added multi instance support for ABM Wayne Lin
2021-04-23 2:37 ` [PATCH 08/16] drm/amd/display: Fix BSOD with NULL check Wayne Lin
2021-04-23 2:37 ` [PATCH 09/16] drm/amd/display: Add new DP_SEC registers for programming SDP Line number Wayne Lin
2021-04-23 2:37 ` [PATCH 10/16] drm/amd/display: Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lock Wayne Lin
2021-04-23 2:37 ` [PATCH 11/16] drm/amd/display: fix wrong statement in mst hpd debugfs Wayne Lin
2021-04-23 2:37 ` [PATCH 12/16] drm/amd/display: take max dsc stream bandwidth overhead into account Wayne Lin
2021-04-23 2:37 ` [PATCH 13/16] drm/amd/display: avoid to authentication when DEVICE_COUNT=0 Wayne Lin
2021-04-23 2:37 ` [PATCH 14/16] drm/amd/display: Add SE_DCN3_REG_LIST for control SDP num Wayne Lin
2021-04-23 2:37 ` [PATCH 15/16] drm/amd/display: [FW Promotion] Release 0.0.63 Wayne Lin
2021-04-23 2:37 ` [PATCH 16/16] drm/amd/display: 3.2.133 Wayne Lin
2021-04-23 19:36 ` [PATCH 00/16] DC Patches April 23, 2021 Wheeler, Daniel
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