DC Patches Apri 6, 2022

DC Patches Apri 6, 2022

[Pavle Kotarac]

This DC patchset brings improvements in multiple areas. In summary, we highlight:
    
    *Disabling Z10 on DCN31
    *Fix issue breaking 32bit Linux build
    *Fix inconsistent timestamp type
    *Add DCN30 support FEC init
    *Fix crash on setting VRR with no display connected
    *Disable FEC if DSC not supported for EDP
    *Add odm seamless boot support
    *Select correct DTO source
    *Power down hardware if timer not trigger


AMD\syerizvi (1):
  drm/amd/display: Disabling Z10 on DCN31

Angus Wang (1):
  drm/amd/display: Fix inconsistent timestamp type

Aric Cyr (1):
  drm/amd/display: 3.2.181

Charlene Liu (1):
  drm/amd/display: remove dtbclk_ss compensation for dcn316

David Zhang (1):
  drm/amd/display: implement shared PSR-SU sink validation helper

Dillon Varone (2):
  drm/amd/display: Add dtb clock to dc_clocks
  drm/amd/display: Select correct DTO source

Duncan Ma (1):
  drm/amd/display: Add odm seamless boot support

Eric Yang (1):
  drm/amd/display: undo clearing of z10 related function pointers

Evgenii Krasnikov (1):
  drm/amd/display: ensure PSR force_static flag can always be set

Harry VanZyllDeJong (1):
  drm/amd/display: Fix crash on setting VRR with no display connected

Hayden Goodfellow (1):
  drm/amd/display: Fix issue breaking 32bit Linux build

Iswara Nagulendran (1):
  drm/amd/display: Disable FEC if DSC not supported for EDP

Jingwen Zhu (1):
  drm/amd/display: add DCN30 support FEC init

Josip Pavic (1):
  drm/amd/display: do not wait for mpc idle if tg is disabled

Max Erenberg (1):
  drm/amd/display: Disallow entering PSR when panel is disconnected

Oliver Logush (2):
  drm/amd/display: Insert pulling smu busy status before sending another
    request
  drm/amd/display: Always update DPPCLK_DTO when clock increase

Paul Hsieh (1):
  drm/amd/display: Power down hardware if timer not trigger

hersen wu (1):
  drm/amd/display: expose skip_detection_link_training to debugfs

 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 37 +++++++++
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  9 +-
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   |  2 +-
 .../dc/clk_mgr/dcn201/dcn201_clk_mgr.c        |  3 +-
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 17 +++-
 .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   |  3 +
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c    |  3 +-
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  | 26 +++++-
 .../dc/clk_mgr/dcn316/dcn316_clk_mgr.c        |  4 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 13 +++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17 +++-
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 82 ++++++++++++-------
 drivers/gpu/drm/amd/display/dc/dc.h           |  6 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  1 +
 .../drm/amd/display/dc/dce/dce_clock_source.c |  2 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 40 +++++++--
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    |  6 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_init.c |  5 --
 .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 21 +++++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.h |  2 +
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  1 +
 .../amd/display/dc/inc/hw/timing_generator.h  |  2 +
 .../amd/display/modules/freesync/freesync.c   |  5 +-
 .../amd/display/modules/power/power_helpers.c | 38 +++++++++
 .../amd/display/modules/power/power_helpers.h |  1 +
 25 files changed, 285 insertions(+), 61 deletions(-)

-- 
2.32.0

[PATCH 01/20] drm/amd/display: undo clearing of z10 related function pointers

[Pavle Kotarac]

From: Eric Yang <Eric.Yang2@amd.com>

[Why]
Z10 and S0i3 have some shared path. Previous code clean up ,
incorrectly removed these pointers, which breaks s0i3 restore

[How]
Do not clear the function pointers based on Z10 disable.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
index d7559e5a99ce..e708f07fe75a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -153,9 +153,4 @@ void dcn31_hw_sequencer_construct(struct dc *dc)
 		dc->hwss.init_hw = dcn20_fpga_init_hw;
 		dc->hwseq->funcs.init_pipes = NULL;
 	}
-	if (dc->debug.disable_z10) {
-		/*hw not support z10 or sw disable it*/
-		dc->hwss.z10_restore = NULL;
-		dc->hwss.z10_save_init = NULL;
-	}
 }
-- 
2.32.0

[PATCH 02/20] drm/amd/display: do not wait for mpc idle if tg is disabled

[Pavle Kotarac]

From: Josip Pavic <Josip.Pavic@amd.com>

[Why]
When booting, the driver waits for the MPC idle bit to be set as part of
pipe initialization. However, on some systems this occurs before OTG is
enabled, and since the MPC idle bit won't be set until the vupdate
signal occurs (which requires OTG to be enabled), this never happens and
the wait times out. This can add hundreds of milliseconds to the boot
time.

[How]
Do not wait for mpc idle if tg is disabled

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 50820e79d3c4..2d3d870f0bea 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3185,7 +3185,8 @@ void dcn10_wait_for_mpcc_disconnect(
 		if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
 			struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
 
-			res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
+			if (pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg))
+				res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
 			pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
 			hubp->funcs->set_blank(hubp, true);
 		}
-- 
2.32.0

[PATCH 03/20] drm/amd/display: Disabling Z10 on DCN31

[Pavle Kotarac]

From: "AMD\\syerizvi" <syerizvi@amd.com>

[WHY]
Z10 is should not be enabled by default on DCN31.

[HOW]
Using DC debug flags to disable Z10 by default on DCN31.

Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: AMD\syerizvi <syerizvi@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index f27262417abe..6cc580be7c79 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -885,6 +885,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 			.afmt = true,
 		}
 	},
+	.disable_z10 = true,
 	.optimize_edp_link_rate = true,
 	.enable_sw_cntl_psr = true,
 	.apply_vendor_specific_lttpr_wa = true,
-- 
2.32.0

[PATCH 04/20] drm/amd/display: Disallow entering PSR when panel is disconnected

[Pavle Kotarac]

From: Max Erenberg <merenber@amd.com>

[WHY]
The dGPU cannot enter PSR when it is not connected to a panel.

[HOW]
Added a check to dc_link_set_psr_allow_active
which returns early if panel is disconnected.

Reviewed-by: Harry Vanzylldejong <harry.vanzylldejong@amd.com>
Reviewed-by: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
Reviewed-by: Nicholas Choi <Nicholas.Choi@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Max Erenberg <merenber@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 47b67fd1e84c..22f2d88fab99 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3079,6 +3079,11 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active
 	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
 		return false;
 
+	if (allow_active && link->type == dc_connection_none) {
+		// Don't enter PSR if panel is not connected
+		return false;
+	}
+
 	/* Set power optimization flag */
 	if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
 		link->psr_settings.psr_power_opt = *power_opts;
-- 
2.32.0

[PATCH 05/20] drm/amd/display: Disable FEC if DSC not supported for EDP

[Pavle Kotarac]

From: Iswara Nagulendran <inagulen@amd.com>

[WHY]
Screen was seen corrupted for a few ms
when switching both ways. There was also
not enough bandwidth for HDR to be
enabled in HG disabled mode.
This was due to FEC being
enabled although DSC was not supported
or disabled for the EDP.

[HOW]
Check for EDP DSC support in DC caps
or if DSC should be disabled for EDP
before enabling FEC for EDP.

Reviewed-by: Harry Vanzylldejong <USER DID NOT SET AN EMAIL>
Reviewed-by: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
Reviewed-by: Nicholas Choi <Nicholas.Choi@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Iswara Nagulendran <inagulen@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 22f2d88fab99..c1a727ff8b1d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4663,8 +4663,10 @@ bool dc_link_should_enable_fec(const struct dc_link *link)
 			link->local_sink->edid_caps.panel_patch.disable_fec)
 		force_disable = true;
 	else if (link->connector_signal == SIGNAL_TYPE_EDP
-			&& link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
-			 dsc_support.DSC_SUPPORT == false)
+			&& (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
+			 dsc_support.DSC_SUPPORT == false
+				|| link->dc->debug.disable_dsc_edp
+				|| !link->dc->caps.edp_dsc_support))
 		force_disable = true;
 
 	return !force_disable && dc_link_is_fec_supported(link);
-- 
2.32.0

[PATCH 06/20] drm/amd/display: Fix crash on setting VRR with no display connected

[Pavle Kotarac]

From: Harry VanZyllDeJong <hvanzyll@amd.com>

[HOW&WHY]
VRR was getting set at the same time
the timing generator would be null when there was no display
connected. Added null check to the timing generator variable
so it does not get referenced if it is null.

Reviewed-by: Harry Vanzylldejong <harry.vanzylldejong@amd.com>
Reviewed-by: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
Reviewed-by: Nicholas Choi <Nicholas.Choi@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Harry VanZyllDeJong <hvanzyll@amd.com>
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c    | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 2d3d870f0bea..328569ad2bd6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3049,12 +3049,16 @@ void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
 	 * as well.
 	 */
 	for (i = 0; i < num_pipes; i++) {
-		pipe_ctx[i]->stream_res.tg->funcs->set_drr(
-			pipe_ctx[i]->stream_res.tg, &params);
-		if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
-			pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
-					pipe_ctx[i]->stream_res.tg,
-					event_triggers, num_frames);
+		if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) {
+			if (pipe_ctx[i]->stream_res.tg->funcs->set_drr)
+				pipe_ctx[i]->stream_res.tg->funcs->set_drr(
+					pipe_ctx[i]->stream_res.tg, &params);
+			if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
+				if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control)
+					pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
+						pipe_ctx[i]->stream_res.tg,
+						event_triggers, num_frames);
+		}
 	}
 }
 
-- 
2.32.0

[PATCH 07/20] drm/amd/display: ensure PSR force_static flag can always be set

[Pavle Kotarac]

From: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>

[HOW&WHY]
Make sure psr_force_static() can always be called regardless of
psr_allow_active value.

Reviewed-by: Harry Vanzylldejong <USER DID NOT SET AN EMAIL>
Reviewed-by: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
Reviewed-by: Nicholas Choi <Nicholas.Choi@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c1a727ff8b1d..b625b46ae96c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3092,6 +3092,10 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active
 			psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
 	}
 
+	if (psr != NULL && link->psr_settings.psr_feature_enabled &&
+			force_static && psr->funcs->psr_force_static)
+		psr->funcs->psr_force_static(psr, panel_inst);
+
 	/* Enable or Disable PSR */
 	if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
 		link->psr_settings.psr_allow_active = *allow_active;
@@ -3102,8 +3106,6 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active
 #endif
 
 		if (psr != NULL && link->psr_settings.psr_feature_enabled) {
-			if (force_static && psr->funcs->psr_force_static)
-				psr->funcs->psr_force_static(psr, panel_inst);
 			psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
 		} else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
 			link->psr_settings.psr_feature_enabled)
-- 
2.32.0

[PATCH 08/20] drm/amd/display: remove dtbclk_ss compensation for dcn316

[Pavle Kotarac]

From: Charlene Liu <Charlene.Liu@amd.com>

[why]
dcn316's dtbclk is from non_ss clock source.
no compensation required here.

Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 2 +-
 .../gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c    | 4 ++--
 drivers/gpu/drm/amd/display/dc/dc.h                           | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index dfba6138f538..26feefbb8990 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -374,7 +374,7 @@ void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)
 				clk_mgr_dce->dprefclk_ss_percentage =
 						info.spread_spectrum_percentage;
 			}
-			if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)
+			if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss)
 				clk_mgr_dce->dprefclk_ss_percentage = 0;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index 702d00ce7da4..3121dd2d2a91 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -686,8 +686,8 @@ void dcn316_clk_mgr_construct(
 	clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
  	clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
 	dce_clock_read_ss_info(&clk_mgr->base);
-	clk_mgr->base.dccg->ref_dtbclk_khz =
-	dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
+	/*clk_mgr->base.dccg->ref_dtbclk_khz =
+	dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/
 
 	clk_mgr->base.base.bw_params = &dcn316_bw_params;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 70cc21ec643a..e723553f9c5a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -340,6 +340,7 @@ struct dc_config {
 	bool is_asymmetric_memory;
 	bool is_single_rank_dimm;
 	bool use_pipe_ctx_sync_logic;
+	bool ignore_dpref_ss;
 };
 
 enum visual_confirm {
@@ -729,7 +730,6 @@ struct dc_debug_options {
 	bool apply_vendor_specific_lttpr_wa;
 	bool extended_blank_optimization;
 	union aux_wake_wa_options aux_wake_wa;
-	bool ignore_dpref_ss;
 	uint8_t psr_power_use_phy_fsm;
 };
 
-- 
2.32.0

[PATCH 09/20] drm/amd/display: Power down hardware if timer not trigger

[Pavle Kotarac]

From: Paul Hsieh <paul.hsieh@amd.com>

[WHY]
In headless systems, if SetMode/Power down timer
is not called, hardware will not be powered down
causing HW/SW discrepancies. Powering down hardware
on SetPowerState to D3 will ensure SW/HW state is accurate.

[HOW]
1. If PowerDownThread timer is not trigger but OS call
SetPowerState to D3, power down hardware.
2. Update HDMI hang w/a to apply to all TMDS signals on
headless system

Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
---
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 17 +++++++++---
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  | 26 ++++++++++++++++++-
 2 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index f4dee0e48a67..02943ca65807 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -88,11 +88,22 @@ static int rn_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context)
 
 static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
 {
+	int display_count;
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct dc *dc = clk_mgr_base->ctx->dc;
+	struct dc_state *context = dc->current_state;
+
+	if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+
+		display_count = rn_get_active_display_cnt_wa(dc, context);
 
-	rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
-	/* update power state */
-	clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+		/* if we can go lower, go lower */
+		if (display_count == 0) {
+			rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
+			/* update power state */
+			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+		}
+	}
 }
 
 static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 59fdd7f0d609..969b40250434 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -615,13 +615,37 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk
 	}
 }
 
+void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)
+{
+	int display_count;
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct dc *dc = clk_mgr_base->ctx->dc;
+	struct dc_state *context = dc->current_state;
+
+	if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+		display_count = dcn31_get_active_display_cnt_wa(dc, context);
+		/* if we can go lower, go lower */
+		if (display_count == 0) {
+			union display_idle_optimization_u idle_info = { 0 };
+
+			idle_info.idle_info.df_request_disabled = 1;
+			idle_info.idle_info.phy_ref_clk_off = 1;
+			idle_info.idle_info.s0i2_rdy = 1;
+			dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+			/* update power state */
+			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+		}
+	}
+}
+
 static struct clk_mgr_funcs dcn31_funcs = {
 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 	.update_clocks = dcn31_update_clocks,
 	.init_clocks = dcn31_init_clocks,
 	.enable_pme_wa = dcn31_enable_pme_wa,
 	.are_clock_states_equal = dcn31_are_clock_states_equal,
-	.notify_wm_ranges = dcn31_notify_wm_ranges
+	.notify_wm_ranges = dcn31_notify_wm_ranges,
+	.set_low_power_state = dcn31_set_low_power_state
 };
 extern struct clk_mgr_funcs dcn3_fpga_funcs;
 
-- 
2.32.0

[PATCH 10/20] drm/amd/display: Insert pulling smu busy status before sending another request

[Pavle Kotarac]

From: Oliver Logush <oliver.logush@amd.com>

[why]
Make sure smu is not busy before sending another request, this is to
prevent stress failures from MS.

[how]
Check to make sure the SMU fw busy signal is cleared before sending
another request

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Oliver Logush <oliver.logush@amd.com>
---
 .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c    | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 8161a6ae410d..30c6f9cd717f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -94,6 +94,9 @@ static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 {
 	uint32_t result;
 
+	result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
+	ASSERT(result == VBIOSSMC_Result_OK);
+
 	/* First clear response register */
 	REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
 
-- 
2.32.0

[PATCH 11/20] drm/amd/display: Always update DPPCLK_DTO when clock increase

[Pavle Kotarac]

From: Oliver Logush <oliver.logush@amd.com>

[why]
Need to update the update_clock sequence to a fully tested sequence for
dcn30

[how]
Removed the check to see if clock is lowered

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Oliver Logush <oliver.logush@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c | 3 +--
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c     | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
index fbdd0a92d146..451e8d6cd8bd 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
@@ -157,8 +157,7 @@ static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base,
 		} else {
 			if (update_dppclk || update_dispclk)
 				dcn20_update_clocks_update_dentist(clk_mgr, context);
-			if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
-				dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index bc4ddc36fe58..f310b0d25a07 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -176,8 +176,7 @@ static void vg_update_clocks(struct clk_mgr *clk_mgr_base,
 		if (update_dppclk || update_dispclk)
 			dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 		// always update dtos unless clock is lowered and not safe to lower
-		if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
-			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+		dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 	}
 }
 
-- 
2.32.0

[PATCH 12/20] drm/amd/display: Add odm seamless boot support

[Pavle Kotarac]

From: Duncan Ma <Duncan.Ma@amd.com>

[WHY]
Implement changes to transition from Pre-OS odm to
Post-OS odm support. Seamless boot case is also
considered.

[HOW]
Revised validation logic when marking for seamless
boot. Init resources accordingly when Pre-OS has
odm enabled. Reset odm and det size when transitioning
Pre-OS odm to Post-OS non-odm to avoid corruption.
Apply logic to set odm accordingly upon commit.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: "Duncan Ma" <duncan.ma@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 13 +++
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 82 ++++++++++++-------
 drivers/gpu/drm/amd/display/dc/dc.h           |  1 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  1 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 21 +++++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 21 +++++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.h |  2 +
 .../amd/display/dc/inc/hw/timing_generator.h  |  2 +
 8 files changed, 115 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c436db416708..c2fcd67bcc4d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1569,11 +1569,24 @@ bool dc_validate_boot_timing(const struct dc *dc,
 
 	if (dc_is_dp_signal(link->connector_signal)) {
 		unsigned int pix_clk_100hz;
+		uint32_t numOdmPipes = 1;
+		uint32_t id_src[4] = {0};
 
 		dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
 			dc->res_pool->dp_clock_source,
 			tg_inst, &pix_clk_100hz);
 
+		if (tg->funcs->get_optc_source)
+			tg->funcs->get_optc_source(tg,
+						&numOdmPipes, &id_src[0], &id_src[1]);
+
+		if (numOdmPipes == 2)
+			pix_clk_100hz *= 2;
+		if (numOdmPipes == 4)
+			pix_clk_100hz *= 4;
+
+		// Note: In rare cases, HW pixclk may differ from crtc's pixclk
+		// slightly due to rounding issues in 10 kHz units.
 		if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
 			return false;
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f5777a71f2f1..f292303b75a5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2120,6 +2120,8 @@ static int acquire_resource_from_hw_enabled_state(
 {
 	struct dc_link *link = stream->link;
 	unsigned int i, inst, tg_inst = 0;
+	uint32_t numPipes = 1;
+	uint32_t id_src[4] = {0};
 
 	/* Check for enabled DIG to identify enabled display */
 	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
@@ -2148,38 +2150,62 @@ static int acquire_resource_from_hw_enabled_state(
 	if (!res_ctx->pipe_ctx[tg_inst].stream) {
 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
 
-		pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
-		pipe_ctx->plane_res.mi = pool->mis[tg_inst];
-		pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
-		pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
-		pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
-		pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
-		pipe_ctx->stream_res.opp = pool->opps[tg_inst];
-
-		if (pool->dpps[tg_inst]) {
-			pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
-
-			// Read DPP->MPCC->OPP Pipe from HW State
-			if (pool->mpc->funcs->read_mpcc_state) {
-				struct mpcc_state s = {0};
-
-				pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
-
-				if (s.dpp_id < MAX_MPCC)
-					pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
-
-				if (s.bot_mpcc_id < MAX_MPCC)
-					pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
-							&pool->mpc->mpcc_array[s.bot_mpcc_id];
+		id_src[0] = tg_inst;
+
+		if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
+			pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
+					&numPipes, &id_src[0], &id_src[1]);
+
+		for (i = 0; i < numPipes; i++) {
+			//Check if src id invalid
+			if (id_src[i] == 0xf)
+				return -1;
+
+			pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
+			pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
+			pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
+			pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];
+			pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];
+			pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];
+			pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
+
+			if (pool->dpps[id_src[i]]) {
+				pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
+
+				if (pool->mpc->funcs->read_mpcc_state) {
+					struct mpcc_state s = {0};
+					pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
+					if (s.dpp_id < MAX_MPCC)
+						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
+								s.dpp_id;
+					if (s.bot_mpcc_id < MAX_MPCC)
+						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
+								&pool->mpc->mpcc_array[s.bot_mpcc_id];
+					if (s.opp_id < MAX_OPP)
+						pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
+				}
+			}
+			pipe_ctx->pipe_idx = id_src[i];
 
-				if (s.opp_id < MAX_OPP)
-					pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
+			if (id_src[i] >= pool->timing_generator_count) {
+				id_src[i] = pool->timing_generator_count - 1;
+				pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
+				pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
 			}
+
+			pipe_ctx->stream = stream;
 		}
-		pipe_ctx->pipe_idx = tg_inst;
 
-		pipe_ctx->stream = stream;
-		return tg_inst;
+		if (numPipes == 2) {
+			stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1;
+			res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];
+			res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;
+			res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;
+			res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];
+		} else
+			stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled;
+
+		return id_src[0];
 	}
 
 	return -1;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e723553f9c5a..863d90bec61b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -666,6 +666,7 @@ struct dc_debug_options {
 	uint32_t edid_read_retry_times;
 	bool remove_disconnect_edp;
 	unsigned int force_odm_combine; //bit vector based on otg inst
+	unsigned int seamless_boot_odm_combine;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
 	bool disable_z9_mpc;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index c4168c11257c..580420c3eedc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -246,6 +246,7 @@ struct dc_stream_state {
 
 	bool apply_edp_fast_boot_optimization;
 	bool apply_seamless_boot_optimization;
+	uint32_t apply_boot_odm_mode;
 
 	uint32_t stream_id;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 328569ad2bd6..283bc42d2fc7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1259,6 +1259,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 {
 	int i;
 	struct dce_hwseq *hws = dc->hwseq;
+	struct hubbub *hubbub = dc->res_pool->hubbub;
 	bool can_apply_seamless_boot = false;
 
 	for (i = 0; i < context->stream_count; i++) {
@@ -1294,6 +1295,21 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 		}
 	}
 
+	/* Reset det size */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+		struct hubp *hubp = dc->res_pool->hubps[i];
+
+		/* Do not need to reset for seamless boot */
+		if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
+			continue;
+
+		if (hubbub && hubp) {
+			if (hubbub->funcs->program_det_size)
+				hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);
+		}
+	}
+
 	/* num_opp will be equal to number of mpcc */
 	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
@@ -1359,6 +1375,11 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 		pipe_ctx->stream_res.tg = NULL;
 		pipe_ctx->plane_res.hubp = NULL;
 
+		if (tg->funcs->is_tg_enabled(tg)) {
+			if (tg->funcs->init_odm)
+				tg->funcs->init_odm(tg);
+		}
+
 		tg->funcs->tg_init(tg);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
index 10f897b1cb63..c51f7dca94f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -213,6 +213,26 @@ void optc31_set_drr(
 	}
 }
 
+void optc3_init_odm(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+			OPTC_NUM_OF_INPUT_SEGMENT, 0,
+			OPTC_SEG0_SRC_SEL, optc->inst,
+			OPTC_SEG1_SRC_SEL, 0xf,
+			OPTC_SEG2_SRC_SEL, 0xf,
+			OPTC_SEG3_SRC_SEL, 0xf
+			);
+
+	REG_SET(OTG_H_TIMING_CNTL, 0,
+			OTG_H_TIMING_DIV_MODE, 0);
+
+	REG_SET(OPTC_MEMORY_CONFIG, 0,
+			OPTC_MEM_SEL, 0);
+	optc1->opp_count = 1;
+}
+
 static struct timing_generator_funcs dcn31_tg_funcs = {
 		.validate_timing = optc1_validate_timing,
 		.program_timing = optc1_program_timing,
@@ -272,6 +292,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = {
 		.program_manual_trigger = optc2_program_manual_trigger,
 		.setup_manual_trigger = optc2_setup_manual_trigger,
 		.get_hw_timing = optc1_get_hw_timing,
+		.init_odm = optc3_init_odm,
 };
 
 void dcn31_timing_generator_init(struct optc *optc1)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
index a37b16040c1d..9e881f2ce74b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
@@ -258,4 +258,6 @@ void dcn31_timing_generator_init(struct optc *optc1);
 
 void optc31_set_drr(struct timing_generator *optc, const struct drr_params *params);
 
+void optc3_init_odm(struct timing_generator *optc);
+
 #endif /* __DC_OPTC_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 59a704781e34..554d2e33bd7f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -310,6 +310,8 @@ struct timing_generator_funcs {
 			uint32_t slave_pixel_clock_100Hz,
 			uint8_t master_clock_divider,
 			uint8_t slave_clock_divider);
+
+	void (*init_odm)(struct timing_generator *tg);
 };
 
 #endif
-- 
2.32.0

[PATCH 13/20] drm/amd/display: add DCN30 support FEC init

[Pavle Kotarac]

From: Jingwen Zhu <Jingwen.Zhu@amd.com>

[Why]
FEC init used on DCN30.

[How]
Check fec active when HW init.

Co-authored-by: Jingwen Zhu <Jingwen.Zhu@github.amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Jingwen Zhu <Jingwen.Zhu@github.amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index f61ec8763844..782b8db451b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -535,8 +535,12 @@ void dcn30_init_hw(struct dc *dc)
 
 		/* Check for enabled DIG to identify enabled display */
 		if (link->link_enc->funcs->is_dig_enabled &&
-			link->link_enc->funcs->is_dig_enabled(link->link_enc))
+			link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 			link->link_status.link_active = true;
+			if (link->link_enc->funcs->fec_is_active &&
+					link->link_enc->funcs->fec_is_active(link->link_enc))
+				link->fec_state = dc_link_fec_enabled;
+		}
 	}
 
 	/* Power gate DSCs */
-- 
2.32.0

[PATCH 14/20] drm/amd/display: Fix inconsistent timestamp type

[Pavle Kotarac]

From: Angus Wang <Angus.Wang@amd.com>

[WHY]
An unsigned int timestamp variable is assigned with an unsigned
long long value. Also, the assignment directly converts the
tick value to us without using built-in get elapsed time function.

[HOW]
Cast the assigned value correctly and also use built-in function
to get the timestamp in the unit we want.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Angus Wang <Angus.Wang@amd.com>
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 0130f1879116..c1d540f017a8 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1230,6 +1230,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 {
 	struct core_freesync *core_freesync = NULL;
 	unsigned int cur_timestamp_in_us;
+	unsigned long long cur_tick;
 
 	if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
 		return;
@@ -1239,7 +1240,9 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 	if (in_out_vrr->supported == false)
 		return;
 
-	cur_timestamp_in_us = dm_get_timestamp(core_freesync->dc->ctx)/10;
+	cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
+	cur_timestamp_in_us = (unsigned int)
+			(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0)/1000);
 
 	in_out_vrr->flip_interval.vsyncs_between_flip++;
 	in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
-- 
2.32.0

[PATCH 15/20] drm/amd/display: Add dtb clock to dc_clocks

[Pavle Kotarac]

From: Dillon Varone <dillon.varone@amd.com>

Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 863d90bec61b..544d58260269 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -417,6 +417,7 @@ struct dc_clocks {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	enum dcn_zstate_support_state zstate_support;
 	bool dtbclk_en;
+	int dtbclk_khz;
 #endif
 	enum dcn_pwr_state pwr_state;
 	/*
-- 
2.32.0

[PATCH 16/20] drm/amd/display: expose skip_detection_link_training to debugfs

[Pavle Kotarac]

From: hersen wu <hersenxs.wu@amd.com>

[Why] within dc link detecion, dp link training will be
executed for external sst dp. for debug purpose, we may
need skip dp link training.

[How] expose dc debug option to skip_detection_link_training
to debugfs

Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index d881e695d97c..5193afb067d3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -3495,6 +3495,40 @@ DEFINE_SHOW_ATTRIBUTE(mst_topo);
 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
 			 visual_confirm_set, "%llu\n");
 
+
+/*
+ * Sets the DC skip_detection_link_training debug option from the given string.
+ * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
+ */
+static int skip_detection_link_training_set(void *data, u64 val)
+{
+	struct amdgpu_device *adev = data;
+
+	if (val == 0)
+		adev->dm.dc->debug.skip_detection_link_training = false;
+	else
+		adev->dm.dc->debug.skip_detection_link_training = true;
+
+	return 0;
+}
+
+/*
+ * Reads the DC skip_detection_link_training debug option value into the given buffer.
+ * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
+ */
+static int skip_detection_link_training_get(void *data, u64 *val)
+{
+	struct amdgpu_device *adev = data;
+
+	*val = adev->dm.dc->debug.skip_detection_link_training;
+
+	return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
+			 skip_detection_link_training_get,
+			 skip_detection_link_training_set, "%llu\n");
+
 /*
  * Dumps the DCC_EN bit for each pipe.
  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
@@ -3588,6 +3622,9 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
 	debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
 				   &visual_confirm_fops);
 
+	debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
+				   &skip_detection_link_training_fops);
+
 	debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
 				   adev, &dmub_tracebuffer_fops);
 
-- 
2.32.0

[PATCH 17/20] drm/amd/display: Fix issue breaking 32bit Linux build

[Pavle Kotarac]

From: Hayden Goodfellow <Hayden.Goodfellow@amd.com>

[Why]
Currently, the 32bit linux build is failing due to an issue with using the
built-in / operator with a 64bit dividend. Doing so generates code which
calls __udivdi3() in libgcc. However, libgcc is not linked with the kernel
at this point in the build, hence this causes the 32bit build to fail to
compile.

[How]
Change the / operator to div_u64 instead.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Hayden Goodfellow <Hayden.Goodfellow@amd.com>
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index c1d540f017a8..03fa63d56fa6 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1242,7 +1242,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 
 	cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
 	cur_timestamp_in_us = (unsigned int)
-			(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0)/1000);
+			div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
 
 	in_out_vrr->flip_interval.vsyncs_between_flip++;
 	in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
-- 
2.32.0

[PATCH 18/20] drm/amd/display: Select correct DTO source

[Pavle Kotarac]

From: Dillon Varone <dillon.varone@amd.com>

[WHY&HOW]
Change criteria for setting DTO source value, and always set it regardless of
the signal type.

Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index c36f8e829344..760653e2b607 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -985,7 +985,7 @@ static bool dcn31_program_pix_clk(
 	struct bp_pixel_clock_parameters bp_pc_params = {0};
 	enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
 	// For these signal types Driver to program DP_DTO without calling VBIOS Command table
-	if (dc_is_dp_signal(pix_clk_params->signal_type)) {
+	if (dc_is_dp_signal(pix_clk_params->signal_type) || dc_is_virtual_signal(pix_clk_params->signal_type)) {
 		if (e) {
 			/* Set DTO values: phase = target clock, modulo = reference clock*/
 			REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
-- 
2.32.0

[PATCH 19/20] drm/amd/display: 3.2.181

[Pavle Kotarac]

From: Aric Cyr <aric.cyr@amd.com>

Title: DC Patches Apri 6, 2022

This DC patchset brings improvements in multiple areas. In summary, we highlight:

*Disabling Z10 on DCN31
*Fix issue breaking 32bit Linux build
*Fix inconsistent timestamp type
*Add DCN30 support FEC init
*Fix crash on setting VRR with no display connected
*Disable FEC if DSC not supported for EDP
*Add odm seamless boot support
*Select correct DTO source
*Power down hardware if timer not trigger

Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 544d58260269..2f0c436dae4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.180"
+#define DC_VER "3.2.181"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.32.0

[PATCH 20/20] drm/amd/display: implement shared PSR-SU sink validation helper

[Pavle Kotarac]

From: David Zhang <dingchen.zhang@amd.com>

[why]
creating a generic helper for AMD specific PSR-SU sink validation.
Moving the function to the power module to reference it across all
OS.

[how]
- drop PSRSU specific sink validation helper and move to power
  module by reading PSR version and other PSR caps
- call the new helper from linux DM (amdgpu_dm_psr)

Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  9 ++++-
 .../amd/display/modules/power/power_helpers.c | 38 +++++++++++++++++++
 .../amd/display/modules/power/power_helpers.h |  1 +
 3 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 0c923a90615c..13b1751e69bf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -27,6 +27,7 @@
 #include "dc.h"
 #include "dm_helpers.h"
 #include "amdgpu_dm.h"
+#include "modules/power/power_helpers.h"
 
 #ifdef CONFIG_DRM_AMD_DC_DCN
 static bool link_supports_psrsu(struct dc_link *link)
@@ -39,6 +40,9 @@ static bool link_supports_psrsu(struct dc_link *link)
 	if (dc->ctx->dce_version < DCN_VERSION_3_1)
 		return false;
 
+	if (!is_psr_su_specific_panel(link))
+		return false;
+
 	if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
 	    !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
 		return false;
@@ -79,7 +83,10 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link)
 		link->psr_settings.psr_feature_enabled = true;
 	}
 
-	DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
+	DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d\n",
+		link->psr_settings.psr_feature_enabled,
+		link->psr_settings.psr_version,
+		link->dpcd_caps.psr_info.psr_version);
 
 }
 
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 2b00f334e93d..97928d4c3b9a 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -784,3 +784,41 @@ bool dmcu_load_iram(struct dmcu *dmcu,
 	return result;
 }
 
+/*
+ * is_psr_su_specific_panel() - check if sink is AMD vendor-specific PSR-SU
+ * supported eDP device.
+ *
+ * @link: dc link pointer
+ *
+ * Return: true if AMDGPU vendor specific PSR-SU eDP panel
+ */
+bool is_psr_su_specific_panel(struct dc_link *link)
+{
+	if (link->dpcd_caps.edp_rev >= DP_EDP_14) {
+		if (link->dpcd_caps.psr_info.psr_version >= DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
+			return true;
+		/*
+		 * Some panels will report PSR capabilities over additional DPCD bits.
+		 * Such panels are approved despite reporting only PSR v3, as long as
+		 * the additional bits are reported.
+		 */
+		if (link->dpcd_caps.psr_info.psr_version < DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)
+			return false;
+
+		if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) {
+			/*
+			 * FIXME:
+			 * This is the temporary workaround to disable PSRSU when system turned on
+			 * DSC function on the sepcific sink. Once the PSRSU + DSC is fixed, this
+			 * condition should be removed.
+			 */
+			if (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)
+				return false;
+
+			if (link->dpcd_caps.psr_info.force_psrsu_cap == 0x1)
+				return true;
+		}
+	}
+
+	return false;
+}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
index 2a9f8e2d8080..1a634d8c78c5 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -52,4 +52,5 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
 		struct dmcu_iram_parameters params,
 		unsigned int inst);
 
+bool is_psr_su_specific_panel(struct dc_link *link);
 #endif /* MODULES_POWER_POWER_HELPERS_H_ */
-- 
2.32.0

Re: [PATCH 01/20] drm/amd/display: undo clearing of z10 related function pointers

[Paul Menzel]

Dear Eric, dear Pavle,


Thank you for the patch.

Am 08.04.22 um 19:18 schrieb Pavle Kotarac:
> From: Eric Yang <Eric.Yang2@amd.com>
> 
> [Why]
> Z10 and S0i3 have some shared path. Previous code clean up ,

1.  cleanup
2.  Remove the space before the comma, or remove the unneeded comma.

> incorrectly removed these pointers, which breaks s0i3 restore

Please add a dot/period at the end of sentences.

How does tho breakage manifest exactly?

Maybe mention, that it only happened with `dc->debug.disable_z10`.

> 
> [How]
> Do not clear the function pointers based on Z10 disable.
> 

What commit introduced the regression? Please add a Fixes tag.

> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
> Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 5 -----
>   1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
> index d7559e5a99ce..e708f07fe75a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
> @@ -153,9 +153,4 @@ void dcn31_hw_sequencer_construct(struct dc *dc)
>   		dc->hwss.init_hw = dcn20_fpga_init_hw;
>   		dc->hwseq->funcs.init_pipes = NULL;
>   	}
> -	if (dc->debug.disable_z10) {
> -		/*hw not support z10 or sw disable it*/
> -		dc->hwss.z10_restore = NULL;
> -		dc->hwss.z10_save_init = NULL;
> -	}
>   }


Kind regards,

Paul

Re: [PATCH 02/20] drm/amd/display: do not wait for mpc idle if tg is disabled

[Paul Menzel]

Dear Pavle,


Thank you for the patch.

Am 08.04.22 um 19:18 schrieb Pavle Kotarac:
> From: Josip Pavic <Josip.Pavic@amd.com>
> 
> [Why]
> When booting, the driver waits for the MPC idle bit to be set as part of
> pipe initialization. However, on some systems this occurs before OTG is
> enabled, and since the MPC idle bit won't be set until the vupdate
> signal occurs (which requires OTG to be enabled), this never happens and
> the wait times out. This can add hundreds of milliseconds to the boot
> time.

Please list one specific system, where OTG is enabled later.

> 
> [How]
> Do not wait for mpc idle if tg is disabled

Please add a dot/period at the end of sentences.

> Reviewed-by: Jun Lei <Jun.Lei@amd.com>
> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 50820e79d3c4..2d3d870f0bea 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -3185,7 +3185,8 @@ void dcn10_wait_for_mpcc_disconnect(
>   		if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
>   			struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
>   
> -			res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
> +			if (pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg))
> +				res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
>   			pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
>   			hubp->funcs->set_blank(hubp, true);
>   		}


Kind regards,

Paul

Re: [PATCH 03/20] drm/amd/display: Disabling Z10 on DCN31

[Paul Menzel]

Dear Pavle, dear syerizvi,


Thank you for the patch.

Am 08.04.22 um 19:18 schrieb Pavle Kotarac:
> From: "AMD\\syerizvi" <syerizvi@amd.com>

Please correct the author name.

Imperative mood should be used in the commit message summary: Disable Z10 ….

> 
> [WHY]
> Z10 is should not be enabled by default on DCN31.

According to what source?

> 
> [HOW]
> Using DC debug flags to disable Z10 by default on DCN31.

s/Using/Use/

Why is that grouped under debug flags? Does not seem related.

> 
> Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
> Signed-off-by: AMD\syerizvi <syerizvi@amd.com>

Please fix the name.

> ---
>   drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> index f27262417abe..6cc580be7c79 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> @@ -885,6 +885,7 @@ static const struct dc_debug_options debug_defaults_drv = {
>   			.afmt = true,
>   		}
>   	},
> +	.disable_z10 = true,
>   	.optimize_edp_link_rate = true,
>   	.enable_sw_cntl_psr = true,
>   	.apply_vendor_specific_lttpr_wa = true,


Kind regards,

Paul

Re: [PATCH 12/20] drm/amd/display: Add odm seamless boot support

[Paul Menzel]

Dear Pavle, dear Duncan,


Thank you for the patch.

Am 08.04.22 um 19:19 schrieb Pavle Kotarac:
> From: Duncan Ma <Duncan.Ma@amd.com>
> 
> [WHY]
> Implement changes to transition from Pre-OS odm to

What is odm/ODM? Original Device Manufacturer?

> Post-OS odm support. Seamless boot case is also
> considered.

Please answer the question Why? better.

What is Post-OS odm support? Why are change to the transition needed?

What is seamless boot? Please add references.

> 
> [HOW]
> Revised validation logic when marking for seamless
> boot.

How is it revised exactly?

> Init resources accordingly when Pre-OS has
> odm enabled. Reset odm and det size when transitioning
> Pre-OS odm to Post-OS non-odm to avoid corruption.
> Apply logic to set odm accordingly upon commit.

I looked through the diff, but would love a more elaborate description 
of the implementation.

How was and can this tested?

Please reflow for 75 characters per line as textwidth.

> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
> Signed-off-by: "Duncan Ma" <duncan.ma@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/core/dc.c      | 13 +++
>   .../gpu/drm/amd/display/dc/core/dc_resource.c | 82 ++++++++++++-------
>   drivers/gpu/drm/amd/display/dc/dc.h           |  1 +
>   drivers/gpu/drm/amd/display/dc/dc_stream.h    |  1 +
>   .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 21 +++++
>   .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 21 +++++
>   .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.h |  2 +
>   .../amd/display/dc/inc/hw/timing_generator.h  |  2 +
>   8 files changed, 115 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index c436db416708..c2fcd67bcc4d 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -1569,11 +1569,24 @@ bool dc_validate_boot_timing(const struct dc *dc,
>   
>   	if (dc_is_dp_signal(link->connector_signal)) {
>   		unsigned int pix_clk_100hz;
> +		uint32_t numOdmPipes = 1;

Maybe add a comment, that the type is due to `get_optc_source` signature.

Why initialize it? get_optc_source seems to always assign a value to the 
passed variable.

Why CamelCase?

> +		uint32_t id_src[4] = {0};
>   
>   		dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
>   			dc->res_pool->dp_clock_source,
>   			tg_inst, &pix_clk_100hz);
>   
> +		if (tg->funcs->get_optc_source)
> +			tg->funcs->get_optc_source(tg,
> +						&numOdmPipes, &id_src[0], &id_src[1]);
> +
> +		if (numOdmPipes == 2)
> +			pix_clk_100hz *= 2;
> +		if (numOdmPipes == 4)
> +			pix_clk_100hz *= 4;
> +
> +		// Note: In rare cases, HW pixclk may differ from crtc's pixclk
> +		// slightly due to rounding issues in 10 kHz units.

The comment could be added in a separate patch, and also the values be 
logged if they are different.

>   		if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
>   			return false;
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index f5777a71f2f1..f292303b75a5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -2120,6 +2120,8 @@ static int acquire_resource_from_hw_enabled_state(
>   {
>   	struct dc_link *link = stream->link;
>   	unsigned int i, inst, tg_inst = 0;
> +	uint32_t numPipes = 1;

Why CamelCase?

> +	uint32_t id_src[4] = {0};
>   
>   	/* Check for enabled DIG to identify enabled display */
>   	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
> @@ -2148,38 +2150,62 @@ static int acquire_resource_from_hw_enabled_state(
>   	if (!res_ctx->pipe_ctx[tg_inst].stream) {
>   		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
>   
> -		pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
> -		pipe_ctx->plane_res.mi = pool->mis[tg_inst];
> -		pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
> -		pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
> -		pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
> -		pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
> -		pipe_ctx->stream_res.opp = pool->opps[tg_inst];
> -
> -		if (pool->dpps[tg_inst]) {
> -			pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
> -
> -			// Read DPP->MPCC->OPP Pipe from HW State
> -			if (pool->mpc->funcs->read_mpcc_state) {
> -				struct mpcc_state s = {0};
> -
> -				pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
> -
> -				if (s.dpp_id < MAX_MPCC)
> -					pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
> -
> -				if (s.bot_mpcc_id < MAX_MPCC)
> -					pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
> -							&pool->mpc->mpcc_array[s.bot_mpcc_id];
> +		id_src[0] = tg_inst;
> +
> +		if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
> +			pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
> +					&numPipes, &id_src[0], &id_src[1]);
> +
> +		for (i = 0; i < numPipes; i++) {
> +			//Check if src id invalid

Missing space.

> +			if (id_src[i] == 0xf)
> +				return -1;
> +
> +			pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
> +			pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
> +			pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
> +			pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];
> +			pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];
> +			pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];
> +			pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
> +
> +			if (pool->dpps[id_src[i]]) {
> +				pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
> +
> +				if (pool->mpc->funcs->read_mpcc_state) {
> +					struct mpcc_state s = {0};
> +					pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
> +					if (s.dpp_id < MAX_MPCC)
> +						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
> +								s.dpp_id;
> +					if (s.bot_mpcc_id < MAX_MPCC)
> +						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
> +								&pool->mpc->mpcc_array[s.bot_mpcc_id];
> +					if (s.opp_id < MAX_OPP)
> +						pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
> +				}
> +			}
> +			pipe_ctx->pipe_idx = id_src[i];
>   
> -				if (s.opp_id < MAX_OPP)
> -					pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
> +			if (id_src[i] >= pool->timing_generator_count) {
> +				id_src[i] = pool->timing_generator_count - 1;
> +				pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
> +				pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
>   			}
> +
> +			pipe_ctx->stream = stream;
>   		}
> -		pipe_ctx->pipe_idx = tg_inst;
>   
> -		pipe_ctx->stream = stream;
> -		return tg_inst;
> +		if (numPipes == 2) {
> +			stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1;
> +			res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];
> +			res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;
> +			res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;
> +			res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];
> +		} else
> +			stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled;

Missing curly braces. Didn’t `scripts/checkpatch.pl` find that?

> +
> +		return id_src[0];
>   	}
>   
>   	return -1;
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
> index e723553f9c5a..863d90bec61b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -666,6 +666,7 @@ struct dc_debug_options {
>   	uint32_t edid_read_retry_times;
>   	bool remove_disconnect_edp;
>   	unsigned int force_odm_combine; //bit vector based on otg inst
> +	unsigned int seamless_boot_odm_combine;

Please add a comment, what this does. Why `combine`?

>   #if defined(CONFIG_DRM_AMD_DC_DCN)
>   	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
>   	bool disable_z9_mpc;
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
> index c4168c11257c..580420c3eedc 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
> @@ -246,6 +246,7 @@ struct dc_stream_state {
>   
>   	bool apply_edp_fast_boot_optimization;
>   	bool apply_seamless_boot_optimization;
> +	uint32_t apply_boot_odm_mode;

The name sounds like a boolean?

>   
>   	uint32_t stream_id;
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 328569ad2bd6..283bc42d2fc7 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -1259,6 +1259,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
>   {
>   	int i;
>   	struct dce_hwseq *hws = dc->hwseq;
> +	struct hubbub *hubbub = dc->res_pool->hubbub;
>   	bool can_apply_seamless_boot = false;
>   
>   	for (i = 0; i < context->stream_count; i++) {
> @@ -1294,6 +1295,21 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
>   		}
>   	}
>   
> +	/* Reset det size */
> +	for (i = 0; i < dc->res_pool->pipe_count; i++) {
> +		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
> +		struct hubp *hubp = dc->res_pool->hubps[i];
> +
> +		/* Do not need to reset for seamless boot */

Comment is redundand to the code. Either remove, or add datasheet 
section or something different as a comment.

> +		if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
> +			continue;
> +
> +		if (hubbub && hubp) {
> +			if (hubbub->funcs->program_det_size)
> +				hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);
> +		}
> +	}
> +
>   	/* num_opp will be equal to number of mpcc */
>   	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
>   		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
> @@ -1359,6 +1375,11 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
>   		pipe_ctx->stream_res.tg = NULL;
>   		pipe_ctx->plane_res.hubp = NULL;
>   
> +		if (tg->funcs->is_tg_enabled(tg)) {
> +			if (tg->funcs->init_odm)
> +				tg->funcs->init_odm(tg);
> +		}
> +
>   		tg->funcs->tg_init(tg);
>   	}
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
> index 10f897b1cb63..c51f7dca94f8 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
> @@ -213,6 +213,26 @@ void optc31_set_drr(
>   	}
>   }
>   
> +void optc3_init_odm(struct timing_generator *optc)
> +{
> +	struct optc *optc1 = DCN10TG_FROM_TG(optc);
> +
> +	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
> +			OPTC_NUM_OF_INPUT_SEGMENT, 0,
> +			OPTC_SEG0_SRC_SEL, optc->inst,
> +			OPTC_SEG1_SRC_SEL, 0xf,
> +			OPTC_SEG2_SRC_SEL, 0xf,
> +			OPTC_SEG3_SRC_SEL, 0xf
> +			);
> +
> +	REG_SET(OTG_H_TIMING_CNTL, 0,
> +			OTG_H_TIMING_DIV_MODE, 0);
> +
> +	REG_SET(OPTC_MEMORY_CONFIG, 0,
> +			OPTC_MEM_SEL, 0);
> +	optc1->opp_count = 1;
> +}
> +
>   static struct timing_generator_funcs dcn31_tg_funcs = {
>   		.validate_timing = optc1_validate_timing,
>   		.program_timing = optc1_program_timing,
> @@ -272,6 +292,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = {
>   		.program_manual_trigger = optc2_program_manual_trigger,
>   		.setup_manual_trigger = optc2_setup_manual_trigger,
>   		.get_hw_timing = optc1_get_hw_timing,
> +		.init_odm = optc3_init_odm,
>   };
>   
>   void dcn31_timing_generator_init(struct optc *optc1)
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
> index a37b16040c1d..9e881f2ce74b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
> @@ -258,4 +258,6 @@ void dcn31_timing_generator_init(struct optc *optc1);
>   
>   void optc31_set_drr(struct timing_generator *optc, const struct drr_params *params);
>   
> +void optc3_init_odm(struct timing_generator *optc);
> +
>   #endif /* __DC_OPTC_DCN31_H__ */
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> index 59a704781e34..554d2e33bd7f 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> @@ -310,6 +310,8 @@ struct timing_generator_funcs {
>   			uint32_t slave_pixel_clock_100Hz,
>   			uint8_t master_clock_divider,
>   			uint8_t slave_clock_divider);
> +
> +	void (*init_odm)(struct timing_generator *tg);
>   };
>   
>   #endif

Re: [PATCH 04/20] drm/amd/display: Disallow entering PSR when panel is disconnected

[Paul Menzel]

Dear Pavle, dear Max,


Am 08.04.22 um 19:18 schrieb Pavle Kotarac:
> From: Max Erenberg <merenber@amd.com>
> 
> [WHY]
> The dGPU cannot enter PSR when it is not connected to a panel.

Maybe spell out Panel Self Refresh once.

> [HOW]
> Added a check to dc_link_set_psr_allow_active

s/Added/Add/

> which returns early if panel is disconnected.

Please reflow for 57 characters per line.

> 
> Reviewed-by: Harry Vanzylldejong <harry.vanzylldejong@amd.com>
> Reviewed-by: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
> Reviewed-by: Nicholas Choi <Nicholas.Choi@amd.com>
> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
> Signed-off-by: Max Erenberg <merenber@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index 47b67fd1e84c..22f2d88fab99 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -3079,6 +3079,11 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active
>   	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
>   		return false;
>   
> +	if (allow_active && link->type == dc_connection_none) {

Why does `allow_active` need to be checked?

> +		// Don't enter PSR if panel is not connected
> +		return false;
> +	}
> +
>   	/* Set power optimization flag */
>   	if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
>   		link->psr_settings.psr_power_opt = *power_opts;


Kind regards,

Paul

RE: DC Patches Apri 6, 2022

[Wheeler, Daniel]

[AMD Official Use Only]

Hi all,
 
This week this patchset was tested on the following systems:
 
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
Sapphire Pulse RX5700XT with the following display types:
4k 60hz  (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Reference AMD RX6800 with the following display types:
4k 60hz  (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz and DSC via USB-C to DP DSC Hub with 3x 4k 60hz.
 
Tested on Ubuntu 20.04.3 with Kernel Version 5.16
 
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
 
 
Thank you,
 
Dan Wheeler
Technologist  |  AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook |  Twitter |  amd.com  

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Pavle Kotarac
Sent: April 8, 2022 1:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
Subject: DC Patches Apri 6, 2022

This DC patchset brings improvements in multiple areas. In summary, we highlight:
    
    *Disabling Z10 on DCN31
    *Fix issue breaking 32bit Linux build
    *Fix inconsistent timestamp type
    *Add DCN30 support FEC init
    *Fix crash on setting VRR with no display connected
    *Disable FEC if DSC not supported for EDP
    *Add odm seamless boot support
    *Select correct DTO source
    *Power down hardware if timer not trigger


AMD\syerizvi (1):
  drm/amd/display: Disabling Z10 on DCN31

Angus Wang (1):
  drm/amd/display: Fix inconsistent timestamp type

Aric Cyr (1):
  drm/amd/display: 3.2.181

Charlene Liu (1):
  drm/amd/display: remove dtbclk_ss compensation for dcn316

David Zhang (1):
  drm/amd/display: implement shared PSR-SU sink validation helper

Dillon Varone (2):
  drm/amd/display: Add dtb clock to dc_clocks
  drm/amd/display: Select correct DTO source

Duncan Ma (1):
  drm/amd/display: Add odm seamless boot support

Eric Yang (1):
  drm/amd/display: undo clearing of z10 related function pointers

Evgenii Krasnikov (1):
  drm/amd/display: ensure PSR force_static flag can always be set

Harry VanZyllDeJong (1):
  drm/amd/display: Fix crash on setting VRR with no display connected

Hayden Goodfellow (1):
  drm/amd/display: Fix issue breaking 32bit Linux build

Iswara Nagulendran (1):
  drm/amd/display: Disable FEC if DSC not supported for EDP

Jingwen Zhu (1):
  drm/amd/display: add DCN30 support FEC init

Josip Pavic (1):
  drm/amd/display: do not wait for mpc idle if tg is disabled

Max Erenberg (1):
  drm/amd/display: Disallow entering PSR when panel is disconnected

Oliver Logush (2):
  drm/amd/display: Insert pulling smu busy status before sending another
    request
  drm/amd/display: Always update DPPCLK_DTO when clock increase

Paul Hsieh (1):
  drm/amd/display: Power down hardware if timer not trigger

hersen wu (1):
  drm/amd/display: expose skip_detection_link_training to debugfs

 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 37 +++++++++  .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  9 +-
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   |  2 +-
 .../dc/clk_mgr/dcn201/dcn201_clk_mgr.c        |  3 +-
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 17 +++-
 .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   |  3 +
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c    |  3 +-
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  | 26 +++++-
 .../dc/clk_mgr/dcn316/dcn316_clk_mgr.c        |  4 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 13 +++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17 +++-  .../gpu/drm/amd/display/dc/core/dc_resource.c | 82 ++++++++++++-------
 drivers/gpu/drm/amd/display/dc/dc.h           |  6 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  1 +
 .../drm/amd/display/dc/dce/dce_clock_source.c |  2 +-  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 40 +++++++--
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    |  6 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_init.c |  5 --  .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 21 +++++  .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.h |  2 +  .../drm/amd/display/dc/dcn31/dcn31_resource.c |  1 +  .../amd/display/dc/inc/hw/timing_generator.h  |  2 +
 .../amd/display/modules/freesync/freesync.c   |  5 +-
 .../amd/display/modules/power/power_helpers.c | 38 +++++++++  .../amd/display/modules/power/power_helpers.h |  1 +
 25 files changed, 285 insertions(+), 61 deletions(-)

--
2.32.0

Re: [PATCH 10/20] drm/amd/display: Insert pulling smu busy status before sending another request

[Mike Lothian]

Hi

I'm seeing the following stack trace, I'm guessing due to the assert:

[    3.516409] ------------[ cut here ]------------
[    3.516412] WARNING: CPU: 1 PID: 1 at
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c:98
rn_vbios_smu_send_msg_with_param+0x3e/0xe0
[    3.516422] Modules linked in:
[    3.516425] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.19.0-rc4-tip+ #3199
[    3.516428] Hardware name: ASUSTeK COMPUTER INC. ROG Strix
G513QY_G513QY/G513QY, BIOS G513QY.318 03/29/2022
[    3.516432] RIP: 0010:rn_vbios_smu_send_msg_with_param+0x3e/0xe0
[    3.516437] Code: f6 48 89 fb 48 8b 3b be 9b 62 01 00 48 c7 c2 02
bd 06 83 e8 44 c6 f0 ff 85 c0 75 12 bf c6 a7 00 00 e8 f6 9a b1 ff ff
c5 75 da <0f> 0b eb 05 83 f8 01 75 f7 48 8b 3b be 9b 62 01 00 48 c7 c1
3
c 86
[    3.516442] RSP: 0018:ffff88810026f628 EFLAGS: 00010202
[    3.516445] RAX: 00000000000000fe RBX: ffff8881058a3200 RCX: 0000000000000000
[    3.516447] RDX: 0000000000000000 RSI: ffff888105adbb80 RDI: ffff888104f80000
[    3.516450] RBP: 00000000fffcf2bf R08: ffff888110ca6800 R09: 7fc9117fffffffff
[    3.516452] R10: 0000000000000000 R11: ffffffff819bca10 R12: ffff888110cd0000
[    3.516454] R13: ffff888100cc2300 R14: 000000000000000d R15: 0000000000000001
[    3.516457] FS:  0000000000000000(0000) GS:ffff888fde440000(0000)
knlGS:0000000000000000
[    3.516460] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[    3.516462] CR2: 0000000000000000 CR3: 00000000b360c000 CR4: 0000000000350ee0
[    3.516465] Call Trace:
[    3.516468]  <TASK>
[    3.516470]  ? rn_clk_mgr_construct+0x744/0x760
[    3.516475]  ? dc_clk_mgr_create+0x1f0/0x4f0
[    3.516478]  ? dc_create+0x43a/0x5c0
[    3.516481]  ? dm_hw_init+0x29a/0x2380
[    3.516485]  ? vprintk_emit+0x106/0x230
[    3.516488]  ? asm_sysvec_apic_timer_interrupt+0x1f/0x30
[    3.516492]  ? dev_vprintk_emit+0x152/0x179
[    3.516496]  ? smu_hw_init+0x255/0x290
[    3.516500]  ? amdgpu_device_ip_init+0x32a/0x4a0
[    3.516504]  ? amdgpu_device_init+0x1622/0x1bb0
[    3.516507]  ? pci_bus_read_config_word+0x35/0x50
[    3.516512]  ? amdgpu_driver_load_kms+0x14/0x150
[    3.516515]  ? amdgpu_pci_probe+0x1c0/0x3d0
[    3.516518]  ? pci_device_probe+0xd3/0x170
[    3.516520]  ? really_probe+0x13e/0x320
[    3.516523]  ? __driver_probe_device+0x91/0xd0
[    3.516525]  ? driver_probe_device+0x1a/0x160
[    3.516527]  ? __driver_attach+0xe6/0x1b0
[    3.516530]  ? bus_add_driver+0x16e/0x270
[    3.516533]  ? driver_register+0x85/0x120
[    3.516535]  ?
__initstub__kmod_gpu_sched__180_178_drm_sched_fence_slab_init6+0x3f/0x3f
[    3.516540]  ? do_one_initcall+0x100/0x290
[    3.516545]  ? do_initcall_level+0x8a/0xe8
[    3.516549]  ? do_initcalls+0x44/0x6b
[    3.516551]  ? kernel_init_freeable+0xc7/0x10d
[    3.516554]  ? rest_init+0xc0/0xc0
[    3.516558]  ? kernel_init+0x15/0x140
[    3.516561]  ? ret_from_fork+0x22/0x30
[    3.516564]  </TASK>
[    3.516565] ---[ end trace 0000000000000000 ]---

On Fri, 8 Apr 2022 at 18:27, Pavle Kotarac <Pavle.Kotarac@amd.com> wrote:
>
> From: Oliver Logush <oliver.logush@amd.com>
>
> [why]
> Make sure smu is not busy before sending another request, this is to
> prevent stress failures from MS.
>
> [how]
> Check to make sure the SMU fw busy signal is cleared before sending
> another request
>
> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
> Signed-off-by: Oliver Logush <oliver.logush@amd.com>
> ---
>  .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c    | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
> index 8161a6ae410d..30c6f9cd717f 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
> @@ -94,6 +94,9 @@ static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
>  {
>         uint32_t result;
>
> +       result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
> +       ASSERT(result == VBIOSSMC_Result_OK);
> +
>         /* First clear response register */
>         REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
>
> --
> 2.32.0
>