* [PATCH 00/13] DC Patches April 20 2022
@ 2022-04-22 16:44 Tom Chung
2022-04-22 16:44 ` [PATCH 01/13] drm/amd/display: Insert smu busy status before sending another request Tom Chung
` (13 more replies)
0 siblings, 14 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Tom Chung, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
This version brings along following fixes:
- Keep tracking of DSC packed PPS for future use
- Maintain current link settings in link loss interrupt
- Remove DDC write and read size check
- Read PSR-SU cap DPCD for specific panel
- Don't pass HostVM by default on DCN3.1
- Reset cached PSR parameters after hibernate
- Add audio readback registers
- Update dcn315 clk table read
- Fix HDCP QUERY Error for eDP and Tiled
- Insert smu busy status before sending another request
Aric Cyr (2):
drm/amd/display: 3.2.182
drm/amd/display: 3.2.183
David Zhang (1):
drm/amd/display: read PSR-SU cap DPCD for specific panel
Dillon Varone (1):
drm/amd/display: Remove unused integer
Dmytro Laktyushkin (1):
drm/amd/display: update dcn315 clk table read
Evgenii Krasnikov (1):
drm/amd/display: Reset cached PSR parameters after hibernate
Gary Li (1):
drm/amd/display: Maintain current link settings in link loss interrupt
Ilya (2):
drm/amd/display: Add Audio readback registers
drm/amd/display: Keep track of DSC packed PPS
Leo (Hanghong) Ma (1):
drm/amd/display: Remove ddc write and read size checking
Michael Strauss (1):
drm/amd/display: Don't pass HostVM by default on DCN3.1
Mustapha Ghaddar (1):
drm/amd/display: Fix HDCP QUERY Error for eDP and Tiled
Oliver Logush (1):
drm/amd/display: Insert smu busy status before sending another request
.../display/dc/clk_mgr/dcn301/dcn301_smu.c | 2 +
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 114 +++++++++-----
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 +-
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 6 -
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 15 ++
drivers/gpu/drm/amd/display/dc/dc.h | 10 +-
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 +-
.../display/dc/dcn10/dcn10_stream_encoder.c | 1 +
.../display/dc/dcn10/dcn10_stream_encoder.h | 8 +
.../dc/dcn30/dcn30_dio_stream_encoder.h | 4 +
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 9 +-
.../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 145 ++++--------------
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 +
.../amd/display/include/ddc_service_types.h | 2 +
14 files changed, 172 insertions(+), 162 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 01/13] drm/amd/display: Insert smu busy status before sending another request
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 02/13] drm/amd/display: Fix HDCP QUERY Error for eDP and Tiled Tom Chung
` (12 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Charlene Liu, Oliver Logush, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Rodrigo.Siqueira, roman.li,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Tom Chung,
Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Oliver Logush <oliver.logush@amd.com>
[why]
Need to check if result register is busy before sending another request
[how]
Call method to check if result register is busy
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Oliver Logush <oliver.logush@amd.com>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
index d9920d91838d..1cae01a91a69 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -94,6 +94,8 @@ static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
{
uint32_t result;
+ result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
+
/* First clear response register */
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 02/13] drm/amd/display: Fix HDCP QUERY Error for eDP and Tiled
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
2022-04-22 16:44 ` [PATCH 01/13] drm/amd/display: Insert smu busy status before sending another request Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 03/13] drm/amd/display: 3.2.182 Tom Chung
` (11 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, James Zhang, Tom Chung, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, Wenjing Liu,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Mustapha Ghaddar,
Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Mustapha Ghaddar <mghaddar@amd.com>
[WHY]
For dio_output_encoder ID we are relying on SW concept which is
invisible to HW
[HOW]
Needed to create separate cases for when DPIA and non DPIA for
dio link encoder ID
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: James Zhang <james.zhang@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index faab1460d0b5..3d13ee32a3db 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3966,8 +3966,12 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
if (is_dp_128b_132b_signal(pipe_ctx))
config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
- /* dio output index */
- config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+ /* dio output index is dpia index for DPIA endpoint & dcio index by default */
+ if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
+ config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
+ else
+ config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+
/* phy index */
config.phy_idx = resource_transmitter_to_phy_idx(
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 03/13] drm/amd/display: 3.2.182
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
2022-04-22 16:44 ` [PATCH 01/13] drm/amd/display: Insert smu busy status before sending another request Tom Chung
2022-04-22 16:44 ` [PATCH 02/13] drm/amd/display: Fix HDCP QUERY Error for eDP and Tiled Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 04/13] drm/amd/display: update dcn315 clk table read Tom Chung
` (10 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Aric Cyr, Tom Chung, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Aric Cyr <aric.cyr@amd.com>
This version brings along following improvements:
- Fix HDCP QUERY Error for eDP and Tiled
- Insert smu busy status before sending another request
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 2f0c436dae4c..5c85e52e5406 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.181"
+#define DC_VER "3.2.182"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 04/13] drm/amd/display: update dcn315 clk table read
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (2 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 03/13] drm/amd/display: 3.2.182 Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 05/13] drm/amd/display: Add Audio readback registers Tom Chung
` (9 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Dmytro Laktyushkin, Tom Chung, Sunpeng.Li,
Harry.Wentland, Qingqing Zhuo, Rodrigo.Siqueira, roman.li,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Clean up the sequence by making sure clk_mgr always builds a
reasonable clock table regardless of what we read from smu
by moving all defaults from resource soc struct to clk_mgr.
Now the only thing resource soc update does is read
the clock table and apply any DC specific policy decisions
to how clocks are populated in dml soc.
Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
---
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 114 +++++++++-----
.../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 145 ++++--------------
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 +
3 files changed, 111 insertions(+), 149 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 8be4c1970628..27501b735a9c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -219,8 +219,50 @@ static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *reg
static struct clk_bw_params dcn315_bw_params = {
.vram_type = Ddr4MemType,
- .num_channels = 1,
+ .num_channels = 2,
.clk_table = {
+ .entries = {
+ {
+ .voltage = 0,
+ .dispclk_mhz = 640,
+ .dppclk_mhz = 640,
+ .phyclk_mhz = 810,
+ .phyclk_d18_mhz = 667,
+ .dtbclk_mhz = 600,
+ },
+ {
+ .voltage = 1,
+ .dispclk_mhz = 739,
+ .dppclk_mhz = 739,
+ .phyclk_mhz = 810,
+ .phyclk_d18_mhz = 667,
+ .dtbclk_mhz = 600,
+ },
+ {
+ .voltage = 2,
+ .dispclk_mhz = 960,
+ .dppclk_mhz = 960,
+ .phyclk_mhz = 810,
+ .phyclk_d18_mhz = 667,
+ .dtbclk_mhz = 600,
+ },
+ {
+ .voltage = 3,
+ .dispclk_mhz = 1200,
+ .dppclk_mhz = 1200,
+ .phyclk_mhz = 810,
+ .phyclk_d18_mhz = 667,
+ .dtbclk_mhz = 600,
+ },
+ {
+ .voltage = 4,
+ .dispclk_mhz = 1372,
+ .dppclk_mhz = 1372,
+ .phyclk_mhz = 810,
+ .phyclk_d18_mhz = 667,
+ .dtbclk_mhz = 600,
+ },
+ },
.num_entries = 5,
},
@@ -300,8 +342,8 @@ static struct wm_table lpddr5_wm_table = {
}
};
-static DpmClocks_315_t dummy_clocks;
-
+/* Temporary Place holder until we can get them from fuse */
+static DpmClocks_315_t dummy_clocks = { 0 };
static struct dcn315_watermarks dummy_wms = { 0 };
static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
@@ -415,22 +457,6 @@ static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
return max;
}
-static unsigned int find_clk_for_voltage(
- const DpmClocks_315_t *clock_table,
- const uint32_t clocks[],
- unsigned int voltage)
-{
- int i;
-
- for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
- if (clock_table->SocVoltage[i] == voltage)
- return clocks[i];
- }
-
- ASSERT(0);
- return 0;
-}
-
static void dcn315_clk_mgr_helper_populate_bw_params(
struct clk_mgr_internal *clk_mgr,
struct integrated_info *bios_info,
@@ -438,13 +464,9 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
{
int i;
struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
- uint32_t max_dispclk, max_dppclk, max_pstate, max_socclk, max_fclk = 0, min_pstate = 0;
+ uint32_t max_pstate = 0, max_fclk = 0, min_pstate = 0;
struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
- max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
- max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
- max_socclk = find_max_clk_value(clock_table->SocClocks, clock_table->NumSocClkLevelsEnabled);
-
/* Find highest fclk pstate */
for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) {
if (clock_table->DfPstateTable[i].FClk > max_fclk) {
@@ -466,35 +488,44 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
}
}
+ /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
+ for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
+ if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
+ break;
+ bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
+ bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
+ bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
+
+ /* Now update clocks we do read */
bw_params->clk_table.entries[i].fclk_mhz = min_fclk;
bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk;
bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[min_pstate].Voltage;
bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
- bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
- bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
+ bw_params->clk_table.entries[i].dispclk_mhz = clock_table->DispClocks[i];
+ bw_params->clk_table.entries[i].dppclk_mhz = clock_table->DppClocks[i];
bw_params->clk_table.entries[i].wck_ratio = 1;
};
/* Make sure to include at least one entry and highest pstate */
- if (max_pstate != min_pstate) {
+ if (max_pstate != min_pstate || i == 0) {
bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[max_pstate].Voltage;
- bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(
- clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[max_pstate].Voltage);
- bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(
- clock_table, clock_table->SocClocks, clock_table->DfPstateTable[max_pstate].Voltage);
- bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
- bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
+ bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
bw_params->clk_table.entries[i].wck_ratio = 1;
i++;
}
- bw_params->clk_table.num_entries = i;
+ bw_params->clk_table.num_entries = i--;
- /* Include highest socclk */
- if (bw_params->clk_table.entries[i-1].socclk_mhz < max_socclk)
- bw_params->clk_table.entries[i-1].socclk_mhz = max_socclk;
+ /* Make sure all highest clocks are included*/
+ bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
+ bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
+ bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
+ ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
+ bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
+ bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
+ bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
/* Set any 0 clocks to max default setting. Not an issue for
* power since we aren't doing switching in such case anyway
@@ -513,9 +544,18 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
if (!bw_params->clk_table.entries[i].dppclk_mhz)
bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
+ if (!bw_params->clk_table.entries[i].phyclk_mhz)
+ bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
+ if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
+ bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
+ if (!bw_params->clk_table.entries[i].dtbclk_mhz)
+ bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
}
+ ASSERT(bw_params->clk_table.entries[i].dcfclk_mhz);
bw_params->vram_type = bios_info->memory_type;
bw_params->num_channels = bios_info->ma_channel_number;
+ if (!bw_params->num_channels)
+ bw_params->num_channels = 2;
for (i = 0; i < WM_SET_COUNT; i++) {
bw_params->wm_table.entries[i].wm_inst = i;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index a0a2e125c9c8..54db2eca9e6b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -260,55 +260,6 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = {
};
struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = {
- /*TODO: correct dispclk/dppclk voltage level determination*/
- .clock_limits = {
- {
- .state = 0,
- .dispclk_mhz = 1372.0,
- .dppclk_mhz = 1372.0,
- .phyclk_mhz = 810.0,
- .phyclk_d18_mhz = 667.0,
- .dscclk_mhz = 417.0,
- .dtbclk_mhz = 600.0,
- },
- {
- .state = 1,
- .dispclk_mhz = 1372.0,
- .dppclk_mhz = 1372.0,
- .phyclk_mhz = 810.0,
- .phyclk_d18_mhz = 667.0,
- .dscclk_mhz = 417.0,
- .dtbclk_mhz = 600.0,
- },
- {
- .state = 2,
- .dispclk_mhz = 1372.0,
- .dppclk_mhz = 1372.0,
- .phyclk_mhz = 810.0,
- .phyclk_d18_mhz = 667.0,
- .dscclk_mhz = 417.0,
- .dtbclk_mhz = 600.0,
- },
- {
- .state = 3,
- .dispclk_mhz = 1372.0,
- .dppclk_mhz = 1372.0,
- .phyclk_mhz = 810.0,
- .phyclk_d18_mhz = 667.0,
- .dscclk_mhz = 417.0,
- .dtbclk_mhz = 600.0,
- },
- {
- .state = 4,
- .dispclk_mhz = 1372.0,
- .dppclk_mhz = 1372.0,
- .phyclk_mhz = 810.0,
- .phyclk_d18_mhz = 667.0,
- .dscclk_mhz = 417.0,
- .dtbclk_mhz = 600.0,
- },
- },
- .num_states = 5,
.sr_exit_time_us = 9.0,
.sr_enter_plus_exit_time_us = 11.0,
.sr_exit_z8_time_us = 50.0,
@@ -696,80 +647,50 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
{
struct clk_limit_table *clk_table = &bw_params->clk_table;
- struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
- unsigned int i, closest_clk_lvl;
- int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
- int j;
+ int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0;
dc_assert_fp_enabled();
- // Default clock levels are used for diags, which may lead to overclocking.
- if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
-
- dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
- dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count;
- dcn3_15_soc.num_chans = bw_params->num_channels;
+ dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
+ dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count;
+ dcn3_15_soc.num_chans = bw_params->num_channels;
- ASSERT(clk_table->num_entries);
+ ASSERT(clk_table->num_entries);
- /* Prepass to find max clocks independent of voltage level. */
- for (i = 0; i < clk_table->num_entries; ++i) {
- if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
- max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
- if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
- max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
- }
+ /* Setup soc to always use max dispclk/dppclk to avoid odm-to-lower-voltage */
+ for (i = 0; i < clk_table->num_entries; ++i) {
+ if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
+ max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
+ if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
+ max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
+ }
- for (i = 0; i < clk_table->num_entries; i++) {
- /* loop backwards*/
- for (closest_clk_lvl = 0, j = dcn3_15_soc.num_states - 1; j >= 0; j--) {
- if ((unsigned int) dcn3_15_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
- closest_clk_lvl = j;
- break;
- }
- }
- if (clk_table->num_entries == 1) {
- /*smu gives one DPM level, let's take the highest one*/
- closest_clk_lvl = dcn3_15_soc.num_states - 1;
- }
+ for (i = 0; i < clk_table->num_entries; i++) {
+ dcn3_15_soc.clock_limits[i].state = i;
- clock_limits[i].state = i;
+ /* Clocks dependent on voltage level. */
+ dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+ dcn3_15_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+ dcn3_15_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+ dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
- /* Clocks dependent on voltage level. */
- clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
- if (clk_table->num_entries == 1 &&
- clock_limits[i].dcfclk_mhz < dcn3_15_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
- /*SMU fix not released yet*/
- clock_limits[i].dcfclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
- }
- clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
- clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
- clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
-
- /* Clocks independent of voltage level. */
- clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
- dcn3_15_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-
- clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
- dcn3_15_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+ /* These aren't actually read from smu, but rather set in clk_mgr defaults */
+ dcn3_15_soc.clock_limits[i].dtbclk_mhz = clk_table->entries[i].dtbclk_mhz;
+ dcn3_15_soc.clock_limits[i].phyclk_d18_mhz = clk_table->entries[i].phyclk_d18_mhz;
+ dcn3_15_soc.clock_limits[i].phyclk_mhz = clk_table->entries[i].phyclk_mhz;
- clock_limits[i].dram_bw_per_chan_gbps = dcn3_15_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
- clock_limits[i].dscclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
- clock_limits[i].dtbclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
- clock_limits[i].phyclk_d18_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
- clock_limits[i].phyclk_mhz = dcn3_15_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
- }
- for (i = 0; i < clk_table->num_entries; i++)
- dcn3_15_soc.clock_limits[i] = clock_limits[i];
- if (clk_table->num_entries) {
- dcn3_15_soc.num_states = clk_table->num_entries;
- }
+ /* Clocks independent of voltage level. */
+ dcn3_15_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
+ dcn3_15_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
+ dcn3_15_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3.0;
}
+ dcn3_15_soc.num_states = clk_table->num_entries;
- if (max_dispclk_mhz) {
- dcn3_15_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
- dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
- }
+
+ /* Set vco to max_dispclk * 2 to make sure the highest dispclk is always available for dml calcs,
+ * no impact outside of dml validation
+ */
+ dcn3_15_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index c920c4b6077d..46ce5a0ee4ec 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -91,6 +91,7 @@ struct clk_limit_table_entry {
unsigned int dispclk_mhz;
unsigned int dppclk_mhz;
unsigned int phyclk_mhz;
+ unsigned int phyclk_d18_mhz;
unsigned int wck_ratio;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 05/13] drm/amd/display: Add Audio readback registers
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (3 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 04/13] drm/amd/display: update dcn315 clk table read Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 06/13] drm/amd/display: Reset cached PSR parameters after hibernate Tom Chung
` (8 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Ilya, Aric Cyr, Tom Chung, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Rodrigo.Siqueira, roman.li,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Ilya <Ilya.Bakoulin@amd.com>
[Why]
Can be useful for verifying the correctness of audio output.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 1 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 8 ++++++++
.../drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h | 4 ++++
3 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index b0c08ee6bc2c..7608187751c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -25,6 +25,7 @@
#include <linux/delay.h>
+#include "dm_services.h"
#include "dc_bios_types.h"
#include "dcn10_stream_encoder.h"
#include "reg_helper.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 687d7e4bf7ca..293595a33982 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -92,6 +92,8 @@
SRI(DP_VID_STREAM_CNTL, DP, id), \
SRI(DP_VID_TIMING, DP, id), \
SRI(DP_SEC_AUD_N, DP, id), \
+ SRI(DP_SEC_AUD_N_READBACK, DP, id), \
+ SRI(DP_SEC_AUD_M_READBACK, DP, id), \
SRI(DP_SEC_TIMESTAMP, DP, id), \
SRI(DIG_CLOCK_PATTERN, DIG, id)
@@ -140,6 +142,8 @@ struct dcn10_stream_enc_registers {
uint32_t DP_VID_STREAM_CNTL;
uint32_t DP_VID_TIMING;
uint32_t DP_SEC_AUD_N;
+ uint32_t DP_SEC_AUD_N_READBACK;
+ uint32_t DP_SEC_AUD_M_READBACK;
uint32_t DP_SEC_TIMESTAMP;
uint32_t HDMI_CONTROL;
uint32_t HDMI_GC;
@@ -256,6 +260,8 @@ struct dcn10_stream_enc_registers {
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
+ SE_SF(DP0_DP_SEC_AUD_N_READBACK, DP_SEC_AUD_N_READBACK, mask_sh),\
+ SE_SF(DP0_DP_SEC_AUD_M_READBACK, DP_SEC_AUD_M_READBACK, mask_sh),\
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
@@ -473,6 +479,8 @@ struct dcn10_stream_enc_registers {
type AFMT_60958_CS_CHANNEL_NUMBER_6;\
type AFMT_60958_CS_CHANNEL_NUMBER_7;\
type DP_SEC_AUD_N;\
+ type DP_SEC_AUD_N_READBACK;\
+ type DP_SEC_AUD_M_READBACK;\
type DP_SEC_TIMESTAMP_MODE;\
type DP_SEC_ASP_ENABLE;\
type DP_SEC_ATP_ENABLE;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
index e2c264ecb20f..42140e73c3b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
@@ -95,6 +95,8 @@
SRI(DP_VID_STREAM_CNTL, DP, id), \
SRI(DP_VID_TIMING, DP, id), \
SRI(DP_SEC_AUD_N, DP, id), \
+ SRI(DP_SEC_AUD_N_READBACK, DP, id), \
+ SRI(DP_SEC_AUD_M_READBACK, DP, id), \
SRI(DP_SEC_TIMESTAMP, DP, id), \
SRI(DP_DSC_CNTL, DP, id), \
SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
@@ -157,6 +159,8 @@
SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
+ SE_SF(DP0_DP_SEC_AUD_N_READBACK, DP_SEC_AUD_N_READBACK, mask_sh),\
+ SE_SF(DP0_DP_SEC_AUD_M_READBACK, DP_SEC_AUD_M_READBACK, mask_sh),\
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 06/13] drm/amd/display: Reset cached PSR parameters after hibernate
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (4 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 05/13] drm/amd/display: Add Audio readback registers Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 07/13] drm/amd/display: Don't pass HostVM by default on DCN3.1 Tom Chung
` (7 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Tom Chung, Evgenii Krasnikov, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Rodrigo.Siqueira, roman.li,
solomon.chiu, Aurabindo.Pillai, Harry Vanzylldejong, wayne.lin,
Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
[WHY]
After hibernate system might be using old invalid psr_power_opt and
psr_allow_active that never get reset
[HOW]
Reset cached Panel Self Refresh parameters when PSR is first configured
for eDP in dc_link_setup_psr.
Reviewed-by: Harry Vanzylldejong <harry.vanzylldejong@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 3d13ee32a3db..1eddf2785153 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3317,9 +3317,14 @@ bool dc_link_setup_psr(struct dc_link *link,
*/
psr_context->frame_delay = 0;
- if (psr)
+ if (psr) {
link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
link, psr_context, panel_inst);
+ if (link->psr_settings.psr_feature_enabled) {
+ link->psr_settings.psr_power_opt = 0;
+ link->psr_settings.psr_allow_active = 0;
+ }
+ }
else
link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 07/13] drm/amd/display: Don't pass HostVM by default on DCN3.1
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (5 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 06/13] drm/amd/display: Reset cached PSR parameters after hibernate Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 08/13] drm/amd/display: read PSR-SU cap DPCD for specific panel Tom Chung
` (6 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Tom Chung, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, Michael Strauss, wayne.lin, Bhawanpreet.Lakha,
Nicholas Kazlauskas, agustin.gutierrez, pavle.kotarac
From: Michael Strauss <michael.strauss@amd.com>
[WHY]
Roll back previous change to stop passing this value by default, instead
add a debug flag to override to previous behaviour (or force HostVM calcs)
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 7 +++++++
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 9 ++++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5c85e52e5406..78b9df776503 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -359,6 +359,12 @@ enum dc_psr_power_opts {
psr_power_opt_ds_disable_allow = 0x100,
};
+enum dml_hostvm_override_opts {
+ DML_HOSTVM_NO_OVERRIDE = 0x0,
+ DML_HOSTVM_OVERRIDE_FALSE = 0x1,
+ DML_HOSTVM_OVERRIDE_TRUE = 0x2,
+};
+
enum dcc_option {
DCC_ENABLE = 0,
DCC_DISABLE = 1,
@@ -733,6 +739,7 @@ struct dc_debug_options {
bool extended_blank_optimization;
union aux_wake_wa_options aux_wake_wa;
uint8_t psr_power_use_phy_fsm;
+ enum dml_hostvm_override_opts dml_hostvm_override;
};
struct gpu_info_soc_bounding_box_v1_0;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 5b3f0c2dfb55..d3edc9d11d88 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -890,6 +890,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.enable_sw_cntl_psr = true,
.apply_vendor_specific_lttpr_wa = true,
.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
+ .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
};
static const struct dc_debug_options debug_defaults_diags = {
@@ -1666,7 +1667,6 @@ int dcn31_populate_dml_pipes_from_context(
* intermittently experienced depending on peak b/w requirements.
*/
pipes[pipe_cnt].pipe.src.immediate_flip = true;
-
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
pipes[pipe_cnt].pipe.src.gpuvm = true;
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
@@ -1675,6 +1675,13 @@ int dcn31_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.src.dcc_rate = 3;
pipes[pipe_cnt].dout.dsc_input_bpc = 0;
+ if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)
+ pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
+ else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
+ pipes[pipe_cnt].pipe.src.hostvm = false;
+ else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
+ pipes[pipe_cnt].pipe.src.hostvm = true;
+
if (pipes[pipe_cnt].dout.dsc_enable) {
switch (timing->display_color_depth) {
case COLOR_DEPTH_888:
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 08/13] drm/amd/display: read PSR-SU cap DPCD for specific panel
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (6 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 07/13] drm/amd/display: Don't pass HostVM by default on DCN3.1 Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 09/13] drm/amd/display: Remove ddc write and read size checking Tom Chung
` (5 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, David Zhang, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, wayne.lin, Tom Chung, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: David Zhang <dingchen.zhang@amd.com>
[why & how]
For some specific eDP panel, we'd check the PSR-SU cap during boot
by reading the vendor specific DPCD, otherwise it will cause to
false report the eDP panel which supports PSR-SU as an non-PSR-SU
panel.
- add the vendor specific DPCD address in ddc_service_types header
- if specific eDP panel detected, check vendor specific DPCD for
PSR-SU cap
Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++++
drivers/gpu/drm/amd/display/include/ddc_service_types.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index c5f5d25035d2..10f990eefe7d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5822,6 +5822,10 @@ void detect_edp_sink_caps(struct dc_link *link)
core_link_read_dpcd(link, DP_PSR_SUPPORT,
&link->dpcd_caps.psr_info.psr_version,
sizeof(link->dpcd_caps.psr_info.psr_version));
+ if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
+ core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY,
+ &link->dpcd_caps.psr_info.force_psrsu_cap,
+ sizeof(link->dpcd_caps.psr_info.force_psrsu_cap));
core_link_read_dpcd(link, DP_PSR_CAPS,
&link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw));
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index f883d87791fe..73b9e0a87e54 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -39,6 +39,8 @@
#define DP_BRANCH_HW_REV_20 0x20
#define DP_DEVICE_ID_38EC11 0x38EC11
+#define DP_FORCE_PSRSU_CAPABILITY 0x40F
+
enum ddc_result {
DDC_RESULT_UNKNOWN = 0,
DDC_RESULT_SUCESSFULL,
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 09/13] drm/amd/display: Remove ddc write and read size checking
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (7 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 08/13] drm/amd/display: read PSR-SU cap DPCD for specific panel Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 10/13] drm/amd/display: Maintain current link settings in link loss interrupt Tom Chung
` (4 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Tom Chung, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Martin Leung, Rodrigo.Siqueira, roman.li,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Leo (Hanghong) Ma,
Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
[Why]
Customer found I2C over AUX using ADL_Display_DDCBlockAccess_Get
will fail when sending more than 256 bytes of data;
[How]
Remove the write and read size checking to allow sending data more
than 256 bytes;
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Leo Ma <hanghong.ma@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 1d4863763df9..2b09310965bc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -543,15 +543,9 @@ bool dal_ddc_service_query_ddc_data(
uint32_t payloads_num = write_payloads + read_payloads;
-
- if (write_size > EDID_SEGMENT_SIZE || read_size > EDID_SEGMENT_SIZE)
- return false;
-
if (!payloads_num)
return false;
- /*TODO: len of payload data for i2c and aux is uint8!!!!,
- * but we want to read 256 over i2c!!!!*/
if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
struct aux_payload payload;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 10/13] drm/amd/display: Maintain current link settings in link loss interrupt
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (8 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 09/13] drm/amd/display: Remove ddc write and read size checking Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 11/13] drm/amd/display: Remove unused integer Tom Chung
` (3 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Tom Chung, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, Wenjing Liu, Gary Li,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Gary Li <garyli12@amd.com>
[Why]
DP compliance test case 400.3.2.3 is failed because in link loss interrupt
the current link settings is not used in the DP link training.
[How]
In link loss interrupt, use the current link settings in the following DP
link training.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Gary Li <garyli12@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 10f990eefe7d..50a12fd08f4a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -4576,6 +4576,7 @@ void dc_link_dp_handle_link_loss(struct dc_link *link)
{
int i;
struct pipe_ctx *pipe_ctx;
+ struct dc_link_settings prev_link_settings = link->preferred_link_setting;
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
@@ -4586,6 +4587,10 @@ void dc_link_dp_handle_link_loss(struct dc_link *link)
if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
return;
+ /* toggle stream state with the preference for current link settings */
+ dc_link_set_preferred_training_settings((struct dc *)link->dc,
+ &link->cur_link_settings, NULL, link, true);
+
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
@@ -4601,6 +4606,10 @@ void dc_link_dp_handle_link_loss(struct dc_link *link)
core_link_enable_stream(link->dc->current_state, pipe_ctx);
}
}
+
+ /* restore previous link settings preference */
+ dc_link_set_preferred_training_settings((struct dc *)link->dc,
+ &prev_link_settings, NULL, link, true);
}
bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss,
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 11/13] drm/amd/display: Remove unused integer
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (9 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 10/13] drm/amd/display: Maintain current link settings in link loss interrupt Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 12/13] drm/amd/display: Keep track of DSC packed PPS Tom Chung
` (2 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Dillon Varone, Tom Chung, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Martin Leung, Rodrigo.Siqueira,
roman.li, solomon.chiu, Aurabindo.Pillai, wayne.lin,
Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Dillon Varone <dillon.varone@amd.com>
Integer no longer needed.
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 78b9df776503..47b56d2a6125 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -423,7 +423,6 @@ struct dc_clocks {
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dcn_zstate_support_state zstate_support;
bool dtbclk_en;
- int dtbclk_khz;
#endif
enum dcn_pwr_state pwr_state;
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 12/13] drm/amd/display: Keep track of DSC packed PPS
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (10 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 11/13] drm/amd/display: Remove unused integer Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-22 16:44 ` [PATCH 13/13] drm/amd/display: 3.2.183 Tom Chung
2022-04-25 13:06 ` [PATCH 00/13] DC Patches April 20 2022 Wheeler, Daniel
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Ilya, Aric Cyr, Tom Chung, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Rodrigo.Siqueira, roman.li,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Ilya <Ilya.Bakoulin@amd.com>
[Why]
Store current packed PPS data in dc_stream_state for future use.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 50a12fd08f4a..c15c46b81111 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -7578,6 +7578,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u
DC_LOG_DSC(" ");
dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
+ memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps));
if (dc_is_dp_signal(stream->signal)) {
DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
if (is_dp_128b_132b_signal(pipe_ctx))
@@ -7595,6 +7596,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u
}
} else {
/* disable DSC PPS in stream encoder */
+ memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps));
if (dc_is_dp_signal(stream->signal)) {
if (is_dp_128b_132b_signal(pipe_ctx))
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 580420c3eedc..58941f4defb3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -162,7 +162,7 @@ struct dc_stream_state {
struct dc_info_packet vrr_infopacket;
struct dc_info_packet vsc_infopacket;
struct dc_info_packet vsp_infopacket;
-
+ uint8_t dsc_packed_pps[128];
struct rect src; /* composition area */
struct rect dst; /* stream addressable area */
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 13/13] drm/amd/display: 3.2.183
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (11 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 12/13] drm/amd/display: Keep track of DSC packed PPS Tom Chung
@ 2022-04-22 16:44 ` Tom Chung
2022-04-25 13:06 ` [PATCH 00/13] DC Patches April 20 2022 Wheeler, Daniel
13 siblings, 0 replies; 15+ messages in thread
From: Tom Chung @ 2022-04-22 16:44 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Aric Cyr, Tom Chung, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Aric Cyr <aric.cyr@amd.com>
This version brings along following fixes:
- Keep tracking of DSC packed PPS for future use
- Maintain current link settings in link loss interrupt
- Remove DDC write and read size check
- Read PSR-SU cap DPCD for specific panel
- Don't pass HostVM by default on DCN3.1
- Reset cached PSR parameters after hibernate
- Add audio readback registers
- Update dcn315 clk table read
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 47b56d2a6125..a649aec78868 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.182"
+#define DC_VER "3.2.183"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* RE: [PATCH 00/13] DC Patches April 20 2022
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
` (12 preceding siblings ...)
2022-04-22 16:44 ` [PATCH 13/13] drm/amd/display: 3.2.183 Tom Chung
@ 2022-04-25 13:06 ` Wheeler, Daniel
13 siblings, 0 replies; 15+ messages in thread
From: Wheeler, Daniel @ 2022-04-25 13:06 UTC (permalink / raw)
To: Chung, ChiaHsuan (Tom), amd-gfx
Cc: Wang, Chao-kai (Stylon), Chung, ChiaHsuan (Tom),
Li, Sun peng (Leo), Lakha, Bhawanpreet, Zhuo, Qingqing (Lillian),
Siqueira, Rodrigo, Li, Roman, Chiu, Solomon, Pillai, Aurabindo,
Lin, Wayne, Wentland, Harry, Gutierrez, Agustin, Kotarac, Pavle
[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Sapphire Pulse RX5700XT with the following display types:
4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Reference AMD RX6800 with the following display types:
4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz and DSC via USB-C to DP DSC Hub with 3x 4k 60hz.
Tested on Ubuntu 20.04.3 with Kernel Version 5.16 and ChromeOS
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Technologist | AMD
SW Display
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Tom Chung
Sent: April 22, 2022 12:45 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Chung, ChiaHsuan (Tom) <ChiaHsuan.Chung@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
Subject: [PATCH 00/13] DC Patches April 20 2022
This version brings along following fixes:
- Keep tracking of DSC packed PPS for future use
- Maintain current link settings in link loss interrupt
- Remove DDC write and read size check
- Read PSR-SU cap DPCD for specific panel
- Don't pass HostVM by default on DCN3.1
- Reset cached PSR parameters after hibernate
- Add audio readback registers
- Update dcn315 clk table read
- Fix HDCP QUERY Error for eDP and Tiled
- Insert smu busy status before sending another request
Aric Cyr (2):
drm/amd/display: 3.2.182
drm/amd/display: 3.2.183
David Zhang (1):
drm/amd/display: read PSR-SU cap DPCD for specific panel
Dillon Varone (1):
drm/amd/display: Remove unused integer
Dmytro Laktyushkin (1):
drm/amd/display: update dcn315 clk table read
Evgenii Krasnikov (1):
drm/amd/display: Reset cached PSR parameters after hibernate
Gary Li (1):
drm/amd/display: Maintain current link settings in link loss interrupt
Ilya (2):
drm/amd/display: Add Audio readback registers
drm/amd/display: Keep track of DSC packed PPS
Leo (Hanghong) Ma (1):
drm/amd/display: Remove ddc write and read size checking
Michael Strauss (1):
drm/amd/display: Don't pass HostVM by default on DCN3.1
Mustapha Ghaddar (1):
drm/amd/display: Fix HDCP QUERY Error for eDP and Tiled
Oliver Logush (1):
drm/amd/display: Insert smu busy status before sending another request
.../display/dc/clk_mgr/dcn301/dcn301_smu.c | 2 +
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 114 +++++++++-----
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 +-
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 6 -
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 15 ++
drivers/gpu/drm/amd/display/dc/dc.h | 10 +-
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 +-
.../display/dc/dcn10/dcn10_stream_encoder.c | 1 +
.../display/dc/dcn10/dcn10_stream_encoder.h | 8 +
.../dc/dcn30/dcn30_dio_stream_encoder.h | 4 +
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 9 +-
.../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 145 ++++--------------
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 +
.../amd/display/include/ddc_service_types.h | 2 +
14 files changed, 172 insertions(+), 162 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-04-25 13:06 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-22 16:44 [PATCH 00/13] DC Patches April 20 2022 Tom Chung
2022-04-22 16:44 ` [PATCH 01/13] drm/amd/display: Insert smu busy status before sending another request Tom Chung
2022-04-22 16:44 ` [PATCH 02/13] drm/amd/display: Fix HDCP QUERY Error for eDP and Tiled Tom Chung
2022-04-22 16:44 ` [PATCH 03/13] drm/amd/display: 3.2.182 Tom Chung
2022-04-22 16:44 ` [PATCH 04/13] drm/amd/display: update dcn315 clk table read Tom Chung
2022-04-22 16:44 ` [PATCH 05/13] drm/amd/display: Add Audio readback registers Tom Chung
2022-04-22 16:44 ` [PATCH 06/13] drm/amd/display: Reset cached PSR parameters after hibernate Tom Chung
2022-04-22 16:44 ` [PATCH 07/13] drm/amd/display: Don't pass HostVM by default on DCN3.1 Tom Chung
2022-04-22 16:44 ` [PATCH 08/13] drm/amd/display: read PSR-SU cap DPCD for specific panel Tom Chung
2022-04-22 16:44 ` [PATCH 09/13] drm/amd/display: Remove ddc write and read size checking Tom Chung
2022-04-22 16:44 ` [PATCH 10/13] drm/amd/display: Maintain current link settings in link loss interrupt Tom Chung
2022-04-22 16:44 ` [PATCH 11/13] drm/amd/display: Remove unused integer Tom Chung
2022-04-22 16:44 ` [PATCH 12/13] drm/amd/display: Keep track of DSC packed PPS Tom Chung
2022-04-22 16:44 ` [PATCH 13/13] drm/amd/display: 3.2.183 Tom Chung
2022-04-25 13:06 ` [PATCH 00/13] DC Patches April 20 2022 Wheeler, Daniel
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