* [PATCH 01/15] drm/amd/display: Refactor LTTPR cap retrieval
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 02/15] drm/amd/display: Reset cached PSR parameters after hibernate Stylon Wang
` (14 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Wesley Chalmers, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, Michael Strauss, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Michael Strauss <michael.strauss@amd.com>
[WHY]
Split LTTPR mode selection between platform support and downstream link support
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 175 +++++++++++-------
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 +
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 3 +-
.../amd/display/include/link_service_types.h | 6 +
4 files changed, 113 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 55a5a6a49fe2..5e49e346aa06 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5097,16 +5097,13 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
return true;
}
-bool dp_retrieve_lttpr_cap(struct dc_link *link)
+void dp_retrieve_lttpr_cap(struct dc_link *link)
{
- uint8_t lttpr_dpcd_data[8];
bool allow_lttpr_non_transparent_mode = 0;
- bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
enum dc_status status = DC_ERROR_UNEXPECTED;
- bool is_lttpr_present = false;
- memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
+ memset(link->lttpr_dpcd_data, '\0', sizeof(link->lttpr_dpcd_data));
if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
@@ -5116,88 +5113,118 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
allow_lttpr_non_transparent_mode = 1;
}
+ link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
+ link->lttpr_support = LTTPR_UNSUPPORTED;
+
/*
- * Logic to determine LTTPR mode
+ * Logic to determine LTTPR support
*/
- link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
- if (vbios_lttpr_enable && vbios_lttpr_interop)
- link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
- else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
- if (allow_lttpr_non_transparent_mode)
- link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
- else
- link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
- } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
- if (!allow_lttpr_non_transparent_mode || !link->dc->caps.extended_aux_timeout_support)
- link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
- else
- link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
- }
+ if (vbios_lttpr_interop)
+ link->lttpr_support = LTTPR_SUPPORTED;
+ else if (link->dc->config.allow_lttpr_non_transparent_mode.raw == 0
+ || !link->dc->caps.extended_aux_timeout_support)
+ link->lttpr_support = LTTPR_UNSUPPORTED;
+ else
+ link->lttpr_support = LTTPR_CHECK_EXT_SUPPORT;
+
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Check DP tunnel LTTPR mode debug option. */
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
link->dc->debug.dpia_debug.bits.force_non_lttpr)
- link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
+ link->lttpr_support = LTTPR_UNSUPPORTED;
#endif
- if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
+ if (link->lttpr_support > LTTPR_UNSUPPORTED) {
/* By reading LTTPR capability, RX assumes that we will enable
* LTTPR extended aux timeout if LTTPR is present.
*/
status = core_link_read_dpcd(
link,
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
- lttpr_dpcd_data,
- sizeof(lttpr_dpcd_data));
- if (status != DC_OK) {
- DC_LOG_DP2("%s: Read LTTPR caps data failed.\n", __func__);
- link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
- return false;
- }
+ link->lttpr_dpcd_data,
+ sizeof(link->lttpr_dpcd_data));
+ }
+}
- link->dpcd_caps.lttpr_caps.revision.raw =
- lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
-
- link->dpcd_caps.lttpr_caps.max_link_rate =
- lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
-
- link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
- lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
-
- link->dpcd_caps.lttpr_caps.max_lane_count =
- lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
-
- link->dpcd_caps.lttpr_caps.mode =
- lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
-
- link->dpcd_caps.lttpr_caps.max_ext_timeout =
- lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
-
- link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
- lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
-
- link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
- lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
-
- /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
- is_lttpr_present = (link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
- link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff &&
- link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
- link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
- if (is_lttpr_present) {
- CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
- configure_lttpr_mode_transparent(link);
- } else
- link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
+bool dp_parse_lttpr_mode(struct dc_link *link)
+{
+ bool dpcd_allow_lttpr_non_transparent_mode = false;
+ bool is_lttpr_present = false;
+
+ bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
+
+ if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
+ link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
+ dpcd_allow_lttpr_non_transparent_mode = true;
+ } else if (link->dc->config.allow_lttpr_non_transparent_mode.bits.DP1_4A &&
+ !link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
+ dpcd_allow_lttpr_non_transparent_mode = true;
}
+
+ /*
+ * Logic to determine LTTPR mode
+ */
+ if (link->lttpr_support == LTTPR_SUPPORTED)
+ if (vbios_lttpr_enable)
+ link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
+ else if (dpcd_allow_lttpr_non_transparent_mode)
+ link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
+ else
+ link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
+ else // lttpr_support == LTTPR_CHECK_EXT_SUPPORT
+ if (dpcd_allow_lttpr_non_transparent_mode) {
+ link->lttpr_support = LTTPR_SUPPORTED;
+ link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
+ } else {
+ link->lttpr_support = LTTPR_UNSUPPORTED;
+ }
+
+ if (link->lttpr_support == LTTPR_UNSUPPORTED)
+ return false;
+
+ link->dpcd_caps.lttpr_caps.revision.raw =
+ link->lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+
+ link->dpcd_caps.lttpr_caps.max_link_rate =
+ link->lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+
+ link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
+ link->lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+
+ link->dpcd_caps.lttpr_caps.max_lane_count =
+ link->lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+
+ link->dpcd_caps.lttpr_caps.mode =
+ link->lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+
+ link->dpcd_caps.lttpr_caps.max_ext_timeout =
+ link->lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+
+ link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
+ link->lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+
+ link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
+ link->lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+
+
+ /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
+ is_lttpr_present = (link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
+ link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
+ link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
+ if (is_lttpr_present) {
+ CONN_DATA_DETECT(link, link->lttpr_dpcd_data, sizeof(link->lttpr_dpcd_data), "LTTPR Caps: ");
+ configure_lttpr_mode_transparent(link);
+ } else
+ link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
+
return is_lttpr_present;
}
@@ -5349,7 +5376,8 @@ static bool retrieve_link_cap(struct dc_link *link)
status = wa_try_to_wake_dprx(link, timeout_ms);
}
- is_lttpr_present = dp_retrieve_lttpr_cap(link);
+ dp_retrieve_lttpr_cap(link);
+
/* Read DP tunneling information. */
status = dpcd_get_tunneling_device_data(link);
@@ -5385,6 +5413,9 @@ static bool retrieve_link_cap(struct dc_link *link)
return false;
}
+ if (link->lttpr_support > LTTPR_UNSUPPORTED)
+ is_lttpr_present = dp_parse_lttpr_mode(link);
+
if (!is_lttpr_present)
dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index a3c37ee3f849..251f2bbc96b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -129,6 +129,8 @@ struct dc_link {
bool link_state_valid;
bool aux_access_disabled;
bool sync_lt_in_progress;
+ uint8_t lttpr_dpcd_data[8];
+ enum lttpr_support lttpr_support;
enum lttpr_mode lttpr_mode;
bool is_internal_display;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index 44f167d2584f..78f09893c118 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -217,7 +217,8 @@ void disable_dp_hpo_output(struct dc_link *link,
void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable);
bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx);
-bool dp_retrieve_lttpr_cap(struct dc_link *link);
+void dp_retrieve_lttpr_cap(struct dc_link *link);
+bool dp_apply_lttpr_mode(struct dc_link *link);
void edp_panel_backlight_power_on(struct dc_link *link);
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
void dp_source_sequence_trace(struct dc_link *link, uint8_t dp_test_mode);
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 447a56286dd0..9f465b4d626e 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -80,6 +80,12 @@ enum link_training_result {
DP_128b_132b_CDS_DONE_TIMEOUT,
};
+enum lttpr_support {
+ LTTPR_UNSUPPORTED,
+ LTTPR_CHECK_EXT_SUPPORT,
+ LTTPR_SUPPORTED,
+};
+
enum lttpr_mode {
LTTPR_MODE_NON_LTTPR,
LTTPR_MODE_TRANSPARENT,
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 02/15] drm/amd/display: Reset cached PSR parameters after hibernate
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
2022-05-06 15:42 ` [PATCH 01/15] drm/amd/display: Refactor LTTPR cap retrieval Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 03/15] drm/amd/display: move definition of dc_flip_addrs struct Stylon Wang
` (13 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Anthony Koo, Evgenii Krasnikov, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Rodrigo.Siqueira, roman.li,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
[WHY]
After hibernate system might be using old invalid psr_power_opt and
psr_allow_active that never get reset
[HOW]
Reset cached Panel Self Refresh parameters when PSR is first configured
for eDP in dc_link_setup_psr.
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 3d13ee32a3db..48e274f9ea84 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3317,9 +3317,12 @@ bool dc_link_setup_psr(struct dc_link *link,
*/
psr_context->frame_delay = 0;
- if (psr)
+ if (psr) {
link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
link, psr_context, panel_inst);
+ link->psr_settings.psr_power_opt = 0;
+ link->psr_settings.psr_allow_active = 0;
+ }
else
link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 03/15] drm/amd/display: move definition of dc_flip_addrs struct
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
2022-05-06 15:42 ` [PATCH 01/15] drm/amd/display: Refactor LTTPR cap retrieval Stylon Wang
2022-05-06 15:42 ` [PATCH 02/15] drm/amd/display: Reset cached PSR parameters after hibernate Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 04/15] drm/amd/display: do not disable an invalid irq source in hdp finish Stylon Wang
` (12 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Josip Pavic, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, Aric Cyr, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Josip Pavic <Josip.Pavic@amd.com>
[Why & How]
Move definition of dc_flip_addrs struct from dc.h to dc_hw_types.h to
prevent build errors
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 12 ------------
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 942bfb8fd851..e37d9c19f089 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1129,18 +1129,6 @@ struct dc_transfer_func *dc_create_transfer_func(void);
struct dc_3dlut *dc_create_3dlut_func(void);
void dc_3dlut_func_release(struct dc_3dlut *lut);
void dc_3dlut_func_retain(struct dc_3dlut *lut);
-/*
- * This structure holds a surface address. There could be multiple addresses
- * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
- * as frame durations and DCC format can also be set.
- */
-struct dc_flip_addrs {
- struct dc_plane_address address;
- unsigned int flip_timestamp_in_us;
- bool flip_immediate;
- /* TODO: add flip duration for FreeSync */
- bool triplebuffer_flips;
-};
void dc_post_update_surfaces_to_stream(
struct dc *dc);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 0c754cb0459e..aa7e3a07191d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -236,6 +236,22 @@ enum pixel_format {
PIXEL_FORMAT_UNKNOWN
};
+/*
+ * This structure holds a surface address. There could be multiple addresses
+ * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
+ * as frame durations and DCC format can also be set.
+ */
+#define DC_MAX_DIRTY_RECTS 3
+struct dc_flip_addrs {
+ struct dc_plane_address address;
+ unsigned int flip_timestamp_in_us;
+ bool flip_immediate;
+ /* TODO: add flip duration for FreeSync */
+ bool triplebuffer_flips;
+ unsigned int dirty_rect_count;
+ struct rect dirty_rects[DC_MAX_DIRTY_RECTS];
+};
+
enum tile_split_values {
DC_DISPLAY_MICRO_TILING = 0x0,
DC_THIN_MICRO_TILING = 0x1,
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 04/15] drm/amd/display: do not disable an invalid irq source in hdp finish
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (2 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 03/15] drm/amd/display: move definition of dc_flip_addrs struct Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 05/15] drm/amd/display: do not calculate DP2.0 SST payload when link is off Stylon Wang
` (11 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Alan Liu, Sunpeng.Li, Harry.Wentland, Qingqing Zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Alan Liu <HaoPing.Liu@amd.com>
[why]
Observing error log about trying to disable non-implemented irq source
when user unload the driver.
[how]
Check and filter the invalid irq source before disabling it.
Reviewed-by: Qingqing (Lillian) Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 4aba0e8c84f8..19f543ba7205 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -928,7 +928,11 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
to_amdgpu_dm_connector(connector);
const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
- dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
+ if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
+ dc_interrupt_set(adev->dm.dc,
+ dc_link->irq_source_hpd,
+ false);
+ }
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
dc_interrupt_set(adev->dm.dc,
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 05/15] drm/amd/display: do not calculate DP2.0 SST payload when link is off
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (3 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 04/15] drm/amd/display: do not disable an invalid irq source in hdp finish Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 06/15] drm/amd/display: do not wait for vblank during pipe programming Stylon Wang
` (10 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
George Shen, Rodrigo.Siqueira, roman.li, Wenjing Liu,
solomon.chiu, Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
[Why & How]
There is a chance where the RX issues HPD deassert in the
middle of link training, this will cause our logic to
abort link training and turn off link. However our payload
allocation logic needs to use current link settings to
determine average time slot per MTP. This will need to
use current link bandwidth as divider. This causes divide
by zero error occasionally. The fix is to skip DP2.0 payload
allocation logic if current link is not in 128b/132b mode.
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 48e274f9ea84..07f154fc4e56 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3546,7 +3546,8 @@ static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
}
/* slot X.Y for SST payload allocate */
- if (allocate) {
+ if (allocate && dp_get_link_encoding_format(&link->cur_link_settings) ==
+ DP_128b_132b_ENCODING) {
avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 06/15] drm/amd/display: do not wait for vblank during pipe programming
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (4 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 05/15] drm/amd/display: do not calculate DP2.0 SST payload when link is off Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc Stylon Wang
` (9 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Josip Pavic, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, Aric Cyr, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
From: Josip Pavic <Josip.Pavic@amd.com>
[Why]
Waiting for the vlbank every time a global sync update is requested,
including during full update flips, results in a stutter.
[How]
Do not wait for vblank during pipe programming.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index b627c41713cc..e1f87bd72e4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1593,7 +1593,6 @@ static void dcn20_program_pipe(
pipe_ctx->pipe_dlg_param.vupdate_offset,
pipe_ctx->pipe_dlg_param.vupdate_width);
- pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
pipe_ctx->stream_res.tg->funcs->set_vtg_params(
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (5 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 06/15] drm/amd/display: do not wait for vblank during pipe programming Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:56 ` Alex Deucher
2022-05-06 15:42 ` [PATCH 08/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dce Stylon Wang
` (8 subsequent siblings)
15 siblings, 1 reply; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
Alex Hung, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Alex Hung <alex.hung@amd.com>
[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.
This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in dc and dc/core directories.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
drivers/gpu/drm/amd/display/dc/Makefile | 2 -
.../display/dc/bios/command_table_helper2.c | 3 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 31 ++--------------
.../gpu/drm/amd/display/dc/core/dc_debug.c | 2 -
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 --
.../drm/amd/display/dc/core/dc_link_dpia.c | 2 -
.../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ++---------
.../gpu/drm/amd/display/dc/core/dc_stream.c | 8 ----
drivers/gpu/drm/amd/display/dc/dc.h | 37 -------------------
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 -
.../gpu/drm/amd/display/dc/inc/core_types.h | 17 ++-------
12 files changed, 10 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index f05ab2bf20c5..b4eca0236435 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -63,9 +63,7 @@ DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink
dc_surface.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
dc_link_enc_cfg.o dc_link_dpia.o dc_link_dpcd.o
-ifdef CONFIG_DRM_AMD_DC_DCN
DISPLAY_CORE += dc_vm_helper.o
-endif
AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index dd9704ef4ccc..f3792286f571 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -65,7 +65,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCE_VERSION_12_1:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
case DCN_VERSION_1_0:
case DCN_VERSION_1_01:
case DCN_VERSION_2_0:
@@ -80,7 +79,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCN_VERSION_3_16:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
-#endif
+
default:
/* Unsupported DCE */
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c2fcd67bcc4d..1eeea7c184ae 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -829,14 +829,12 @@ static void dc_destruct(struct dc *dc)
kfree(dc->bw_dceip);
dc->bw_dceip = NULL;
-#ifdef CONFIG_DRM_AMD_DC_DCN
kfree(dc->dcn_soc);
dc->dcn_soc = NULL;
kfree(dc->dcn_ip);
dc->dcn_ip = NULL;
-#endif
kfree(dc->vm_helper);
dc->vm_helper = NULL;
@@ -882,10 +880,8 @@ static bool dc_construct(struct dc *dc,
struct dc_context *dc_ctx;
struct bw_calcs_dceip *dc_dceip;
struct bw_calcs_vbios *dc_vbios;
-#ifdef CONFIG_DRM_AMD_DC_DCN
struct dcn_soc_bounding_box *dcn_soc;
struct dcn_ip_params *dcn_ip;
-#endif
dc->config = init_params->flags;
@@ -913,7 +909,6 @@ static bool dc_construct(struct dc *dc,
}
dc->bw_vbios = dc_vbios;
-#ifdef CONFIG_DRM_AMD_DC_DCN
dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
if (!dcn_soc) {
dm_error("%s: failed to create dcn_soc\n", __func__);
@@ -929,7 +924,6 @@ static bool dc_construct(struct dc *dc,
}
dc->dcn_ip = dcn_ip;
-#endif
if (!dc_construct_ctx(dc, init_params)) {
dm_error("%s: failed to create ctx\n", __func__);
@@ -1868,7 +1862,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
return (result == DC_OK);
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dc_acquire_release_mpc_3dlut(
struct dc *dc, bool acquire,
struct dc_stream_state *stream,
@@ -1904,7 +1897,7 @@ bool dc_acquire_release_mpc_3dlut(
}
return ret;
}
-#endif
+
static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
{
int i;
@@ -1925,7 +1918,6 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
return false;
}
-#ifdef CONFIG_DRM_AMD_DC_DCN
/* Perform updates here which need to be deferred until next vupdate
*
* i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
@@ -1944,7 +1936,6 @@ static void process_deferred_updates(struct dc *dc)
dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
}
}
-#endif /* CONFIG_DRM_AMD_DC_DCN */
void dc_post_update_surfaces_to_stream(struct dc *dc)
{
@@ -1971,9 +1962,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
}
-#ifdef CONFIG_DRM_AMD_DC_DCN
process_deferred_updates(dc);
-#endif
dc->hwss.optimize_bandwidth(dc, context);
@@ -1987,9 +1976,7 @@ static void init_state(struct dc *dc, struct dc_state *context)
* initialize and obtain IP and SOC the base DML instance from DC is
* initially copied into every context
*/
-#ifdef CONFIG_DRM_AMD_DC_DCN
memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
-#endif
}
struct dc_state *dc_create_state(struct dc *dc)
@@ -2361,11 +2348,9 @@ static enum surface_update_type check_update_surfaces_for_stream(
int i;
enum surface_update_type overall_type = UPDATE_TYPE_FAST;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dc->idle_optimizations_allowed)
overall_type = UPDATE_TYPE_FULL;
-#endif
if (stream_status == NULL || stream_status->plane_count != surface_count)
overall_type = UPDATE_TYPE_FULL;
@@ -2874,10 +2859,8 @@ static void commit_planes_for_stream(struct dc *dc,
}
if (update_type == UPDATE_TYPE_FULL) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_allow_idle_optimizations(dc, false);
-#endif
if (get_seamless_boot_stream_count(context) == 0)
dc->hwss.prepare_bandwidth(dc, context);
@@ -2895,7 +2878,6 @@ static void commit_planes_for_stream(struct dc *dc,
}
}
-#ifdef CONFIG_DRM_AMD_DC_DCN
if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
struct pipe_ctx *mpcc_pipe;
struct pipe_ctx *odm_pipe;
@@ -2904,7 +2886,6 @@ static void commit_planes_for_stream(struct dc *dc,
for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
}
-#endif
if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
if (top_pipe_to_program &&
@@ -3014,7 +2995,6 @@ static void commit_planes_for_stream(struct dc *dc,
}
if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
dc->hwss.program_front_end_for_ctx(dc, context);
-#ifdef CONFIG_DRM_AMD_DC_DCN
if (dc->debug.validate_dml_output) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
@@ -3028,7 +3008,6 @@ static void commit_planes_for_stream(struct dc *dc,
&context->res_ctx.pipe_ctx[i].ttu_regs);
}
}
-#endif
}
// Update Type FAST, Surface updates
@@ -3583,8 +3562,6 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)
return true;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-
void dc_allow_idle_optimizations(struct dc *dc, bool allow)
{
if (dc->debug.disable_idle_power_optimizations)
@@ -3740,7 +3717,6 @@ void dc_hardware_release(struct dc *dc)
if (dc->hwss.hardware_release)
dc->hwss.hardware_release(dc);
}
-#endif
/*
*****************************************************************************
@@ -3760,13 +3736,12 @@ void dc_hardware_release(struct dc *dc)
*/
bool dc_is_dmub_outbox_supported(struct dc *dc)
{
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- /* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */
+ /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
!dc->debug.dpia_debug.bits.disable_dpia)
return true;
-#endif
+
/* dmub aux needs dmub notifications to be enabled */
return dc->debug.enable_dmub_aux_for_legacy_ddc;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 643762542e4d..72376075db0c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -345,7 +345,6 @@ void context_clock_trace(
struct dc *dc,
struct dc_state *context)
{
-#if defined(CONFIG_DRM_AMD_DC_DCN)
DC_LOGGER_INIT(dc->ctx->logger);
CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
@@ -363,7 +362,6 @@ void context_clock_trace(
context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
context->bw_ctx.bw.dcn.clk.fclk_khz,
context->bw_ctx.bw.dcn.clk.socclk_khz);
-#endif
}
/**
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 07f154fc4e56..9529b924742e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -804,7 +804,6 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
{
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
* reports DSC support.
*/
@@ -815,7 +814,6 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
link->wa_flags.dpia_mst_dsc_always_on = true;
-#endif
}
static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 5e49e346aa06..975d631534b5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5127,12 +5127,10 @@ void dp_retrieve_lttpr_cap(struct dc_link *link)
else
link->lttpr_support = LTTPR_CHECK_EXT_SUPPORT;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Check DP tunnel LTTPR mode debug option. */
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
link->dc->debug.dpia_debug.bits.force_non_lttpr)
link->lttpr_support = LTTPR_UNSUPPORTED;
-#endif
if (link->lttpr_support > LTTPR_UNSUPPORTED) {
/* By reading LTTPR capability, RX assumes that we will enable
@@ -5626,9 +5624,7 @@ static bool retrieve_link_cap(struct dc_link *link)
* only if required.
*/
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
-#if defined(CONFIG_DRM_AMD_DC_DCN)
!link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around &&
-#endif
link->dpcd_caps.is_branch_dev &&
link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
index 0e95bc5df4e7..a5765f36d86f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
@@ -547,11 +547,9 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link,
dp_translate_training_aux_read_interval(
link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Check debug option for extending aux read interval. */
if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
-#endif
return wait_time_microsec;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 147c6a3c6312..f702919a2279 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -56,7 +56,6 @@
#include "dce110/dce110_resource.h"
#include "dce112/dce112_resource.h"
#include "dce120/dce120_resource.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dcn10/dcn10_resource.h"
#include "dcn20/dcn20_resource.h"
#include "dcn21/dcn21_resource.h"
@@ -68,7 +67,6 @@
#include "dcn31/dcn31_resource.h"
#include "dcn315/dcn315_resource.h"
#include "dcn316/dcn316_resource.h"
-#endif
#define DC_LOGGER_INIT(logger)
@@ -124,7 +122,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
else
dc_version = DCE_VERSION_12_0;
break;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
case FAMILY_RV:
dc_version = DCN_VERSION_1_0;
if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
@@ -165,7 +162,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_3_16;
break;
-#endif
default:
dc_version = DCE_VERSION_UNKNOWN;
@@ -397,7 +393,6 @@ bool resource_construct(
}
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
for (i = 0; i < caps->num_mpc_3dlut; i++) {
pool->mpc_lut[i] = dc_create_3dlut_func();
if (pool->mpc_lut[i] == NULL)
@@ -406,7 +401,7 @@ bool resource_construct(
if (pool->mpc_shaper[i] == NULL)
DC_ERR("DC: failed to create MPC shaper!\n");
}
-#endif
+
dc->caps.dynamic_audio = false;
if (pool->audio_count < pool->stream_enc_count) {
dc->caps.dynamic_audio = true;
@@ -1369,7 +1364,6 @@ static struct pipe_ctx *acquire_free_pipe_for_head(
return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
static int acquire_first_split_pipe(
struct resource_context *res_ctx,
const struct resource_pool *pool,
@@ -1404,7 +1398,6 @@ static int acquire_first_split_pipe(
}
return -1;
}
-#endif
bool dc_add_plane_to_context(
const struct dc *dc,
@@ -1447,13 +1440,12 @@ bool dc_add_plane_to_context(
while (head_pipe) {
free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
- #if defined(CONFIG_DRM_AMD_DC_DCN)
if (!free_pipe) {
int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
if (pipe_idx >= 0)
free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
}
- #endif
+
if (!free_pipe) {
dc_plane_state_release(plane_state);
return false;
@@ -2259,10 +2251,8 @@ enum dc_status resource_map_pool_resources(
/* acquire new resources */
pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
-#ifdef CONFIG_DRM_AMD_DC_DCN
if (pipe_idx < 0)
pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
-#endif
if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
return DC_NO_CONTROLLER_RESOURCE;
@@ -2453,7 +2443,6 @@ enum dc_status dc_validate_global_state(
if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
result = DC_FAIL_BANDWIDTH_VALIDATE;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/*
* Only update link encoder to stream assignment after bandwidth validation passed.
* TODO: Split out assignment and validation.
@@ -2461,7 +2450,6 @@ enum dc_status dc_validate_global_state(
if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
dc->res_pool->funcs->link_encs_assign(
dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
-#endif
return result;
}
@@ -3189,10 +3177,8 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-#if defined(CONFIG_DRM_AMD_DC_DCN)
case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
-#endif
return 32;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
@@ -3345,7 +3331,6 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
/* TODO - get transmitter to phy idx mapping from DMUB */
uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
switch (transmitter) {
@@ -3369,7 +3354,7 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
break;
}
}
-#endif
+
return phy_idx;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index c4e871f358ab..acca35d86c10 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -314,9 +314,7 @@ bool dc_stream_set_cursor_attributes(
const struct dc_cursor_attributes *attributes)
{
struct dc *dc;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool reset_idle_optimizations = false;
-#endif
if (NULL == stream) {
dm_error("DC: dc_stream is NULL!\n");
@@ -346,12 +344,10 @@ bool dc_stream_set_cursor_attributes(
#endif
program_cursor_attributes(dc, stream, attributes);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* re-enable idle optimizations if necessary */
if (reset_idle_optimizations)
dc_allow_idle_optimizations(dc, true);
-#endif
return true;
}
@@ -396,9 +392,7 @@ bool dc_stream_set_cursor_position(
const struct dc_cursor_position *position)
{
struct dc *dc;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool reset_idle_optimizations = false;
-#endif
if (NULL == stream) {
dm_error("DC: dc_stream is NULL!\n");
@@ -424,12 +418,10 @@ bool dc_stream_set_cursor_position(
stream->cursor_position = *position;
program_cursor_position(dc, stream, position);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* re-enable idle optimizations if necessary */
if (reset_idle_optimizations)
dc_allow_idle_optimizations(dc, true);
-#endif
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e37d9c19f089..0f86bb809e04 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -222,7 +222,6 @@ struct dc_dcc_setting {
unsigned int max_compressed_blk_size;
unsigned int max_uncompressed_blk_size;
bool independent_64b_blks;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
//These bitfields to be used starting with DCN
struct {
uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
@@ -230,7 +229,6 @@ struct dc_dcc_setting {
uint32_t dcc_256_128_128 : 1; //available starting with DCN
uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
} dcc_controls;
-#endif
};
struct dc_surface_dcc_cap {
@@ -332,9 +330,7 @@ struct dc_config {
bool enable_4to1MPC;
bool enable_windowed_mpo_odm;
bool allow_edp_hotplug_detection;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool clamp_min_dcfclk;
-#endif
uint64_t vblank_alignment_dto_params;
uint8_t vblank_alignment_max_frame_time_diff;
bool is_asymmetric_memory;
@@ -395,14 +391,12 @@ enum dcn_pwr_state {
DCN_PWR_STATE_LOW_POWER = 3,
};
-#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dcn_zstate_support_state {
DCN_ZSTATE_SUPPORT_UNKNOWN,
DCN_ZSTATE_SUPPORT_ALLOW,
DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
DCN_ZSTATE_SUPPORT_DISALLOW,
};
-#endif
/*
* For any clocks that may differ per pipe
* only the max is stored in this structure
@@ -420,10 +414,8 @@ struct dc_clocks {
int phyclk_khz;
int dramclk_khz;
bool p_state_change_support;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dcn_zstate_support_state zstate_support;
bool dtbclk_en;
-#endif
enum dcn_pwr_state pwr_state;
/*
* Elements below are not compared for the purposes of
@@ -653,9 +645,7 @@ struct dc_debug_options {
bool disable_pplib_clock_request;
bool disable_clock_gate;
bool disable_mem_low_power;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool pstate_enabled;
-#endif
bool disable_dmcu;
bool disable_psr;
bool force_abm_enable;
@@ -673,20 +663,16 @@ struct dc_debug_options {
bool remove_disconnect_edp;
unsigned int force_odm_combine; //bit vector based on otg inst
unsigned int seamless_boot_odm_combine;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
unsigned int force_odm_combine_4to1; //bit vector based on otg inst
bool disable_z9_mpc;
-#endif
unsigned int force_fclk_khz;
bool enable_tri_buf;
bool dmub_offload_enabled;
bool dmcub_emulation;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool disable_idle_power_optimizations;
unsigned int mall_size_override;
unsigned int mall_additional_timer_percent;
bool mall_error_as_fatal;
-#endif
bool dmub_command_table; /* for testing only */
struct dc_bw_validation_profile bw_val_profile;
bool disable_fec;
@@ -695,9 +681,7 @@ struct dc_debug_options {
* watermarks are not affected.
*/
unsigned int force_min_dcfclk_mhz;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
int dwb_fi_phase;
-#endif
bool disable_timing_sync;
bool cm_in_bypass;
int force_clock_mode;/*every mode change.*/
@@ -729,11 +713,9 @@ struct dc_debug_options {
enum det_size crb_alloc_policy;
int crb_alloc_policy_min_disp_count;
bool disable_z10;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool enable_z9_disable_interface;
bool enable_sw_cntl_psr;
union dpia_debug_options dpia_debug;
-#endif
bool apply_vendor_specific_lttpr_wa;
bool extended_blank_optimization;
union aux_wake_wa_options aux_wake_wa;
@@ -767,11 +749,9 @@ struct dc {
/* Inputs into BW and WM calculations. */
struct bw_calcs_dceip *bw_dceip;
struct bw_calcs_vbios *bw_vbios;
-#ifdef CONFIG_DRM_AMD_DC_DCN
struct dcn_soc_bounding_box *dcn_soc;
struct dcn_ip_params *dcn_ip;
struct display_mode_lib dml;
-#endif
/* HW functions */
struct hw_sequencer_funcs hwss;
@@ -780,12 +760,8 @@ struct dc {
/* Require to optimize clocks and bandwidth for added/removed planes */
bool optimized_required;
bool wm_optimized_required;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool idle_optimizations_allowed;
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool enable_c20_dtm_b0;
-#endif
/* Require to maintain clocks and bandwidth for UEFI enabled HW */
@@ -835,9 +811,7 @@ struct dc_init_data {
uint64_t log_mask;
struct dpcd_vendor_signature vendor_signature;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool force_smu_not_present;
-#endif
};
struct dc_callback_init {
@@ -1030,9 +1004,7 @@ struct dc_plane_state {
struct dc_transfer_func *in_shaper_func;
struct dc_transfer_func *blend_tf;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
struct dc_transfer_func *gamcor_tf;
-#endif
enum surface_pixel_format format;
enum dc_rotation_angle rotation;
enum plane_stereo_format stereo_format;
@@ -1169,13 +1141,11 @@ void dc_resource_state_construct(
const struct dc *dc,
struct dc_state *dst_ctx);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dc_acquire_release_mpc_3dlut(
struct dc *dc, bool acquire,
struct dc_stream_state *stream,
struct dc_3dlut **lut,
struct dc_transfer_func **shaper);
-#endif
void dc_resource_state_copy_construct(
const struct dc_state *src_ctx,
@@ -1306,10 +1276,8 @@ struct hdcp_caps {
#include "dc_link.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN)
uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
-#endif
/*******************************************************************************
* Sink Interfaces - A sink corresponds to a display output device
******************************************************************************/
@@ -1433,7 +1401,6 @@ bool dc_is_dmcu_initialized(struct dc *dc);
enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
struct dc_cursor_attributes *cursor_attr);
@@ -1458,13 +1425,9 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
/* cleanup on driver unload */
void dc_hardware_release(struct dc *dc);
-#endif
-
bool dc_set_psr_allow_active(struct dc *dc, bool enable);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
void dc_z10_restore(const struct dc *dc);
void dc_z10_save_init(struct dc *dc);
-#endif
bool dc_is_dmub_outbox_supported(struct dc *dc);
bool dc_enable_dmub_notifications(struct dc *dc);
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index 31109db02e93..fb6a2d7b6470 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -160,9 +160,7 @@ void dm_set_dcn_clocks(
struct dc_context *ctx,
struct dc_clocks *clks);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable);
-#endif
void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 951c9b60917d..26f3a55c35d7 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -33,9 +33,7 @@
#include "dc_bios_types.h"
#include "mem_input.h"
#include "hubp.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "mpc.h"
-#endif
#include "dwb.h"
#include "mcif_wb.h"
#include "panel_cntl.h"
@@ -181,7 +179,6 @@ struct resource_funcs {
void (*update_bw_bounding_box)(
struct dc *dc,
struct clk_bw_params *bw_params);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool (*acquire_post_bldn_3dlut)(
struct resource_context *res_ctx,
const struct resource_pool *pool,
@@ -194,7 +191,7 @@ struct resource_funcs {
const struct resource_pool *pool,
struct dc_3dlut **lut,
struct dc_transfer_func **shaper);
-#endif
+
enum dc_status (*add_dsc_to_stream_resource)(
struct dc *dc, struct dc_state *state,
struct dc_stream_state *stream);
@@ -254,10 +251,9 @@ struct resource_pool {
struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
unsigned int hpo_dp_link_enc_count;
struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
-#if defined(CONFIG_DRM_AMD_DC_DCN)
struct dc_3dlut *mpc_lut[MAX_PIPES];
struct dc_transfer_func *mpc_shaper[MAX_PIPES];
-#endif
+
struct {
unsigned int xtalin_clock_inKhz;
unsigned int dccg_ref_clock_inKhz;
@@ -286,9 +282,7 @@ struct resource_pool {
struct dmcu *dmcu;
struct dmub_psr *psr;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
struct abm *multiple_abms[MAX_PIPES];
-#endif
const struct resource_funcs *funcs;
const struct resource_caps *res_cap;
@@ -380,7 +374,6 @@ struct pipe_ctx {
struct pipe_ctx *next_odm_pipe;
struct pipe_ctx *prev_odm_pipe;
-#ifdef CONFIG_DRM_AMD_DC_DCN
struct _vcs_dpi_display_dlg_regs_st dlg_regs;
struct _vcs_dpi_display_ttu_regs_st ttu_regs;
struct _vcs_dpi_display_rq_regs_st rq_regs;
@@ -390,7 +383,7 @@ struct pipe_ctx {
struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
int det_buffer_size_kb;
bool unbounded_req;
-#endif
+
union pipe_update_flags update_flags;
struct dwbc *dwbc;
struct mcif_wb *mcif_wb;
@@ -419,9 +412,7 @@ struct resource_context {
bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool is_mpc_3dlut_acquired[MAX_PIPES];
-#endif
};
struct dce_bw_output {
@@ -484,9 +475,7 @@ struct dc_state {
/* Note: these are big structures, do *not* put on stack! */
struct dm_pp_display_configuration pp_display_cfg;
-#ifdef CONFIG_DRM_AMD_DC_DCN
struct dcn_bw_internal_vars dcn_bw_vars;
-#endif
struct clk_mgr *clk_mgr;
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
2022-05-06 15:42 ` [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc Stylon Wang
@ 2022-05-06 15:56 ` Alex Deucher
2022-05-06 17:12 ` Rodrigo Siqueira Jordao
0 siblings, 1 reply; 29+ messages in thread
From: Alex Deucher @ 2022-05-06 15:56 UTC (permalink / raw)
To: Stylon Wang
Cc: Leo (Sunpeng) Li, Bhawanpreet Lakha, Qingqing Zhuo, Siqueira,
Rodrigo, Roman Li, amd-gfx list, Solomon Chiu, Aurabindo Pillai,
Alex Hung, Wayne Lin, Wentland, Harry, Gutierrez, Agustin,
Kotarac, Pavle
On Fri, May 6, 2022 at 11:43 AM Stylon Wang <stylon.wang@amd.com> wrote:
>
> From: Alex Hung <alex.hung@amd.com>
>
> [Why & How]
> CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
> code should be OS-agnostic.
>
> This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
> in dc and dc/core directories.
>
> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> Acked-by: Stylon Wang <stylon.wang@amd.com>
> Signed-off-by: Alex Hung <alex.hung@amd.com>
I presume the driver still builds properly on configs where
CONFIG_DRM_AMD_DC_DCN is not set? E.g., platforms without floating
point for example?
Alex
> ---
> drivers/gpu/drm/amd/display/dc/Makefile | 2 -
> .../display/dc/bios/command_table_helper2.c | 3 +-
> drivers/gpu/drm/amd/display/dc/core/dc.c | 31 ++--------------
> .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 -
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -
> .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 --
> .../drm/amd/display/dc/core/dc_link_dpia.c | 2 -
> .../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ++---------
> .../gpu/drm/amd/display/dc/core/dc_stream.c | 8 ----
> drivers/gpu/drm/amd/display/dc/dc.h | 37 -------------------
> drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 -
> .../gpu/drm/amd/display/dc/inc/core_types.h | 17 ++-------
> 12 files changed, 10 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
> index f05ab2bf20c5..b4eca0236435 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -63,9 +63,7 @@ DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink
> dc_surface.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
> dc_link_enc_cfg.o dc_link_dpia.o dc_link_dpcd.o
>
> -ifdef CONFIG_DRM_AMD_DC_DCN
> DISPLAY_CORE += dc_vm_helper.o
> -endif
>
> AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> index dd9704ef4ccc..f3792286f571 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> @@ -65,7 +65,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> case DCE_VERSION_12_1:
> *h = dal_cmd_tbl_helper_dce112_get_table2();
> return true;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> case DCN_VERSION_1_0:
> case DCN_VERSION_1_01:
> case DCN_VERSION_2_0:
> @@ -80,7 +79,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> case DCN_VERSION_3_16:
> *h = dal_cmd_tbl_helper_dce112_get_table2();
> return true;
> -#endif
> +
> default:
> /* Unsupported DCE */
> BREAK_TO_DEBUGGER();
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index c2fcd67bcc4d..1eeea7c184ae 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -829,14 +829,12 @@ static void dc_destruct(struct dc *dc)
> kfree(dc->bw_dceip);
> dc->bw_dceip = NULL;
>
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> kfree(dc->dcn_soc);
> dc->dcn_soc = NULL;
>
> kfree(dc->dcn_ip);
> dc->dcn_ip = NULL;
>
> -#endif
> kfree(dc->vm_helper);
> dc->vm_helper = NULL;
>
> @@ -882,10 +880,8 @@ static bool dc_construct(struct dc *dc,
> struct dc_context *dc_ctx;
> struct bw_calcs_dceip *dc_dceip;
> struct bw_calcs_vbios *dc_vbios;
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> struct dcn_soc_bounding_box *dcn_soc;
> struct dcn_ip_params *dcn_ip;
> -#endif
>
> dc->config = init_params->flags;
>
> @@ -913,7 +909,6 @@ static bool dc_construct(struct dc *dc,
> }
>
> dc->bw_vbios = dc_vbios;
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
> if (!dcn_soc) {
> dm_error("%s: failed to create dcn_soc\n", __func__);
> @@ -929,7 +924,6 @@ static bool dc_construct(struct dc *dc,
> }
>
> dc->dcn_ip = dcn_ip;
> -#endif
>
> if (!dc_construct_ctx(dc, init_params)) {
> dm_error("%s: failed to create ctx\n", __func__);
> @@ -1868,7 +1862,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
> return (result == DC_OK);
> }
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool dc_acquire_release_mpc_3dlut(
> struct dc *dc, bool acquire,
> struct dc_stream_state *stream,
> @@ -1904,7 +1897,7 @@ bool dc_acquire_release_mpc_3dlut(
> }
> return ret;
> }
> -#endif
> +
> static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
> {
> int i;
> @@ -1925,7 +1918,6 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
> return false;
> }
>
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> /* Perform updates here which need to be deferred until next vupdate
> *
> * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
> @@ -1944,7 +1936,6 @@ static void process_deferred_updates(struct dc *dc)
> dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
> }
> }
> -#endif /* CONFIG_DRM_AMD_DC_DCN */
>
> void dc_post_update_surfaces_to_stream(struct dc *dc)
> {
> @@ -1971,9 +1962,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
> dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
> }
>
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> process_deferred_updates(dc);
> -#endif
>
> dc->hwss.optimize_bandwidth(dc, context);
>
> @@ -1987,9 +1976,7 @@ static void init_state(struct dc *dc, struct dc_state *context)
> * initialize and obtain IP and SOC the base DML instance from DC is
> * initially copied into every context
> */
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
> -#endif
> }
>
> struct dc_state *dc_create_state(struct dc *dc)
> @@ -2361,11 +2348,9 @@ static enum surface_update_type check_update_surfaces_for_stream(
> int i;
> enum surface_update_type overall_type = UPDATE_TYPE_FAST;
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> if (dc->idle_optimizations_allowed)
> overall_type = UPDATE_TYPE_FULL;
>
> -#endif
> if (stream_status == NULL || stream_status->plane_count != surface_count)
> overall_type = UPDATE_TYPE_FULL;
>
> @@ -2874,10 +2859,8 @@ static void commit_planes_for_stream(struct dc *dc,
> }
>
> if (update_type == UPDATE_TYPE_FULL) {
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> dc_allow_idle_optimizations(dc, false);
>
> -#endif
> if (get_seamless_boot_stream_count(context) == 0)
> dc->hwss.prepare_bandwidth(dc, context);
>
> @@ -2895,7 +2878,6 @@ static void commit_planes_for_stream(struct dc *dc,
> }
> }
>
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
> struct pipe_ctx *mpcc_pipe;
> struct pipe_ctx *odm_pipe;
> @@ -2904,7 +2886,6 @@ static void commit_planes_for_stream(struct dc *dc,
> for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
> odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
> }
> -#endif
>
> if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
> if (top_pipe_to_program &&
> @@ -3014,7 +2995,6 @@ static void commit_planes_for_stream(struct dc *dc,
> }
> if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
> dc->hwss.program_front_end_for_ctx(dc, context);
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> if (dc->debug.validate_dml_output) {
> for (i = 0; i < dc->res_pool->pipe_count; i++) {
> struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
> @@ -3028,7 +3008,6 @@ static void commit_planes_for_stream(struct dc *dc,
> &context->res_ctx.pipe_ctx[i].ttu_regs);
> }
> }
> -#endif
> }
>
> // Update Type FAST, Surface updates
> @@ -3583,8 +3562,6 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)
> return true;
> }
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> -
> void dc_allow_idle_optimizations(struct dc *dc, bool allow)
> {
> if (dc->debug.disable_idle_power_optimizations)
> @@ -3740,7 +3717,6 @@ void dc_hardware_release(struct dc *dc)
> if (dc->hwss.hardware_release)
> dc->hwss.hardware_release(dc);
> }
> -#endif
>
> /*
> *****************************************************************************
> @@ -3760,13 +3736,12 @@ void dc_hardware_release(struct dc *dc)
> */
> bool dc_is_dmub_outbox_supported(struct dc *dc)
> {
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> - /* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */
> + /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
> if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
> !dc->debug.dpia_debug.bits.disable_dpia)
> return true;
> -#endif
> +
> /* dmub aux needs dmub notifications to be enabled */
> return dc->debug.enable_dmub_aux_for_legacy_ddc;
> }
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
> index 643762542e4d..72376075db0c 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
> @@ -345,7 +345,6 @@ void context_clock_trace(
> struct dc *dc,
> struct dc_state *context)
> {
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> DC_LOGGER_INIT(dc->ctx->logger);
> CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
> "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
> @@ -363,7 +362,6 @@ void context_clock_trace(
> context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
> context->bw_ctx.bw.dcn.clk.fclk_khz,
> context->bw_ctx.bw.dcn.clk.socclk_khz);
> -#endif
> }
>
> /**
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index 07f154fc4e56..9529b924742e 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -804,7 +804,6 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
>
> static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
> {
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
> * reports DSC support.
> */
> @@ -815,7 +814,6 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
> link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
> !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
> link->wa_flags.dpia_mst_dsc_always_on = true;
> -#endif
> }
>
> static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 5e49e346aa06..975d631534b5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -5127,12 +5127,10 @@ void dp_retrieve_lttpr_cap(struct dc_link *link)
> else
> link->lttpr_support = LTTPR_CHECK_EXT_SUPPORT;
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> /* Check DP tunnel LTTPR mode debug option. */
> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
> link->dc->debug.dpia_debug.bits.force_non_lttpr)
> link->lttpr_support = LTTPR_UNSUPPORTED;
> -#endif
>
> if (link->lttpr_support > LTTPR_UNSUPPORTED) {
> /* By reading LTTPR capability, RX assumes that we will enable
> @@ -5626,9 +5624,7 @@ static bool retrieve_link_cap(struct dc_link *link)
> * only if required.
> */
> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> !link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around &&
> -#endif
> link->dpcd_caps.is_branch_dev &&
> link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
> link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
> index 0e95bc5df4e7..a5765f36d86f 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
> @@ -547,11 +547,9 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link,
> dp_translate_training_aux_read_interval(
> link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> /* Check debug option for extending aux read interval. */
> if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
> wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
> -#endif
>
> return wait_time_microsec;
> }
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index 147c6a3c6312..f702919a2279 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -56,7 +56,6 @@
> #include "dce110/dce110_resource.h"
> #include "dce112/dce112_resource.h"
> #include "dce120/dce120_resource.h"
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> #include "dcn10/dcn10_resource.h"
> #include "dcn20/dcn20_resource.h"
> #include "dcn21/dcn21_resource.h"
> @@ -68,7 +67,6 @@
> #include "dcn31/dcn31_resource.h"
> #include "dcn315/dcn315_resource.h"
> #include "dcn316/dcn316_resource.h"
> -#endif
>
> #define DC_LOGGER_INIT(logger)
>
> @@ -124,7 +122,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
> else
> dc_version = DCE_VERSION_12_0;
> break;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> case FAMILY_RV:
> dc_version = DCN_VERSION_1_0;
> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
> @@ -165,7 +162,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
> if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
> dc_version = DCN_VERSION_3_16;
> break;
> -#endif
>
> default:
> dc_version = DCE_VERSION_UNKNOWN;
> @@ -397,7 +393,6 @@ bool resource_construct(
> }
> }
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> for (i = 0; i < caps->num_mpc_3dlut; i++) {
> pool->mpc_lut[i] = dc_create_3dlut_func();
> if (pool->mpc_lut[i] == NULL)
> @@ -406,7 +401,7 @@ bool resource_construct(
> if (pool->mpc_shaper[i] == NULL)
> DC_ERR("DC: failed to create MPC shaper!\n");
> }
> -#endif
> +
> dc->caps.dynamic_audio = false;
> if (pool->audio_count < pool->stream_enc_count) {
> dc->caps.dynamic_audio = true;
> @@ -1369,7 +1364,6 @@ static struct pipe_ctx *acquire_free_pipe_for_head(
> return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
> }
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> static int acquire_first_split_pipe(
> struct resource_context *res_ctx,
> const struct resource_pool *pool,
> @@ -1404,7 +1398,6 @@ static int acquire_first_split_pipe(
> }
> return -1;
> }
> -#endif
>
> bool dc_add_plane_to_context(
> const struct dc *dc,
> @@ -1447,13 +1440,12 @@ bool dc_add_plane_to_context(
> while (head_pipe) {
> free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
>
> - #if defined(CONFIG_DRM_AMD_DC_DCN)
> if (!free_pipe) {
> int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
> if (pipe_idx >= 0)
> free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
> }
> - #endif
> +
> if (!free_pipe) {
> dc_plane_state_release(plane_state);
> return false;
> @@ -2259,10 +2251,8 @@ enum dc_status resource_map_pool_resources(
> /* acquire new resources */
> pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
>
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> if (pipe_idx < 0)
> pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
> -#endif
>
> if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
> return DC_NO_CONTROLLER_RESOURCE;
> @@ -2453,7 +2443,6 @@ enum dc_status dc_validate_global_state(
> if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
> result = DC_FAIL_BANDWIDTH_VALIDATE;
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> /*
> * Only update link encoder to stream assignment after bandwidth validation passed.
> * TODO: Split out assignment and validation.
> @@ -2461,7 +2450,6 @@ enum dc_status dc_validate_global_state(
> if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
> dc->res_pool->funcs->link_encs_assign(
> dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
> -#endif
>
> return result;
> }
> @@ -3189,10 +3177,8 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
> case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
> case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
> -#endif
> return 32;
> case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
> case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
> @@ -3345,7 +3331,6 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
> /* TODO - get transmitter to phy idx mapping from DMUB */
> uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
> switch (transmitter) {
> @@ -3369,7 +3354,7 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
> break;
> }
> }
> -#endif
> +
> return phy_idx;
> }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> index c4e871f358ab..acca35d86c10 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> @@ -314,9 +314,7 @@ bool dc_stream_set_cursor_attributes(
> const struct dc_cursor_attributes *attributes)
> {
> struct dc *dc;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool reset_idle_optimizations = false;
> -#endif
>
> if (NULL == stream) {
> dm_error("DC: dc_stream is NULL!\n");
> @@ -346,12 +344,10 @@ bool dc_stream_set_cursor_attributes(
> #endif
> program_cursor_attributes(dc, stream, attributes);
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> /* re-enable idle optimizations if necessary */
> if (reset_idle_optimizations)
> dc_allow_idle_optimizations(dc, true);
>
> -#endif
> return true;
> }
>
> @@ -396,9 +392,7 @@ bool dc_stream_set_cursor_position(
> const struct dc_cursor_position *position)
> {
> struct dc *dc;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool reset_idle_optimizations = false;
> -#endif
>
> if (NULL == stream) {
> dm_error("DC: dc_stream is NULL!\n");
> @@ -424,12 +418,10 @@ bool dc_stream_set_cursor_position(
> stream->cursor_position = *position;
>
> program_cursor_position(dc, stream, position);
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> /* re-enable idle optimizations if necessary */
> if (reset_idle_optimizations)
> dc_allow_idle_optimizations(dc, true);
>
> -#endif
> return true;
> }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
> index e37d9c19f089..0f86bb809e04 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -222,7 +222,6 @@ struct dc_dcc_setting {
> unsigned int max_compressed_blk_size;
> unsigned int max_uncompressed_blk_size;
> bool independent_64b_blks;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> //These bitfields to be used starting with DCN
> struct {
> uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
> @@ -230,7 +229,6 @@ struct dc_dcc_setting {
> uint32_t dcc_256_128_128 : 1; //available starting with DCN
> uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
> } dcc_controls;
> -#endif
> };
>
> struct dc_surface_dcc_cap {
> @@ -332,9 +330,7 @@ struct dc_config {
> bool enable_4to1MPC;
> bool enable_windowed_mpo_odm;
> bool allow_edp_hotplug_detection;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool clamp_min_dcfclk;
> -#endif
> uint64_t vblank_alignment_dto_params;
> uint8_t vblank_alignment_max_frame_time_diff;
> bool is_asymmetric_memory;
> @@ -395,14 +391,12 @@ enum dcn_pwr_state {
> DCN_PWR_STATE_LOW_POWER = 3,
> };
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> enum dcn_zstate_support_state {
> DCN_ZSTATE_SUPPORT_UNKNOWN,
> DCN_ZSTATE_SUPPORT_ALLOW,
> DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
> DCN_ZSTATE_SUPPORT_DISALLOW,
> };
> -#endif
> /*
> * For any clocks that may differ per pipe
> * only the max is stored in this structure
> @@ -420,10 +414,8 @@ struct dc_clocks {
> int phyclk_khz;
> int dramclk_khz;
> bool p_state_change_support;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> enum dcn_zstate_support_state zstate_support;
> bool dtbclk_en;
> -#endif
> enum dcn_pwr_state pwr_state;
> /*
> * Elements below are not compared for the purposes of
> @@ -653,9 +645,7 @@ struct dc_debug_options {
> bool disable_pplib_clock_request;
> bool disable_clock_gate;
> bool disable_mem_low_power;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool pstate_enabled;
> -#endif
> bool disable_dmcu;
> bool disable_psr;
> bool force_abm_enable;
> @@ -673,20 +663,16 @@ struct dc_debug_options {
> bool remove_disconnect_edp;
> unsigned int force_odm_combine; //bit vector based on otg inst
> unsigned int seamless_boot_odm_combine;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> unsigned int force_odm_combine_4to1; //bit vector based on otg inst
> bool disable_z9_mpc;
> -#endif
> unsigned int force_fclk_khz;
> bool enable_tri_buf;
> bool dmub_offload_enabled;
> bool dmcub_emulation;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool disable_idle_power_optimizations;
> unsigned int mall_size_override;
> unsigned int mall_additional_timer_percent;
> bool mall_error_as_fatal;
> -#endif
> bool dmub_command_table; /* for testing only */
> struct dc_bw_validation_profile bw_val_profile;
> bool disable_fec;
> @@ -695,9 +681,7 @@ struct dc_debug_options {
> * watermarks are not affected.
> */
> unsigned int force_min_dcfclk_mhz;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> int dwb_fi_phase;
> -#endif
> bool disable_timing_sync;
> bool cm_in_bypass;
> int force_clock_mode;/*every mode change.*/
> @@ -729,11 +713,9 @@ struct dc_debug_options {
> enum det_size crb_alloc_policy;
> int crb_alloc_policy_min_disp_count;
> bool disable_z10;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool enable_z9_disable_interface;
> bool enable_sw_cntl_psr;
> union dpia_debug_options dpia_debug;
> -#endif
> bool apply_vendor_specific_lttpr_wa;
> bool extended_blank_optimization;
> union aux_wake_wa_options aux_wake_wa;
> @@ -767,11 +749,9 @@ struct dc {
> /* Inputs into BW and WM calculations. */
> struct bw_calcs_dceip *bw_dceip;
> struct bw_calcs_vbios *bw_vbios;
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> struct dcn_soc_bounding_box *dcn_soc;
> struct dcn_ip_params *dcn_ip;
> struct display_mode_lib dml;
> -#endif
>
> /* HW functions */
> struct hw_sequencer_funcs hwss;
> @@ -780,12 +760,8 @@ struct dc {
> /* Require to optimize clocks and bandwidth for added/removed planes */
> bool optimized_required;
> bool wm_optimized_required;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool idle_optimizations_allowed;
> -#endif
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool enable_c20_dtm_b0;
> -#endif
>
> /* Require to maintain clocks and bandwidth for UEFI enabled HW */
>
> @@ -835,9 +811,7 @@ struct dc_init_data {
> uint64_t log_mask;
>
> struct dpcd_vendor_signature vendor_signature;
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool force_smu_not_present;
> -#endif
> };
>
> struct dc_callback_init {
> @@ -1030,9 +1004,7 @@ struct dc_plane_state {
> struct dc_transfer_func *in_shaper_func;
> struct dc_transfer_func *blend_tf;
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> struct dc_transfer_func *gamcor_tf;
> -#endif
> enum surface_pixel_format format;
> enum dc_rotation_angle rotation;
> enum plane_stereo_format stereo_format;
> @@ -1169,13 +1141,11 @@ void dc_resource_state_construct(
> const struct dc *dc,
> struct dc_state *dst_ctx);
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool dc_acquire_release_mpc_3dlut(
> struct dc *dc, bool acquire,
> struct dc_stream_state *stream,
> struct dc_3dlut **lut,
> struct dc_transfer_func **shaper);
> -#endif
>
> void dc_resource_state_copy_construct(
> const struct dc_state *src_ctx,
> @@ -1306,10 +1276,8 @@ struct hdcp_caps {
>
> #include "dc_link.h"
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
>
> -#endif
> /*******************************************************************************
> * Sink Interfaces - A sink corresponds to a display output device
> ******************************************************************************/
> @@ -1433,7 +1401,6 @@ bool dc_is_dmcu_initialized(struct dc *dc);
>
> enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
> void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>
> bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
> struct dc_cursor_attributes *cursor_attr);
> @@ -1458,13 +1425,9 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
> /* cleanup on driver unload */
> void dc_hardware_release(struct dc *dc);
>
> -#endif
> -
> bool dc_set_psr_allow_active(struct dc *dc, bool enable);
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> void dc_z10_restore(const struct dc *dc);
> void dc_z10_save_init(struct dc *dc);
> -#endif
>
> bool dc_is_dmub_outbox_supported(struct dc *dc);
> bool dc_enable_dmub_notifications(struct dc *dc);
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
> index 31109db02e93..fb6a2d7b6470 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
> @@ -160,9 +160,7 @@ void dm_set_dcn_clocks(
> struct dc_context *ctx,
> struct dc_clocks *clks);
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable);
> -#endif
>
> void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz);
>
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
> index 951c9b60917d..26f3a55c35d7 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
> @@ -33,9 +33,7 @@
> #include "dc_bios_types.h"
> #include "mem_input.h"
> #include "hubp.h"
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> #include "mpc.h"
> -#endif
> #include "dwb.h"
> #include "mcif_wb.h"
> #include "panel_cntl.h"
> @@ -181,7 +179,6 @@ struct resource_funcs {
> void (*update_bw_bounding_box)(
> struct dc *dc,
> struct clk_bw_params *bw_params);
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool (*acquire_post_bldn_3dlut)(
> struct resource_context *res_ctx,
> const struct resource_pool *pool,
> @@ -194,7 +191,7 @@ struct resource_funcs {
> const struct resource_pool *pool,
> struct dc_3dlut **lut,
> struct dc_transfer_func **shaper);
> -#endif
> +
> enum dc_status (*add_dsc_to_stream_resource)(
> struct dc *dc, struct dc_state *state,
> struct dc_stream_state *stream);
> @@ -254,10 +251,9 @@ struct resource_pool {
> struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
> unsigned int hpo_dp_link_enc_count;
> struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> struct dc_3dlut *mpc_lut[MAX_PIPES];
> struct dc_transfer_func *mpc_shaper[MAX_PIPES];
> -#endif
> +
> struct {
> unsigned int xtalin_clock_inKhz;
> unsigned int dccg_ref_clock_inKhz;
> @@ -286,9 +282,7 @@ struct resource_pool {
> struct dmcu *dmcu;
> struct dmub_psr *psr;
>
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> struct abm *multiple_abms[MAX_PIPES];
> -#endif
>
> const struct resource_funcs *funcs;
> const struct resource_caps *res_cap;
> @@ -380,7 +374,6 @@ struct pipe_ctx {
> struct pipe_ctx *next_odm_pipe;
> struct pipe_ctx *prev_odm_pipe;
>
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> struct _vcs_dpi_display_dlg_regs_st dlg_regs;
> struct _vcs_dpi_display_ttu_regs_st ttu_regs;
> struct _vcs_dpi_display_rq_regs_st rq_regs;
> @@ -390,7 +383,7 @@ struct pipe_ctx {
> struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
> int det_buffer_size_kb;
> bool unbounded_req;
> -#endif
> +
> union pipe_update_flags update_flags;
> struct dwbc *dwbc;
> struct mcif_wb *mcif_wb;
> @@ -419,9 +412,7 @@ struct resource_context {
> bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
> unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
> int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> bool is_mpc_3dlut_acquired[MAX_PIPES];
> -#endif
> };
>
> struct dce_bw_output {
> @@ -484,9 +475,7 @@ struct dc_state {
>
> /* Note: these are big structures, do *not* put on stack! */
> struct dm_pp_display_configuration pp_display_cfg;
> -#ifdef CONFIG_DRM_AMD_DC_DCN
> struct dcn_bw_internal_vars dcn_bw_vars;
> -#endif
>
> struct clk_mgr *clk_mgr;
>
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
2022-05-06 15:56 ` Alex Deucher
@ 2022-05-06 17:12 ` Rodrigo Siqueira Jordao
2022-05-06 18:00 ` Alex Deucher
2022-05-07 7:39 ` Cui, Flora
0 siblings, 2 replies; 29+ messages in thread
From: Rodrigo Siqueira Jordao @ 2022-05-06 17:12 UTC (permalink / raw)
To: Alex Deucher, Alex Hung, Stylon Wang
Cc: Leo (Sunpeng) Li, Bhawanpreet Lakha, Qingqing Zhuo, Roman Li,
amd-gfx list, Solomon Chiu, Aurabindo Pillai, Wayne Lin,
Wentland, Harry, Gutierrez, Agustin, Kotarac, Pavle
On 2022-05-06 11:56, Alex Deucher wrote:
> On Fri, May 6, 2022 at 11:43 AM Stylon Wang <stylon.wang@amd.com> wrote:
>>
>> From: Alex Hung <alex.hung@amd.com>
>>
>> [Why & How]
>> CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
>> code should be OS-agnostic.
>>
>> This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
>> in dc and dc/core directories.
>>
>> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>> Acked-by: Stylon Wang <stylon.wang@amd.com>
>> Signed-off-by: Alex Hung <alex.hung@amd.com>
>
> I presume the driver still builds properly on configs where
> CONFIG_DRM_AMD_DC_DCN is not set? E.g., platforms without floating
> point for example?
>
Hi Alex,
This is part of our effort to isolate FPU code inside DML (right now, we
are only missing DCN30); since we are really close to that, many of
these guards become useless. All of these patches were tested in our CI
against:
1. x86 with DCN
2. x86 without DCN
3. Clang
4. make allmodconfig
Additionally, I think that Alex Hung also checked the compilation with
PowerPC.
Thanks
Siqueira
> Alex
>
>> ---
>> drivers/gpu/drm/amd/display/dc/Makefile | 2 -
>> .../display/dc/bios/command_table_helper2.c | 3 +-
>> drivers/gpu/drm/amd/display/dc/core/dc.c | 31 ++--------------
>> .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 -
>> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -
>> .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 --
>> .../drm/amd/display/dc/core/dc_link_dpia.c | 2 -
>> .../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ++---------
>> .../gpu/drm/amd/display/dc/core/dc_stream.c | 8 ----
>> drivers/gpu/drm/amd/display/dc/dc.h | 37 -------------------
>> drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 -
>> .../gpu/drm/amd/display/dc/inc/core_types.h | 17 ++-------
>> 12 files changed, 10 insertions(+), 121 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
>> index f05ab2bf20c5..b4eca0236435 100644
>> --- a/drivers/gpu/drm/amd/display/dc/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
>> @@ -63,9 +63,7 @@ DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink
>> dc_surface.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
>> dc_link_enc_cfg.o dc_link_dpia.o dc_link_dpcd.o
>>
>> -ifdef CONFIG_DRM_AMD_DC_DCN
>> DISPLAY_CORE += dc_vm_helper.o
>> -endif
>>
>> AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> index dd9704ef4ccc..f3792286f571 100644
>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> @@ -65,7 +65,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>> case DCE_VERSION_12_1:
>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>> return true;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> case DCN_VERSION_1_0:
>> case DCN_VERSION_1_01:
>> case DCN_VERSION_2_0:
>> @@ -80,7 +79,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>> case DCN_VERSION_3_16:
>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>> return true;
>> -#endif
>> +
>> default:
>> /* Unsupported DCE */
>> BREAK_TO_DEBUGGER();
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> index c2fcd67bcc4d..1eeea7c184ae 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> @@ -829,14 +829,12 @@ static void dc_destruct(struct dc *dc)
>> kfree(dc->bw_dceip);
>> dc->bw_dceip = NULL;
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> kfree(dc->dcn_soc);
>> dc->dcn_soc = NULL;
>>
>> kfree(dc->dcn_ip);
>> dc->dcn_ip = NULL;
>>
>> -#endif
>> kfree(dc->vm_helper);
>> dc->vm_helper = NULL;
>>
>> @@ -882,10 +880,8 @@ static bool dc_construct(struct dc *dc,
>> struct dc_context *dc_ctx;
>> struct bw_calcs_dceip *dc_dceip;
>> struct bw_calcs_vbios *dc_vbios;
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> struct dcn_soc_bounding_box *dcn_soc;
>> struct dcn_ip_params *dcn_ip;
>> -#endif
>>
>> dc->config = init_params->flags;
>>
>> @@ -913,7 +909,6 @@ static bool dc_construct(struct dc *dc,
>> }
>>
>> dc->bw_vbios = dc_vbios;
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
>> if (!dcn_soc) {
>> dm_error("%s: failed to create dcn_soc\n", __func__);
>> @@ -929,7 +924,6 @@ static bool dc_construct(struct dc *dc,
>> }
>>
>> dc->dcn_ip = dcn_ip;
>> -#endif
>>
>> if (!dc_construct_ctx(dc, init_params)) {
>> dm_error("%s: failed to create ctx\n", __func__);
>> @@ -1868,7 +1862,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
>> return (result == DC_OK);
>> }
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool dc_acquire_release_mpc_3dlut(
>> struct dc *dc, bool acquire,
>> struct dc_stream_state *stream,
>> @@ -1904,7 +1897,7 @@ bool dc_acquire_release_mpc_3dlut(
>> }
>> return ret;
>> }
>> -#endif
>> +
>> static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
>> {
>> int i;
>> @@ -1925,7 +1918,6 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
>> return false;
>> }
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> /* Perform updates here which need to be deferred until next vupdate
>> *
>> * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
>> @@ -1944,7 +1936,6 @@ static void process_deferred_updates(struct dc *dc)
>> dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
>> }
>> }
>> -#endif /* CONFIG_DRM_AMD_DC_DCN */
>>
>> void dc_post_update_surfaces_to_stream(struct dc *dc)
>> {
>> @@ -1971,9 +1962,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
>> dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
>> }
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> process_deferred_updates(dc);
>> -#endif
>>
>> dc->hwss.optimize_bandwidth(dc, context);
>>
>> @@ -1987,9 +1976,7 @@ static void init_state(struct dc *dc, struct dc_state *context)
>> * initialize and obtain IP and SOC the base DML instance from DC is
>> * initially copied into every context
>> */
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
>> -#endif
>> }
>>
>> struct dc_state *dc_create_state(struct dc *dc)
>> @@ -2361,11 +2348,9 @@ static enum surface_update_type check_update_surfaces_for_stream(
>> int i;
>> enum surface_update_type overall_type = UPDATE_TYPE_FAST;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> if (dc->idle_optimizations_allowed)
>> overall_type = UPDATE_TYPE_FULL;
>>
>> -#endif
>> if (stream_status == NULL || stream_status->plane_count != surface_count)
>> overall_type = UPDATE_TYPE_FULL;
>>
>> @@ -2874,10 +2859,8 @@ static void commit_planes_for_stream(struct dc *dc,
>> }
>>
>> if (update_type == UPDATE_TYPE_FULL) {
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> dc_allow_idle_optimizations(dc, false);
>>
>> -#endif
>> if (get_seamless_boot_stream_count(context) == 0)
>> dc->hwss.prepare_bandwidth(dc, context);
>>
>> @@ -2895,7 +2878,6 @@ static void commit_planes_for_stream(struct dc *dc,
>> }
>> }
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
>> struct pipe_ctx *mpcc_pipe;
>> struct pipe_ctx *odm_pipe;
>> @@ -2904,7 +2886,6 @@ static void commit_planes_for_stream(struct dc *dc,
>> for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>> odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
>> }
>> -#endif
>>
>> if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
>> if (top_pipe_to_program &&
>> @@ -3014,7 +2995,6 @@ static void commit_planes_for_stream(struct dc *dc,
>> }
>> if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
>> dc->hwss.program_front_end_for_ctx(dc, context);
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> if (dc->debug.validate_dml_output) {
>> for (i = 0; i < dc->res_pool->pipe_count; i++) {
>> struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
>> @@ -3028,7 +3008,6 @@ static void commit_planes_for_stream(struct dc *dc,
>> &context->res_ctx.pipe_ctx[i].ttu_regs);
>> }
>> }
>> -#endif
>> }
>>
>> // Update Type FAST, Surface updates
>> @@ -3583,8 +3562,6 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)
>> return true;
>> }
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> -
>> void dc_allow_idle_optimizations(struct dc *dc, bool allow)
>> {
>> if (dc->debug.disable_idle_power_optimizations)
>> @@ -3740,7 +3717,6 @@ void dc_hardware_release(struct dc *dc)
>> if (dc->hwss.hardware_release)
>> dc->hwss.hardware_release(dc);
>> }
>> -#endif
>>
>> /*
>> *****************************************************************************
>> @@ -3760,13 +3736,12 @@ void dc_hardware_release(struct dc *dc)
>> */
>> bool dc_is_dmub_outbox_supported(struct dc *dc)
>> {
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> - /* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */
>> + /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
>> if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
>> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
>> !dc->debug.dpia_debug.bits.disable_dpia)
>> return true;
>> -#endif
>> +
>> /* dmub aux needs dmub notifications to be enabled */
>> return dc->debug.enable_dmub_aux_for_legacy_ddc;
>> }
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>> index 643762542e4d..72376075db0c 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>> @@ -345,7 +345,6 @@ void context_clock_trace(
>> struct dc *dc,
>> struct dc_state *context)
>> {
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> DC_LOGGER_INIT(dc->ctx->logger);
>> CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
>> "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
>> @@ -363,7 +362,6 @@ void context_clock_trace(
>> context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
>> context->bw_ctx.bw.dcn.clk.fclk_khz,
>> context->bw_ctx.bw.dcn.clk.socclk_khz);
>> -#endif
>> }
>>
>> /**
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>> index 07f154fc4e56..9529b924742e 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>> @@ -804,7 +804,6 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
>>
>> static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>> {
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
>> * reports DSC support.
>> */
>> @@ -815,7 +814,6 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>> link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
>> !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
>> link->wa_flags.dpia_mst_dsc_always_on = true;
>> -#endif
>> }
>>
>> static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> index 5e49e346aa06..975d631534b5 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> @@ -5127,12 +5127,10 @@ void dp_retrieve_lttpr_cap(struct dc_link *link)
>> else
>> link->lttpr_support = LTTPR_CHECK_EXT_SUPPORT;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* Check DP tunnel LTTPR mode debug option. */
>> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
>> link->dc->debug.dpia_debug.bits.force_non_lttpr)
>> link->lttpr_support = LTTPR_UNSUPPORTED;
>> -#endif
>>
>> if (link->lttpr_support > LTTPR_UNSUPPORTED) {
>> /* By reading LTTPR capability, RX assumes that we will enable
>> @@ -5626,9 +5624,7 @@ static bool retrieve_link_cap(struct dc_link *link)
>> * only if required.
>> */
>> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> !link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around &&
>> -#endif
>> link->dpcd_caps.is_branch_dev &&
>> link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
>> link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>> index 0e95bc5df4e7..a5765f36d86f 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>> @@ -547,11 +547,9 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link,
>> dp_translate_training_aux_read_interval(
>> link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* Check debug option for extending aux read interval. */
>> if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
>> wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
>> -#endif
>>
>> return wait_time_microsec;
>> }
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> index 147c6a3c6312..f702919a2279 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> @@ -56,7 +56,6 @@
>> #include "dce110/dce110_resource.h"
>> #include "dce112/dce112_resource.h"
>> #include "dce120/dce120_resource.h"
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> #include "dcn10/dcn10_resource.h"
>> #include "dcn20/dcn20_resource.h"
>> #include "dcn21/dcn21_resource.h"
>> @@ -68,7 +67,6 @@
>> #include "dcn31/dcn31_resource.h"
>> #include "dcn315/dcn315_resource.h"
>> #include "dcn316/dcn316_resource.h"
>> -#endif
>>
>> #define DC_LOGGER_INIT(logger)
>>
>> @@ -124,7 +122,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>> else
>> dc_version = DCE_VERSION_12_0;
>> break;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> case FAMILY_RV:
>> dc_version = DCN_VERSION_1_0;
>> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
>> @@ -165,7 +162,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>> if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
>> dc_version = DCN_VERSION_3_16;
>> break;
>> -#endif
>>
>> default:
>> dc_version = DCE_VERSION_UNKNOWN;
>> @@ -397,7 +393,6 @@ bool resource_construct(
>> }
>> }
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> for (i = 0; i < caps->num_mpc_3dlut; i++) {
>> pool->mpc_lut[i] = dc_create_3dlut_func();
>> if (pool->mpc_lut[i] == NULL)
>> @@ -406,7 +401,7 @@ bool resource_construct(
>> if (pool->mpc_shaper[i] == NULL)
>> DC_ERR("DC: failed to create MPC shaper!\n");
>> }
>> -#endif
>> +
>> dc->caps.dynamic_audio = false;
>> if (pool->audio_count < pool->stream_enc_count) {
>> dc->caps.dynamic_audio = true;
>> @@ -1369,7 +1364,6 @@ static struct pipe_ctx *acquire_free_pipe_for_head(
>> return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
>> }
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> static int acquire_first_split_pipe(
>> struct resource_context *res_ctx,
>> const struct resource_pool *pool,
>> @@ -1404,7 +1398,6 @@ static int acquire_first_split_pipe(
>> }
>> return -1;
>> }
>> -#endif
>>
>> bool dc_add_plane_to_context(
>> const struct dc *dc,
>> @@ -1447,13 +1440,12 @@ bool dc_add_plane_to_context(
>> while (head_pipe) {
>> free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
>>
>> - #if defined(CONFIG_DRM_AMD_DC_DCN)
>> if (!free_pipe) {
>> int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
>> if (pipe_idx >= 0)
>> free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
>> }
>> - #endif
>> +
>> if (!free_pipe) {
>> dc_plane_state_release(plane_state);
>> return false;
>> @@ -2259,10 +2251,8 @@ enum dc_status resource_map_pool_resources(
>> /* acquire new resources */
>> pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> if (pipe_idx < 0)
>> pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
>> -#endif
>>
>> if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
>> return DC_NO_CONTROLLER_RESOURCE;
>> @@ -2453,7 +2443,6 @@ enum dc_status dc_validate_global_state(
>> if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
>> result = DC_FAIL_BANDWIDTH_VALIDATE;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /*
>> * Only update link encoder to stream assignment after bandwidth validation passed.
>> * TODO: Split out assignment and validation.
>> @@ -2461,7 +2450,6 @@ enum dc_status dc_validate_global_state(
>> if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
>> dc->res_pool->funcs->link_encs_assign(
>> dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
>> -#endif
>>
>> return result;
>> }
>> @@ -3189,10 +3177,8 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
>> case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
>> case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
>> -#endif
>> return 32;
>> case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
>> @@ -3345,7 +3331,6 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
>> /* TODO - get transmitter to phy idx mapping from DMUB */
>> uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
>> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
>> switch (transmitter) {
>> @@ -3369,7 +3354,7 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
>> break;
>> }
>> }
>> -#endif
>> +
>> return phy_idx;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>> index c4e871f358ab..acca35d86c10 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>> @@ -314,9 +314,7 @@ bool dc_stream_set_cursor_attributes(
>> const struct dc_cursor_attributes *attributes)
>> {
>> struct dc *dc;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool reset_idle_optimizations = false;
>> -#endif
>>
>> if (NULL == stream) {
>> dm_error("DC: dc_stream is NULL!\n");
>> @@ -346,12 +344,10 @@ bool dc_stream_set_cursor_attributes(
>> #endif
>> program_cursor_attributes(dc, stream, attributes);
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* re-enable idle optimizations if necessary */
>> if (reset_idle_optimizations)
>> dc_allow_idle_optimizations(dc, true);
>>
>> -#endif
>> return true;
>> }
>>
>> @@ -396,9 +392,7 @@ bool dc_stream_set_cursor_position(
>> const struct dc_cursor_position *position)
>> {
>> struct dc *dc;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool reset_idle_optimizations = false;
>> -#endif
>>
>> if (NULL == stream) {
>> dm_error("DC: dc_stream is NULL!\n");
>> @@ -424,12 +418,10 @@ bool dc_stream_set_cursor_position(
>> stream->cursor_position = *position;
>>
>> program_cursor_position(dc, stream, position);
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* re-enable idle optimizations if necessary */
>> if (reset_idle_optimizations)
>> dc_allow_idle_optimizations(dc, true);
>>
>> -#endif
>> return true;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
>> index e37d9c19f089..0f86bb809e04 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dc.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
>> @@ -222,7 +222,6 @@ struct dc_dcc_setting {
>> unsigned int max_compressed_blk_size;
>> unsigned int max_uncompressed_blk_size;
>> bool independent_64b_blks;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> //These bitfields to be used starting with DCN
>> struct {
>> uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
>> @@ -230,7 +229,6 @@ struct dc_dcc_setting {
>> uint32_t dcc_256_128_128 : 1; //available starting with DCN
>> uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
>> } dcc_controls;
>> -#endif
>> };
>>
>> struct dc_surface_dcc_cap {
>> @@ -332,9 +330,7 @@ struct dc_config {
>> bool enable_4to1MPC;
>> bool enable_windowed_mpo_odm;
>> bool allow_edp_hotplug_detection;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool clamp_min_dcfclk;
>> -#endif
>> uint64_t vblank_alignment_dto_params;
>> uint8_t vblank_alignment_max_frame_time_diff;
>> bool is_asymmetric_memory;
>> @@ -395,14 +391,12 @@ enum dcn_pwr_state {
>> DCN_PWR_STATE_LOW_POWER = 3,
>> };
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> enum dcn_zstate_support_state {
>> DCN_ZSTATE_SUPPORT_UNKNOWN,
>> DCN_ZSTATE_SUPPORT_ALLOW,
>> DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
>> DCN_ZSTATE_SUPPORT_DISALLOW,
>> };
>> -#endif
>> /*
>> * For any clocks that may differ per pipe
>> * only the max is stored in this structure
>> @@ -420,10 +414,8 @@ struct dc_clocks {
>> int phyclk_khz;
>> int dramclk_khz;
>> bool p_state_change_support;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> enum dcn_zstate_support_state zstate_support;
>> bool dtbclk_en;
>> -#endif
>> enum dcn_pwr_state pwr_state;
>> /*
>> * Elements below are not compared for the purposes of
>> @@ -653,9 +645,7 @@ struct dc_debug_options {
>> bool disable_pplib_clock_request;
>> bool disable_clock_gate;
>> bool disable_mem_low_power;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool pstate_enabled;
>> -#endif
>> bool disable_dmcu;
>> bool disable_psr;
>> bool force_abm_enable;
>> @@ -673,20 +663,16 @@ struct dc_debug_options {
>> bool remove_disconnect_edp;
>> unsigned int force_odm_combine; //bit vector based on otg inst
>> unsigned int seamless_boot_odm_combine;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> unsigned int force_odm_combine_4to1; //bit vector based on otg inst
>> bool disable_z9_mpc;
>> -#endif
>> unsigned int force_fclk_khz;
>> bool enable_tri_buf;
>> bool dmub_offload_enabled;
>> bool dmcub_emulation;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool disable_idle_power_optimizations;
>> unsigned int mall_size_override;
>> unsigned int mall_additional_timer_percent;
>> bool mall_error_as_fatal;
>> -#endif
>> bool dmub_command_table; /* for testing only */
>> struct dc_bw_validation_profile bw_val_profile;
>> bool disable_fec;
>> @@ -695,9 +681,7 @@ struct dc_debug_options {
>> * watermarks are not affected.
>> */
>> unsigned int force_min_dcfclk_mhz;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> int dwb_fi_phase;
>> -#endif
>> bool disable_timing_sync;
>> bool cm_in_bypass;
>> int force_clock_mode;/*every mode change.*/
>> @@ -729,11 +713,9 @@ struct dc_debug_options {
>> enum det_size crb_alloc_policy;
>> int crb_alloc_policy_min_disp_count;
>> bool disable_z10;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool enable_z9_disable_interface;
>> bool enable_sw_cntl_psr;
>> union dpia_debug_options dpia_debug;
>> -#endif
>> bool apply_vendor_specific_lttpr_wa;
>> bool extended_blank_optimization;
>> union aux_wake_wa_options aux_wake_wa;
>> @@ -767,11 +749,9 @@ struct dc {
>> /* Inputs into BW and WM calculations. */
>> struct bw_calcs_dceip *bw_dceip;
>> struct bw_calcs_vbios *bw_vbios;
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> struct dcn_soc_bounding_box *dcn_soc;
>> struct dcn_ip_params *dcn_ip;
>> struct display_mode_lib dml;
>> -#endif
>>
>> /* HW functions */
>> struct hw_sequencer_funcs hwss;
>> @@ -780,12 +760,8 @@ struct dc {
>> /* Require to optimize clocks and bandwidth for added/removed planes */
>> bool optimized_required;
>> bool wm_optimized_required;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool idle_optimizations_allowed;
>> -#endif
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool enable_c20_dtm_b0;
>> -#endif
>>
>> /* Require to maintain clocks and bandwidth for UEFI enabled HW */
>>
>> @@ -835,9 +811,7 @@ struct dc_init_data {
>> uint64_t log_mask;
>>
>> struct dpcd_vendor_signature vendor_signature;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool force_smu_not_present;
>> -#endif
>> };
>>
>> struct dc_callback_init {
>> @@ -1030,9 +1004,7 @@ struct dc_plane_state {
>> struct dc_transfer_func *in_shaper_func;
>> struct dc_transfer_func *blend_tf;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> struct dc_transfer_func *gamcor_tf;
>> -#endif
>> enum surface_pixel_format format;
>> enum dc_rotation_angle rotation;
>> enum plane_stereo_format stereo_format;
>> @@ -1169,13 +1141,11 @@ void dc_resource_state_construct(
>> const struct dc *dc,
>> struct dc_state *dst_ctx);
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool dc_acquire_release_mpc_3dlut(
>> struct dc *dc, bool acquire,
>> struct dc_stream_state *stream,
>> struct dc_3dlut **lut,
>> struct dc_transfer_func **shaper);
>> -#endif
>>
>> void dc_resource_state_copy_construct(
>> const struct dc_state *src_ctx,
>> @@ -1306,10 +1276,8 @@ struct hdcp_caps {
>>
>> #include "dc_link.h"
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
>>
>> -#endif
>> /*******************************************************************************
>> * Sink Interfaces - A sink corresponds to a display output device
>> ******************************************************************************/
>> @@ -1433,7 +1401,6 @@ bool dc_is_dmcu_initialized(struct dc *dc);
>>
>> enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
>> void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>
>> bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
>> struct dc_cursor_attributes *cursor_attr);
>> @@ -1458,13 +1425,9 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
>> /* cleanup on driver unload */
>> void dc_hardware_release(struct dc *dc);
>>
>> -#endif
>> -
>> bool dc_set_psr_allow_active(struct dc *dc, bool enable);
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> void dc_z10_restore(const struct dc *dc);
>> void dc_z10_save_init(struct dc *dc);
>> -#endif
>>
>> bool dc_is_dmub_outbox_supported(struct dc *dc);
>> bool dc_enable_dmub_notifications(struct dc *dc);
>> diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>> index 31109db02e93..fb6a2d7b6470 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>> @@ -160,9 +160,7 @@ void dm_set_dcn_clocks(
>> struct dc_context *ctx,
>> struct dc_clocks *clks);
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable);
>> -#endif
>>
>> void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz);
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>> index 951c9b60917d..26f3a55c35d7 100644
>> --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>> +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>> @@ -33,9 +33,7 @@
>> #include "dc_bios_types.h"
>> #include "mem_input.h"
>> #include "hubp.h"
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> #include "mpc.h"
>> -#endif
>> #include "dwb.h"
>> #include "mcif_wb.h"
>> #include "panel_cntl.h"
>> @@ -181,7 +179,6 @@ struct resource_funcs {
>> void (*update_bw_bounding_box)(
>> struct dc *dc,
>> struct clk_bw_params *bw_params);
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool (*acquire_post_bldn_3dlut)(
>> struct resource_context *res_ctx,
>> const struct resource_pool *pool,
>> @@ -194,7 +191,7 @@ struct resource_funcs {
>> const struct resource_pool *pool,
>> struct dc_3dlut **lut,
>> struct dc_transfer_func **shaper);
>> -#endif
>> +
>> enum dc_status (*add_dsc_to_stream_resource)(
>> struct dc *dc, struct dc_state *state,
>> struct dc_stream_state *stream);
>> @@ -254,10 +251,9 @@ struct resource_pool {
>> struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
>> unsigned int hpo_dp_link_enc_count;
>> struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> struct dc_3dlut *mpc_lut[MAX_PIPES];
>> struct dc_transfer_func *mpc_shaper[MAX_PIPES];
>> -#endif
>> +
>> struct {
>> unsigned int xtalin_clock_inKhz;
>> unsigned int dccg_ref_clock_inKhz;
>> @@ -286,9 +282,7 @@ struct resource_pool {
>> struct dmcu *dmcu;
>> struct dmub_psr *psr;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> struct abm *multiple_abms[MAX_PIPES];
>> -#endif
>>
>> const struct resource_funcs *funcs;
>> const struct resource_caps *res_cap;
>> @@ -380,7 +374,6 @@ struct pipe_ctx {
>> struct pipe_ctx *next_odm_pipe;
>> struct pipe_ctx *prev_odm_pipe;
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> struct _vcs_dpi_display_dlg_regs_st dlg_regs;
>> struct _vcs_dpi_display_ttu_regs_st ttu_regs;
>> struct _vcs_dpi_display_rq_regs_st rq_regs;
>> @@ -390,7 +383,7 @@ struct pipe_ctx {
>> struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
>> int det_buffer_size_kb;
>> bool unbounded_req;
>> -#endif
>> +
>> union pipe_update_flags update_flags;
>> struct dwbc *dwbc;
>> struct mcif_wb *mcif_wb;
>> @@ -419,9 +412,7 @@ struct resource_context {
>> bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
>> unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
>> int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool is_mpc_3dlut_acquired[MAX_PIPES];
>> -#endif
>> };
>>
>> struct dce_bw_output {
>> @@ -484,9 +475,7 @@ struct dc_state {
>>
>> /* Note: these are big structures, do *not* put on stack! */
>> struct dm_pp_display_configuration pp_display_cfg;
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> struct dcn_bw_internal_vars dcn_bw_vars;
>> -#endif
>>
>> struct clk_mgr *clk_mgr;
>>
>> --
>> 2.35.1
>>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
2022-05-06 17:12 ` Rodrigo Siqueira Jordao
@ 2022-05-06 18:00 ` Alex Deucher
2022-05-07 7:39 ` Cui, Flora
1 sibling, 0 replies; 29+ messages in thread
From: Alex Deucher @ 2022-05-06 18:00 UTC (permalink / raw)
To: Rodrigo Siqueira Jordao
Cc: Stylon Wang, Solomon Chiu, Alex Hung, Bhawanpreet Lakha,
Qingqing Zhuo, Roman Li, amd-gfx list, Leo (Sunpeng) Li,
Aurabindo Pillai, Wayne Lin, Wentland, Harry, Gutierrez, Agustin,
Kotarac, Pavle
On Fri, May 6, 2022 at 1:12 PM Rodrigo Siqueira Jordao
<Rodrigo.Siqueira@amd.com> wrote:
>
>
>
> On 2022-05-06 11:56, Alex Deucher wrote:
> > On Fri, May 6, 2022 at 11:43 AM Stylon Wang <stylon.wang@amd.com> wrote:
> >>
> >> From: Alex Hung <alex.hung@amd.com>
> >>
> >> [Why & How]
> >> CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
> >> code should be OS-agnostic.
> >>
> >> This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
> >> in dc and dc/core directories.
> >>
> >> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> >> Acked-by: Stylon Wang <stylon.wang@amd.com>
> >> Signed-off-by: Alex Hung <alex.hung@amd.com>
> >
> > I presume the driver still builds properly on configs where
> > CONFIG_DRM_AMD_DC_DCN is not set? E.g., platforms without floating
> > point for example?
> >
>
> Hi Alex,
>
> This is part of our effort to isolate FPU code inside DML (right now, we
> are only missing DCN30); since we are really close to that, many of
> these guards become useless. All of these patches were tested in our CI
> against:
>
> 1. x86 with DCN
> 2. x86 without DCN
> 3. Clang
> 4. make allmodconfig
>
> Additionally, I think that Alex Hung also checked the compilation with
> PowerPC.
Excellent. Thanks!
Alex
>
> Thanks
> Siqueira
>
>
> > Alex
> >
> >> ---
> >> drivers/gpu/drm/amd/display/dc/Makefile | 2 -
> >> .../display/dc/bios/command_table_helper2.c | 3 +-
> >> drivers/gpu/drm/amd/display/dc/core/dc.c | 31 ++--------------
> >> .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 -
> >> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -
> >> .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 --
> >> .../drm/amd/display/dc/core/dc_link_dpia.c | 2 -
> >> .../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ++---------
> >> .../gpu/drm/amd/display/dc/core/dc_stream.c | 8 ----
> >> drivers/gpu/drm/amd/display/dc/dc.h | 37 -------------------
> >> drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 -
> >> .../gpu/drm/amd/display/dc/inc/core_types.h | 17 ++-------
> >> 12 files changed, 10 insertions(+), 121 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
> >> index f05ab2bf20c5..b4eca0236435 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> >> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> >> @@ -63,9 +63,7 @@ DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink
> >> dc_surface.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
> >> dc_link_enc_cfg.o dc_link_dpia.o dc_link_dpcd.o
> >>
> >> -ifdef CONFIG_DRM_AMD_DC_DCN
> >> DISPLAY_CORE += dc_vm_helper.o
> >> -endif
> >>
> >> AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> index dd9704ef4ccc..f3792286f571 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> @@ -65,7 +65,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> >> case DCE_VERSION_12_1:
> >> *h = dal_cmd_tbl_helper_dce112_get_table2();
> >> return true;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> case DCN_VERSION_1_0:
> >> case DCN_VERSION_1_01:
> >> case DCN_VERSION_2_0:
> >> @@ -80,7 +79,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> >> case DCN_VERSION_3_16:
> >> *h = dal_cmd_tbl_helper_dce112_get_table2();
> >> return true;
> >> -#endif
> >> +
> >> default:
> >> /* Unsupported DCE */
> >> BREAK_TO_DEBUGGER();
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> >> index c2fcd67bcc4d..1eeea7c184ae 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> >> @@ -829,14 +829,12 @@ static void dc_destruct(struct dc *dc)
> >> kfree(dc->bw_dceip);
> >> dc->bw_dceip = NULL;
> >>
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> kfree(dc->dcn_soc);
> >> dc->dcn_soc = NULL;
> >>
> >> kfree(dc->dcn_ip);
> >> dc->dcn_ip = NULL;
> >>
> >> -#endif
> >> kfree(dc->vm_helper);
> >> dc->vm_helper = NULL;
> >>
> >> @@ -882,10 +880,8 @@ static bool dc_construct(struct dc *dc,
> >> struct dc_context *dc_ctx;
> >> struct bw_calcs_dceip *dc_dceip;
> >> struct bw_calcs_vbios *dc_vbios;
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> struct dcn_soc_bounding_box *dcn_soc;
> >> struct dcn_ip_params *dcn_ip;
> >> -#endif
> >>
> >> dc->config = init_params->flags;
> >>
> >> @@ -913,7 +909,6 @@ static bool dc_construct(struct dc *dc,
> >> }
> >>
> >> dc->bw_vbios = dc_vbios;
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
> >> if (!dcn_soc) {
> >> dm_error("%s: failed to create dcn_soc\n", __func__);
> >> @@ -929,7 +924,6 @@ static bool dc_construct(struct dc *dc,
> >> }
> >>
> >> dc->dcn_ip = dcn_ip;
> >> -#endif
> >>
> >> if (!dc_construct_ctx(dc, init_params)) {
> >> dm_error("%s: failed to create ctx\n", __func__);
> >> @@ -1868,7 +1862,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
> >> return (result == DC_OK);
> >> }
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool dc_acquire_release_mpc_3dlut(
> >> struct dc *dc, bool acquire,
> >> struct dc_stream_state *stream,
> >> @@ -1904,7 +1897,7 @@ bool dc_acquire_release_mpc_3dlut(
> >> }
> >> return ret;
> >> }
> >> -#endif
> >> +
> >> static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
> >> {
> >> int i;
> >> @@ -1925,7 +1918,6 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
> >> return false;
> >> }
> >>
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> /* Perform updates here which need to be deferred until next vupdate
> >> *
> >> * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
> >> @@ -1944,7 +1936,6 @@ static void process_deferred_updates(struct dc *dc)
> >> dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
> >> }
> >> }
> >> -#endif /* CONFIG_DRM_AMD_DC_DCN */
> >>
> >> void dc_post_update_surfaces_to_stream(struct dc *dc)
> >> {
> >> @@ -1971,9 +1962,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
> >> dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
> >> }
> >>
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> process_deferred_updates(dc);
> >> -#endif
> >>
> >> dc->hwss.optimize_bandwidth(dc, context);
> >>
> >> @@ -1987,9 +1976,7 @@ static void init_state(struct dc *dc, struct dc_state *context)
> >> * initialize and obtain IP and SOC the base DML instance from DC is
> >> * initially copied into every context
> >> */
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
> >> -#endif
> >> }
> >>
> >> struct dc_state *dc_create_state(struct dc *dc)
> >> @@ -2361,11 +2348,9 @@ static enum surface_update_type check_update_surfaces_for_stream(
> >> int i;
> >> enum surface_update_type overall_type = UPDATE_TYPE_FAST;
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> if (dc->idle_optimizations_allowed)
> >> overall_type = UPDATE_TYPE_FULL;
> >>
> >> -#endif
> >> if (stream_status == NULL || stream_status->plane_count != surface_count)
> >> overall_type = UPDATE_TYPE_FULL;
> >>
> >> @@ -2874,10 +2859,8 @@ static void commit_planes_for_stream(struct dc *dc,
> >> }
> >>
> >> if (update_type == UPDATE_TYPE_FULL) {
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> dc_allow_idle_optimizations(dc, false);
> >>
> >> -#endif
> >> if (get_seamless_boot_stream_count(context) == 0)
> >> dc->hwss.prepare_bandwidth(dc, context);
> >>
> >> @@ -2895,7 +2878,6 @@ static void commit_planes_for_stream(struct dc *dc,
> >> }
> >> }
> >>
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
> >> struct pipe_ctx *mpcc_pipe;
> >> struct pipe_ctx *odm_pipe;
> >> @@ -2904,7 +2886,6 @@ static void commit_planes_for_stream(struct dc *dc,
> >> for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
> >> odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
> >> }
> >> -#endif
> >>
> >> if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
> >> if (top_pipe_to_program &&
> >> @@ -3014,7 +2995,6 @@ static void commit_planes_for_stream(struct dc *dc,
> >> }
> >> if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
> >> dc->hwss.program_front_end_for_ctx(dc, context);
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> if (dc->debug.validate_dml_output) {
> >> for (i = 0; i < dc->res_pool->pipe_count; i++) {
> >> struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
> >> @@ -3028,7 +3008,6 @@ static void commit_planes_for_stream(struct dc *dc,
> >> &context->res_ctx.pipe_ctx[i].ttu_regs);
> >> }
> >> }
> >> -#endif
> >> }
> >>
> >> // Update Type FAST, Surface updates
> >> @@ -3583,8 +3562,6 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)
> >> return true;
> >> }
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> -
> >> void dc_allow_idle_optimizations(struct dc *dc, bool allow)
> >> {
> >> if (dc->debug.disable_idle_power_optimizations)
> >> @@ -3740,7 +3717,6 @@ void dc_hardware_release(struct dc *dc)
> >> if (dc->hwss.hardware_release)
> >> dc->hwss.hardware_release(dc);
> >> }
> >> -#endif
> >>
> >> /*
> >> *****************************************************************************
> >> @@ -3760,13 +3736,12 @@ void dc_hardware_release(struct dc *dc)
> >> */
> >> bool dc_is_dmub_outbox_supported(struct dc *dc)
> >> {
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> - /* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */
> >> + /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
> >> if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
> >> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
> >> !dc->debug.dpia_debug.bits.disable_dpia)
> >> return true;
> >> -#endif
> >> +
> >> /* dmub aux needs dmub notifications to be enabled */
> >> return dc->debug.enable_dmub_aux_for_legacy_ddc;
> >> }
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
> >> index 643762542e4d..72376075db0c 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
> >> @@ -345,7 +345,6 @@ void context_clock_trace(
> >> struct dc *dc,
> >> struct dc_state *context)
> >> {
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> DC_LOGGER_INIT(dc->ctx->logger);
> >> CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
> >> "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
> >> @@ -363,7 +362,6 @@ void context_clock_trace(
> >> context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
> >> context->bw_ctx.bw.dcn.clk.fclk_khz,
> >> context->bw_ctx.bw.dcn.clk.socclk_khz);
> >> -#endif
> >> }
> >>
> >> /**
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> >> index 07f154fc4e56..9529b924742e 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> >> @@ -804,7 +804,6 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
> >>
> >> static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
> >> {
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
> >> * reports DSC support.
> >> */
> >> @@ -815,7 +814,6 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
> >> link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
> >> !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
> >> link->wa_flags.dpia_mst_dsc_always_on = true;
> >> -#endif
> >> }
> >>
> >> static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> >> index 5e49e346aa06..975d631534b5 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> >> @@ -5127,12 +5127,10 @@ void dp_retrieve_lttpr_cap(struct dc_link *link)
> >> else
> >> link->lttpr_support = LTTPR_CHECK_EXT_SUPPORT;
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> /* Check DP tunnel LTTPR mode debug option. */
> >> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
> >> link->dc->debug.dpia_debug.bits.force_non_lttpr)
> >> link->lttpr_support = LTTPR_UNSUPPORTED;
> >> -#endif
> >>
> >> if (link->lttpr_support > LTTPR_UNSUPPORTED) {
> >> /* By reading LTTPR capability, RX assumes that we will enable
> >> @@ -5626,9 +5624,7 @@ static bool retrieve_link_cap(struct dc_link *link)
> >> * only if required.
> >> */
> >> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> !link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around &&
> >> -#endif
> >> link->dpcd_caps.is_branch_dev &&
> >> link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
> >> link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
> >> index 0e95bc5df4e7..a5765f36d86f 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
> >> @@ -547,11 +547,9 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link,
> >> dp_translate_training_aux_read_interval(
> >> link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> /* Check debug option for extending aux read interval. */
> >> if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
> >> wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
> >> -#endif
> >>
> >> return wait_time_microsec;
> >> }
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> index 147c6a3c6312..f702919a2279 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> @@ -56,7 +56,6 @@
> >> #include "dce110/dce110_resource.h"
> >> #include "dce112/dce112_resource.h"
> >> #include "dce120/dce120_resource.h"
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> #include "dcn10/dcn10_resource.h"
> >> #include "dcn20/dcn20_resource.h"
> >> #include "dcn21/dcn21_resource.h"
> >> @@ -68,7 +67,6 @@
> >> #include "dcn31/dcn31_resource.h"
> >> #include "dcn315/dcn315_resource.h"
> >> #include "dcn316/dcn316_resource.h"
> >> -#endif
> >>
> >> #define DC_LOGGER_INIT(logger)
> >>
> >> @@ -124,7 +122,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
> >> else
> >> dc_version = DCE_VERSION_12_0;
> >> break;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> case FAMILY_RV:
> >> dc_version = DCN_VERSION_1_0;
> >> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
> >> @@ -165,7 +162,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
> >> if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
> >> dc_version = DCN_VERSION_3_16;
> >> break;
> >> -#endif
> >>
> >> default:
> >> dc_version = DCE_VERSION_UNKNOWN;
> >> @@ -397,7 +393,6 @@ bool resource_construct(
> >> }
> >> }
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> for (i = 0; i < caps->num_mpc_3dlut; i++) {
> >> pool->mpc_lut[i] = dc_create_3dlut_func();
> >> if (pool->mpc_lut[i] == NULL)
> >> @@ -406,7 +401,7 @@ bool resource_construct(
> >> if (pool->mpc_shaper[i] == NULL)
> >> DC_ERR("DC: failed to create MPC shaper!\n");
> >> }
> >> -#endif
> >> +
> >> dc->caps.dynamic_audio = false;
> >> if (pool->audio_count < pool->stream_enc_count) {
> >> dc->caps.dynamic_audio = true;
> >> @@ -1369,7 +1364,6 @@ static struct pipe_ctx *acquire_free_pipe_for_head(
> >> return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
> >> }
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> static int acquire_first_split_pipe(
> >> struct resource_context *res_ctx,
> >> const struct resource_pool *pool,
> >> @@ -1404,7 +1398,6 @@ static int acquire_first_split_pipe(
> >> }
> >> return -1;
> >> }
> >> -#endif
> >>
> >> bool dc_add_plane_to_context(
> >> const struct dc *dc,
> >> @@ -1447,13 +1440,12 @@ bool dc_add_plane_to_context(
> >> while (head_pipe) {
> >> free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
> >>
> >> - #if defined(CONFIG_DRM_AMD_DC_DCN)
> >> if (!free_pipe) {
> >> int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
> >> if (pipe_idx >= 0)
> >> free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
> >> }
> >> - #endif
> >> +
> >> if (!free_pipe) {
> >> dc_plane_state_release(plane_state);
> >> return false;
> >> @@ -2259,10 +2251,8 @@ enum dc_status resource_map_pool_resources(
> >> /* acquire new resources */
> >> pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
> >>
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> if (pipe_idx < 0)
> >> pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
> >> -#endif
> >>
> >> if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
> >> return DC_NO_CONTROLLER_RESOURCE;
> >> @@ -2453,7 +2443,6 @@ enum dc_status dc_validate_global_state(
> >> if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
> >> result = DC_FAIL_BANDWIDTH_VALIDATE;
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> /*
> >> * Only update link encoder to stream assignment after bandwidth validation passed.
> >> * TODO: Split out assignment and validation.
> >> @@ -2461,7 +2450,6 @@ enum dc_status dc_validate_global_state(
> >> if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
> >> dc->res_pool->funcs->link_encs_assign(
> >> dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
> >> -#endif
> >>
> >> return result;
> >> }
> >> @@ -3189,10 +3177,8 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
> >> case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
> >> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
> >> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
> >> case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
> >> -#endif
> >> return 32;
> >> case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
> >> case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
> >> @@ -3345,7 +3331,6 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
> >> /* TODO - get transmitter to phy idx mapping from DMUB */
> >> uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
> >> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
> >> switch (transmitter) {
> >> @@ -3369,7 +3354,7 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
> >> break;
> >> }
> >> }
> >> -#endif
> >> +
> >> return phy_idx;
> >> }
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> >> index c4e871f358ab..acca35d86c10 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> >> @@ -314,9 +314,7 @@ bool dc_stream_set_cursor_attributes(
> >> const struct dc_cursor_attributes *attributes)
> >> {
> >> struct dc *dc;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool reset_idle_optimizations = false;
> >> -#endif
> >>
> >> if (NULL == stream) {
> >> dm_error("DC: dc_stream is NULL!\n");
> >> @@ -346,12 +344,10 @@ bool dc_stream_set_cursor_attributes(
> >> #endif
> >> program_cursor_attributes(dc, stream, attributes);
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> /* re-enable idle optimizations if necessary */
> >> if (reset_idle_optimizations)
> >> dc_allow_idle_optimizations(dc, true);
> >>
> >> -#endif
> >> return true;
> >> }
> >>
> >> @@ -396,9 +392,7 @@ bool dc_stream_set_cursor_position(
> >> const struct dc_cursor_position *position)
> >> {
> >> struct dc *dc;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool reset_idle_optimizations = false;
> >> -#endif
> >>
> >> if (NULL == stream) {
> >> dm_error("DC: dc_stream is NULL!\n");
> >> @@ -424,12 +418,10 @@ bool dc_stream_set_cursor_position(
> >> stream->cursor_position = *position;
> >>
> >> program_cursor_position(dc, stream, position);
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> /* re-enable idle optimizations if necessary */
> >> if (reset_idle_optimizations)
> >> dc_allow_idle_optimizations(dc, true);
> >>
> >> -#endif
> >> return true;
> >> }
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
> >> index e37d9c19f089..0f86bb809e04 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> >> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> >> @@ -222,7 +222,6 @@ struct dc_dcc_setting {
> >> unsigned int max_compressed_blk_size;
> >> unsigned int max_uncompressed_blk_size;
> >> bool independent_64b_blks;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> //These bitfields to be used starting with DCN
> >> struct {
> >> uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
> >> @@ -230,7 +229,6 @@ struct dc_dcc_setting {
> >> uint32_t dcc_256_128_128 : 1; //available starting with DCN
> >> uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
> >> } dcc_controls;
> >> -#endif
> >> };
> >>
> >> struct dc_surface_dcc_cap {
> >> @@ -332,9 +330,7 @@ struct dc_config {
> >> bool enable_4to1MPC;
> >> bool enable_windowed_mpo_odm;
> >> bool allow_edp_hotplug_detection;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool clamp_min_dcfclk;
> >> -#endif
> >> uint64_t vblank_alignment_dto_params;
> >> uint8_t vblank_alignment_max_frame_time_diff;
> >> bool is_asymmetric_memory;
> >> @@ -395,14 +391,12 @@ enum dcn_pwr_state {
> >> DCN_PWR_STATE_LOW_POWER = 3,
> >> };
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> enum dcn_zstate_support_state {
> >> DCN_ZSTATE_SUPPORT_UNKNOWN,
> >> DCN_ZSTATE_SUPPORT_ALLOW,
> >> DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
> >> DCN_ZSTATE_SUPPORT_DISALLOW,
> >> };
> >> -#endif
> >> /*
> >> * For any clocks that may differ per pipe
> >> * only the max is stored in this structure
> >> @@ -420,10 +414,8 @@ struct dc_clocks {
> >> int phyclk_khz;
> >> int dramclk_khz;
> >> bool p_state_change_support;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> enum dcn_zstate_support_state zstate_support;
> >> bool dtbclk_en;
> >> -#endif
> >> enum dcn_pwr_state pwr_state;
> >> /*
> >> * Elements below are not compared for the purposes of
> >> @@ -653,9 +645,7 @@ struct dc_debug_options {
> >> bool disable_pplib_clock_request;
> >> bool disable_clock_gate;
> >> bool disable_mem_low_power;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool pstate_enabled;
> >> -#endif
> >> bool disable_dmcu;
> >> bool disable_psr;
> >> bool force_abm_enable;
> >> @@ -673,20 +663,16 @@ struct dc_debug_options {
> >> bool remove_disconnect_edp;
> >> unsigned int force_odm_combine; //bit vector based on otg inst
> >> unsigned int seamless_boot_odm_combine;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> unsigned int force_odm_combine_4to1; //bit vector based on otg inst
> >> bool disable_z9_mpc;
> >> -#endif
> >> unsigned int force_fclk_khz;
> >> bool enable_tri_buf;
> >> bool dmub_offload_enabled;
> >> bool dmcub_emulation;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool disable_idle_power_optimizations;
> >> unsigned int mall_size_override;
> >> unsigned int mall_additional_timer_percent;
> >> bool mall_error_as_fatal;
> >> -#endif
> >> bool dmub_command_table; /* for testing only */
> >> struct dc_bw_validation_profile bw_val_profile;
> >> bool disable_fec;
> >> @@ -695,9 +681,7 @@ struct dc_debug_options {
> >> * watermarks are not affected.
> >> */
> >> unsigned int force_min_dcfclk_mhz;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> int dwb_fi_phase;
> >> -#endif
> >> bool disable_timing_sync;
> >> bool cm_in_bypass;
> >> int force_clock_mode;/*every mode change.*/
> >> @@ -729,11 +713,9 @@ struct dc_debug_options {
> >> enum det_size crb_alloc_policy;
> >> int crb_alloc_policy_min_disp_count;
> >> bool disable_z10;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool enable_z9_disable_interface;
> >> bool enable_sw_cntl_psr;
> >> union dpia_debug_options dpia_debug;
> >> -#endif
> >> bool apply_vendor_specific_lttpr_wa;
> >> bool extended_blank_optimization;
> >> union aux_wake_wa_options aux_wake_wa;
> >> @@ -767,11 +749,9 @@ struct dc {
> >> /* Inputs into BW and WM calculations. */
> >> struct bw_calcs_dceip *bw_dceip;
> >> struct bw_calcs_vbios *bw_vbios;
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> struct dcn_soc_bounding_box *dcn_soc;
> >> struct dcn_ip_params *dcn_ip;
> >> struct display_mode_lib dml;
> >> -#endif
> >>
> >> /* HW functions */
> >> struct hw_sequencer_funcs hwss;
> >> @@ -780,12 +760,8 @@ struct dc {
> >> /* Require to optimize clocks and bandwidth for added/removed planes */
> >> bool optimized_required;
> >> bool wm_optimized_required;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool idle_optimizations_allowed;
> >> -#endif
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool enable_c20_dtm_b0;
> >> -#endif
> >>
> >> /* Require to maintain clocks and bandwidth for UEFI enabled HW */
> >>
> >> @@ -835,9 +811,7 @@ struct dc_init_data {
> >> uint64_t log_mask;
> >>
> >> struct dpcd_vendor_signature vendor_signature;
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool force_smu_not_present;
> >> -#endif
> >> };
> >>
> >> struct dc_callback_init {
> >> @@ -1030,9 +1004,7 @@ struct dc_plane_state {
> >> struct dc_transfer_func *in_shaper_func;
> >> struct dc_transfer_func *blend_tf;
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> struct dc_transfer_func *gamcor_tf;
> >> -#endif
> >> enum surface_pixel_format format;
> >> enum dc_rotation_angle rotation;
> >> enum plane_stereo_format stereo_format;
> >> @@ -1169,13 +1141,11 @@ void dc_resource_state_construct(
> >> const struct dc *dc,
> >> struct dc_state *dst_ctx);
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool dc_acquire_release_mpc_3dlut(
> >> struct dc *dc, bool acquire,
> >> struct dc_stream_state *stream,
> >> struct dc_3dlut **lut,
> >> struct dc_transfer_func **shaper);
> >> -#endif
> >>
> >> void dc_resource_state_copy_construct(
> >> const struct dc_state *src_ctx,
> >> @@ -1306,10 +1276,8 @@ struct hdcp_caps {
> >>
> >> #include "dc_link.h"
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
> >>
> >> -#endif
> >> /*******************************************************************************
> >> * Sink Interfaces - A sink corresponds to a display output device
> >> ******************************************************************************/
> >> @@ -1433,7 +1401,6 @@ bool dc_is_dmcu_initialized(struct dc *dc);
> >>
> >> enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
> >> void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >>
> >> bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
> >> struct dc_cursor_attributes *cursor_attr);
> >> @@ -1458,13 +1425,9 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
> >> /* cleanup on driver unload */
> >> void dc_hardware_release(struct dc *dc);
> >>
> >> -#endif
> >> -
> >> bool dc_set_psr_allow_active(struct dc *dc, bool enable);
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> void dc_z10_restore(const struct dc *dc);
> >> void dc_z10_save_init(struct dc *dc);
> >> -#endif
> >>
> >> bool dc_is_dmub_outbox_supported(struct dc *dc);
> >> bool dc_enable_dmub_notifications(struct dc *dc);
> >> diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
> >> index 31109db02e93..fb6a2d7b6470 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
> >> +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
> >> @@ -160,9 +160,7 @@ void dm_set_dcn_clocks(
> >> struct dc_context *ctx,
> >> struct dc_clocks *clks);
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable);
> >> -#endif
> >>
> >> void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz);
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
> >> index 951c9b60917d..26f3a55c35d7 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
> >> +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
> >> @@ -33,9 +33,7 @@
> >> #include "dc_bios_types.h"
> >> #include "mem_input.h"
> >> #include "hubp.h"
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> #include "mpc.h"
> >> -#endif
> >> #include "dwb.h"
> >> #include "mcif_wb.h"
> >> #include "panel_cntl.h"
> >> @@ -181,7 +179,6 @@ struct resource_funcs {
> >> void (*update_bw_bounding_box)(
> >> struct dc *dc,
> >> struct clk_bw_params *bw_params);
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool (*acquire_post_bldn_3dlut)(
> >> struct resource_context *res_ctx,
> >> const struct resource_pool *pool,
> >> @@ -194,7 +191,7 @@ struct resource_funcs {
> >> const struct resource_pool *pool,
> >> struct dc_3dlut **lut,
> >> struct dc_transfer_func **shaper);
> >> -#endif
> >> +
> >> enum dc_status (*add_dsc_to_stream_resource)(
> >> struct dc *dc, struct dc_state *state,
> >> struct dc_stream_state *stream);
> >> @@ -254,10 +251,9 @@ struct resource_pool {
> >> struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
> >> unsigned int hpo_dp_link_enc_count;
> >> struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> struct dc_3dlut *mpc_lut[MAX_PIPES];
> >> struct dc_transfer_func *mpc_shaper[MAX_PIPES];
> >> -#endif
> >> +
> >> struct {
> >> unsigned int xtalin_clock_inKhz;
> >> unsigned int dccg_ref_clock_inKhz;
> >> @@ -286,9 +282,7 @@ struct resource_pool {
> >> struct dmcu *dmcu;
> >> struct dmub_psr *psr;
> >>
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> struct abm *multiple_abms[MAX_PIPES];
> >> -#endif
> >>
> >> const struct resource_funcs *funcs;
> >> const struct resource_caps *res_cap;
> >> @@ -380,7 +374,6 @@ struct pipe_ctx {
> >> struct pipe_ctx *next_odm_pipe;
> >> struct pipe_ctx *prev_odm_pipe;
> >>
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> struct _vcs_dpi_display_dlg_regs_st dlg_regs;
> >> struct _vcs_dpi_display_ttu_regs_st ttu_regs;
> >> struct _vcs_dpi_display_rq_regs_st rq_regs;
> >> @@ -390,7 +383,7 @@ struct pipe_ctx {
> >> struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
> >> int det_buffer_size_kb;
> >> bool unbounded_req;
> >> -#endif
> >> +
> >> union pipe_update_flags update_flags;
> >> struct dwbc *dwbc;
> >> struct mcif_wb *mcif_wb;
> >> @@ -419,9 +412,7 @@ struct resource_context {
> >> bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
> >> unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
> >> int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
> >> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> >> bool is_mpc_3dlut_acquired[MAX_PIPES];
> >> -#endif
> >> };
> >>
> >> struct dce_bw_output {
> >> @@ -484,9 +475,7 @@ struct dc_state {
> >>
> >> /* Note: these are big structures, do *not* put on stack! */
> >> struct dm_pp_display_configuration pp_display_cfg;
> >> -#ifdef CONFIG_DRM_AMD_DC_DCN
> >> struct dcn_bw_internal_vars dcn_bw_vars;
> >> -#endif
> >>
> >> struct clk_mgr *clk_mgr;
> >>
> >> --
> >> 2.35.1
> >>
>
^ permalink raw reply [flat|nested] 29+ messages in thread* RE: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
2022-05-06 17:12 ` Rodrigo Siqueira Jordao
2022-05-06 18:00 ` Alex Deucher
@ 2022-05-07 7:39 ` Cui, Flora
2022-05-09 11:57 ` VURDIGERENATARAJ, CHANDAN
1 sibling, 1 reply; 29+ messages in thread
From: Cui, Flora @ 2022-05-07 7:39 UTC (permalink / raw)
To: Siqueira, Rodrigo, Alex Deucher, Hung, Alex, Wang, Chao-kai (Stylon)
Cc: Li, Sun peng (Leo), Wentland, Harry, Zhuo, Qingqing (Lillian),
Li, Roman, amd-gfx list, Chiu, Solomon, Pillai, Aurabindo, Lin,
Wayne, Lakha, Bhawanpreet, Gutierrez, Agustin, Kotarac, Pavle
[AMD Official Use Only - General]
What about arm?
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Rodrigo Siqueira Jordao
Sent: 2022年5月7日 1:13
To: Alex Deucher <alexdeucher@gmail.com>; Hung, Alex <Alex.Hung@amd.com>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>
Cc: Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Li, Roman <Roman.Li@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Chiu, Solomon <Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
Subject: Re: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
On 2022-05-06 11:56, Alex Deucher wrote:
> On Fri, May 6, 2022 at 11:43 AM Stylon Wang <stylon.wang@amd.com> wrote:
>>
>> From: Alex Hung <alex.hung@amd.com>
>>
>> [Why & How]
>> CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
>> code should be OS-agnostic.
>>
>> This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
>> in dc and dc/core directories.
>>
>> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>> Acked-by: Stylon Wang <stylon.wang@amd.com>
>> Signed-off-by: Alex Hung <alex.hung@amd.com>
>
> I presume the driver still builds properly on configs where
> CONFIG_DRM_AMD_DC_DCN is not set? E.g., platforms without floating
> point for example?
>
Hi Alex,
This is part of our effort to isolate FPU code inside DML (right now, we
are only missing DCN30); since we are really close to that, many of
these guards become useless. All of these patches were tested in our CI
against:
1. x86 with DCN
2. x86 without DCN
3. Clang
4. make allmodconfig
Additionally, I think that Alex Hung also checked the compilation with
PowerPC.
Thanks
Siqueira
> Alex
>
>> ---
>> drivers/gpu/drm/amd/display/dc/Makefile | 2 -
>> .../display/dc/bios/command_table_helper2.c | 3 +-
>> drivers/gpu/drm/amd/display/dc/core/dc.c | 31 ++--------------
>> .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 -
>> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -
>> .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 --
>> .../drm/amd/display/dc/core/dc_link_dpia.c | 2 -
>> .../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ++---------
>> .../gpu/drm/amd/display/dc/core/dc_stream.c | 8 ----
>> drivers/gpu/drm/amd/display/dc/dc.h | 37 -------------------
>> drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 -
>> .../gpu/drm/amd/display/dc/inc/core_types.h | 17 ++-------
>> 12 files changed, 10 insertions(+), 121 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
>> index f05ab2bf20c5..b4eca0236435 100644
>> --- a/drivers/gpu/drm/amd/display/dc/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
>> @@ -63,9 +63,7 @@ DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink
>> dc_surface.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
>> dc_link_enc_cfg.o dc_link_dpia.o dc_link_dpcd.o
>>
>> -ifdef CONFIG_DRM_AMD_DC_DCN
>> DISPLAY_CORE += dc_vm_helper.o
>> -endif
>>
>> AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> index dd9704ef4ccc..f3792286f571 100644
>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> @@ -65,7 +65,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>> case DCE_VERSION_12_1:
>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>> return true;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> case DCN_VERSION_1_0:
>> case DCN_VERSION_1_01:
>> case DCN_VERSION_2_0:
>> @@ -80,7 +79,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>> case DCN_VERSION_3_16:
>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>> return true;
>> -#endif
>> +
>> default:
>> /* Unsupported DCE */
>> BREAK_TO_DEBUGGER();
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> index c2fcd67bcc4d..1eeea7c184ae 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> @@ -829,14 +829,12 @@ static void dc_destruct(struct dc *dc)
>> kfree(dc->bw_dceip);
>> dc->bw_dceip = NULL;
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> kfree(dc->dcn_soc);
>> dc->dcn_soc = NULL;
>>
>> kfree(dc->dcn_ip);
>> dc->dcn_ip = NULL;
>>
>> -#endif
>> kfree(dc->vm_helper);
>> dc->vm_helper = NULL;
>>
>> @@ -882,10 +880,8 @@ static bool dc_construct(struct dc *dc,
>> struct dc_context *dc_ctx;
>> struct bw_calcs_dceip *dc_dceip;
>> struct bw_calcs_vbios *dc_vbios;
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> struct dcn_soc_bounding_box *dcn_soc;
>> struct dcn_ip_params *dcn_ip;
>> -#endif
>>
>> dc->config = init_params->flags;
>>
>> @@ -913,7 +909,6 @@ static bool dc_construct(struct dc *dc,
>> }
>>
>> dc->bw_vbios = dc_vbios;
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
>> if (!dcn_soc) {
>> dm_error("%s: failed to create dcn_soc\n", __func__);
>> @@ -929,7 +924,6 @@ static bool dc_construct(struct dc *dc,
>> }
>>
>> dc->dcn_ip = dcn_ip;
>> -#endif
>>
>> if (!dc_construct_ctx(dc, init_params)) {
>> dm_error("%s: failed to create ctx\n", __func__);
>> @@ -1868,7 +1862,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
>> return (result == DC_OK);
>> }
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool dc_acquire_release_mpc_3dlut(
>> struct dc *dc, bool acquire,
>> struct dc_stream_state *stream,
>> @@ -1904,7 +1897,7 @@ bool dc_acquire_release_mpc_3dlut(
>> }
>> return ret;
>> }
>> -#endif
>> +
>> static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
>> {
>> int i;
>> @@ -1925,7 +1918,6 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
>> return false;
>> }
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> /* Perform updates here which need to be deferred until next vupdate
>> *
>> * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
>> @@ -1944,7 +1936,6 @@ static void process_deferred_updates(struct dc *dc)
>> dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
>> }
>> }
>> -#endif /* CONFIG_DRM_AMD_DC_DCN */
>>
>> void dc_post_update_surfaces_to_stream(struct dc *dc)
>> {
>> @@ -1971,9 +1962,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
>> dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
>> }
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> process_deferred_updates(dc);
>> -#endif
>>
>> dc->hwss.optimize_bandwidth(dc, context);
>>
>> @@ -1987,9 +1976,7 @@ static void init_state(struct dc *dc, struct dc_state *context)
>> * initialize and obtain IP and SOC the base DML instance from DC is
>> * initially copied into every context
>> */
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
>> -#endif
>> }
>>
>> struct dc_state *dc_create_state(struct dc *dc)
>> @@ -2361,11 +2348,9 @@ static enum surface_update_type check_update_surfaces_for_stream(
>> int i;
>> enum surface_update_type overall_type = UPDATE_TYPE_FAST;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> if (dc->idle_optimizations_allowed)
>> overall_type = UPDATE_TYPE_FULL;
>>
>> -#endif
>> if (stream_status == NULL || stream_status->plane_count != surface_count)
>> overall_type = UPDATE_TYPE_FULL;
>>
>> @@ -2874,10 +2859,8 @@ static void commit_planes_for_stream(struct dc *dc,
>> }
>>
>> if (update_type == UPDATE_TYPE_FULL) {
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> dc_allow_idle_optimizations(dc, false);
>>
>> -#endif
>> if (get_seamless_boot_stream_count(context) == 0)
>> dc->hwss.prepare_bandwidth(dc, context);
>>
>> @@ -2895,7 +2878,6 @@ static void commit_planes_for_stream(struct dc *dc,
>> }
>> }
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
>> struct pipe_ctx *mpcc_pipe;
>> struct pipe_ctx *odm_pipe;
>> @@ -2904,7 +2886,6 @@ static void commit_planes_for_stream(struct dc *dc,
>> for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>> odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
>> }
>> -#endif
>>
>> if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
>> if (top_pipe_to_program &&
>> @@ -3014,7 +2995,6 @@ static void commit_planes_for_stream(struct dc *dc,
>> }
>> if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
>> dc->hwss.program_front_end_for_ctx(dc, context);
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> if (dc->debug.validate_dml_output) {
>> for (i = 0; i < dc->res_pool->pipe_count; i++) {
>> struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
>> @@ -3028,7 +3008,6 @@ static void commit_planes_for_stream(struct dc *dc,
>> &context->res_ctx.pipe_ctx[i].ttu_regs);
>> }
>> }
>> -#endif
>> }
>>
>> // Update Type FAST, Surface updates
>> @@ -3583,8 +3562,6 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)
>> return true;
>> }
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> -
>> void dc_allow_idle_optimizations(struct dc *dc, bool allow)
>> {
>> if (dc->debug.disable_idle_power_optimizations)
>> @@ -3740,7 +3717,6 @@ void dc_hardware_release(struct dc *dc)
>> if (dc->hwss.hardware_release)
>> dc->hwss.hardware_release(dc);
>> }
>> -#endif
>>
>> /*
>> *****************************************************************************
>> @@ -3760,13 +3736,12 @@ void dc_hardware_release(struct dc *dc)
>> */
>> bool dc_is_dmub_outbox_supported(struct dc *dc)
>> {
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> - /* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */
>> + /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
>> if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
>> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
>> !dc->debug.dpia_debug.bits.disable_dpia)
>> return true;
>> -#endif
>> +
>> /* dmub aux needs dmub notifications to be enabled */
>> return dc->debug.enable_dmub_aux_for_legacy_ddc;
>> }
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>> index 643762542e4d..72376075db0c 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>> @@ -345,7 +345,6 @@ void context_clock_trace(
>> struct dc *dc,
>> struct dc_state *context)
>> {
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> DC_LOGGER_INIT(dc->ctx->logger);
>> CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
>> "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
>> @@ -363,7 +362,6 @@ void context_clock_trace(
>> context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
>> context->bw_ctx.bw.dcn.clk.fclk_khz,
>> context->bw_ctx.bw.dcn.clk.socclk_khz);
>> -#endif
>> }
>>
>> /**
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>> index 07f154fc4e56..9529b924742e 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>> @@ -804,7 +804,6 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
>>
>> static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>> {
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
>> * reports DSC support.
>> */
>> @@ -815,7 +814,6 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>> link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
>> !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
>> link->wa_flags.dpia_mst_dsc_always_on = true;
>> -#endif
>> }
>>
>> static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> index 5e49e346aa06..975d631534b5 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> @@ -5127,12 +5127,10 @@ void dp_retrieve_lttpr_cap(struct dc_link *link)
>> else
>> link->lttpr_support = LTTPR_CHECK_EXT_SUPPORT;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* Check DP tunnel LTTPR mode debug option. */
>> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
>> link->dc->debug.dpia_debug.bits.force_non_lttpr)
>> link->lttpr_support = LTTPR_UNSUPPORTED;
>> -#endif
>>
>> if (link->lttpr_support > LTTPR_UNSUPPORTED) {
>> /* By reading LTTPR capability, RX assumes that we will enable
>> @@ -5626,9 +5624,7 @@ static bool retrieve_link_cap(struct dc_link *link)
>> * only if required.
>> */
>> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> !link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around &&
>> -#endif
>> link->dpcd_caps.is_branch_dev &&
>> link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
>> link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>> index 0e95bc5df4e7..a5765f36d86f 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>> @@ -547,11 +547,9 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link,
>> dp_translate_training_aux_read_interval(
>> link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* Check debug option for extending aux read interval. */
>> if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
>> wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
>> -#endif
>>
>> return wait_time_microsec;
>> }
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> index 147c6a3c6312..f702919a2279 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> @@ -56,7 +56,6 @@
>> #include "dce110/dce110_resource.h"
>> #include "dce112/dce112_resource.h"
>> #include "dce120/dce120_resource.h"
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> #include "dcn10/dcn10_resource.h"
>> #include "dcn20/dcn20_resource.h"
>> #include "dcn21/dcn21_resource.h"
>> @@ -68,7 +67,6 @@
>> #include "dcn31/dcn31_resource.h"
>> #include "dcn315/dcn315_resource.h"
>> #include "dcn316/dcn316_resource.h"
>> -#endif
>>
>> #define DC_LOGGER_INIT(logger)
>>
>> @@ -124,7 +122,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>> else
>> dc_version = DCE_VERSION_12_0;
>> break;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> case FAMILY_RV:
>> dc_version = DCN_VERSION_1_0;
>> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
>> @@ -165,7 +162,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>> if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
>> dc_version = DCN_VERSION_3_16;
>> break;
>> -#endif
>>
>> default:
>> dc_version = DCE_VERSION_UNKNOWN;
>> @@ -397,7 +393,6 @@ bool resource_construct(
>> }
>> }
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> for (i = 0; i < caps->num_mpc_3dlut; i++) {
>> pool->mpc_lut[i] = dc_create_3dlut_func();
>> if (pool->mpc_lut[i] == NULL)
>> @@ -406,7 +401,7 @@ bool resource_construct(
>> if (pool->mpc_shaper[i] == NULL)
>> DC_ERR("DC: failed to create MPC shaper!\n");
>> }
>> -#endif
>> +
>> dc->caps.dynamic_audio = false;
>> if (pool->audio_count < pool->stream_enc_count) {
>> dc->caps.dynamic_audio = true;
>> @@ -1369,7 +1364,6 @@ static struct pipe_ctx *acquire_free_pipe_for_head(
>> return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
>> }
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> static int acquire_first_split_pipe(
>> struct resource_context *res_ctx,
>> const struct resource_pool *pool,
>> @@ -1404,7 +1398,6 @@ static int acquire_first_split_pipe(
>> }
>> return -1;
>> }
>> -#endif
>>
>> bool dc_add_plane_to_context(
>> const struct dc *dc,
>> @@ -1447,13 +1440,12 @@ bool dc_add_plane_to_context(
>> while (head_pipe) {
>> free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
>>
>> - #if defined(CONFIG_DRM_AMD_DC_DCN)
>> if (!free_pipe) {
>> int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
>> if (pipe_idx >= 0)
>> free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
>> }
>> - #endif
>> +
>> if (!free_pipe) {
>> dc_plane_state_release(plane_state);
>> return false;
>> @@ -2259,10 +2251,8 @@ enum dc_status resource_map_pool_resources(
>> /* acquire new resources */
>> pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> if (pipe_idx < 0)
>> pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
>> -#endif
>>
>> if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
>> return DC_NO_CONTROLLER_RESOURCE;
>> @@ -2453,7 +2443,6 @@ enum dc_status dc_validate_global_state(
>> if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
>> result = DC_FAIL_BANDWIDTH_VALIDATE;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /*
>> * Only update link encoder to stream assignment after bandwidth validation passed.
>> * TODO: Split out assignment and validation.
>> @@ -2461,7 +2450,6 @@ enum dc_status dc_validate_global_state(
>> if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
>> dc->res_pool->funcs->link_encs_assign(
>> dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
>> -#endif
>>
>> return result;
>> }
>> @@ -3189,10 +3177,8 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
>> case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
>> case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
>> -#endif
>> return 32;
>> case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
>> @@ -3345,7 +3331,6 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
>> /* TODO - get transmitter to phy idx mapping from DMUB */
>> uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
>> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
>> switch (transmitter) {
>> @@ -3369,7 +3354,7 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
>> break;
>> }
>> }
>> -#endif
>> +
>> return phy_idx;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>> index c4e871f358ab..acca35d86c10 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>> @@ -314,9 +314,7 @@ bool dc_stream_set_cursor_attributes(
>> const struct dc_cursor_attributes *attributes)
>> {
>> struct dc *dc;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool reset_idle_optimizations = false;
>> -#endif
>>
>> if (NULL == stream) {
>> dm_error("DC: dc_stream is NULL!\n");
>> @@ -346,12 +344,10 @@ bool dc_stream_set_cursor_attributes(
>> #endif
>> program_cursor_attributes(dc, stream, attributes);
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* re-enable idle optimizations if necessary */
>> if (reset_idle_optimizations)
>> dc_allow_idle_optimizations(dc, true);
>>
>> -#endif
>> return true;
>> }
>>
>> @@ -396,9 +392,7 @@ bool dc_stream_set_cursor_position(
>> const struct dc_cursor_position *position)
>> {
>> struct dc *dc;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool reset_idle_optimizations = false;
>> -#endif
>>
>> if (NULL == stream) {
>> dm_error("DC: dc_stream is NULL!\n");
>> @@ -424,12 +418,10 @@ bool dc_stream_set_cursor_position(
>> stream->cursor_position = *position;
>>
>> program_cursor_position(dc, stream, position);
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> /* re-enable idle optimizations if necessary */
>> if (reset_idle_optimizations)
>> dc_allow_idle_optimizations(dc, true);
>>
>> -#endif
>> return true;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
>> index e37d9c19f089..0f86bb809e04 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dc.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
>> @@ -222,7 +222,6 @@ struct dc_dcc_setting {
>> unsigned int max_compressed_blk_size;
>> unsigned int max_uncompressed_blk_size;
>> bool independent_64b_blks;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> //These bitfields to be used starting with DCN
>> struct {
>> uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
>> @@ -230,7 +229,6 @@ struct dc_dcc_setting {
>> uint32_t dcc_256_128_128 : 1; //available starting with DCN
>> uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
>> } dcc_controls;
>> -#endif
>> };
>>
>> struct dc_surface_dcc_cap {
>> @@ -332,9 +330,7 @@ struct dc_config {
>> bool enable_4to1MPC;
>> bool enable_windowed_mpo_odm;
>> bool allow_edp_hotplug_detection;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool clamp_min_dcfclk;
>> -#endif
>> uint64_t vblank_alignment_dto_params;
>> uint8_t vblank_alignment_max_frame_time_diff;
>> bool is_asymmetric_memory;
>> @@ -395,14 +391,12 @@ enum dcn_pwr_state {
>> DCN_PWR_STATE_LOW_POWER = 3,
>> };
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> enum dcn_zstate_support_state {
>> DCN_ZSTATE_SUPPORT_UNKNOWN,
>> DCN_ZSTATE_SUPPORT_ALLOW,
>> DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
>> DCN_ZSTATE_SUPPORT_DISALLOW,
>> };
>> -#endif
>> /*
>> * For any clocks that may differ per pipe
>> * only the max is stored in this structure
>> @@ -420,10 +414,8 @@ struct dc_clocks {
>> int phyclk_khz;
>> int dramclk_khz;
>> bool p_state_change_support;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> enum dcn_zstate_support_state zstate_support;
>> bool dtbclk_en;
>> -#endif
>> enum dcn_pwr_state pwr_state;
>> /*
>> * Elements below are not compared for the purposes of
>> @@ -653,9 +645,7 @@ struct dc_debug_options {
>> bool disable_pplib_clock_request;
>> bool disable_clock_gate;
>> bool disable_mem_low_power;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool pstate_enabled;
>> -#endif
>> bool disable_dmcu;
>> bool disable_psr;
>> bool force_abm_enable;
>> @@ -673,20 +663,16 @@ struct dc_debug_options {
>> bool remove_disconnect_edp;
>> unsigned int force_odm_combine; //bit vector based on otg inst
>> unsigned int seamless_boot_odm_combine;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> unsigned int force_odm_combine_4to1; //bit vector based on otg inst
>> bool disable_z9_mpc;
>> -#endif
>> unsigned int force_fclk_khz;
>> bool enable_tri_buf;
>> bool dmub_offload_enabled;
>> bool dmcub_emulation;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool disable_idle_power_optimizations;
>> unsigned int mall_size_override;
>> unsigned int mall_additional_timer_percent;
>> bool mall_error_as_fatal;
>> -#endif
>> bool dmub_command_table; /* for testing only */
>> struct dc_bw_validation_profile bw_val_profile;
>> bool disable_fec;
>> @@ -695,9 +681,7 @@ struct dc_debug_options {
>> * watermarks are not affected.
>> */
>> unsigned int force_min_dcfclk_mhz;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> int dwb_fi_phase;
>> -#endif
>> bool disable_timing_sync;
>> bool cm_in_bypass;
>> int force_clock_mode;/*every mode change.*/
>> @@ -729,11 +713,9 @@ struct dc_debug_options {
>> enum det_size crb_alloc_policy;
>> int crb_alloc_policy_min_disp_count;
>> bool disable_z10;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool enable_z9_disable_interface;
>> bool enable_sw_cntl_psr;
>> union dpia_debug_options dpia_debug;
>> -#endif
>> bool apply_vendor_specific_lttpr_wa;
>> bool extended_blank_optimization;
>> union aux_wake_wa_options aux_wake_wa;
>> @@ -767,11 +749,9 @@ struct dc {
>> /* Inputs into BW and WM calculations. */
>> struct bw_calcs_dceip *bw_dceip;
>> struct bw_calcs_vbios *bw_vbios;
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> struct dcn_soc_bounding_box *dcn_soc;
>> struct dcn_ip_params *dcn_ip;
>> struct display_mode_lib dml;
>> -#endif
>>
>> /* HW functions */
>> struct hw_sequencer_funcs hwss;
>> @@ -780,12 +760,8 @@ struct dc {
>> /* Require to optimize clocks and bandwidth for added/removed planes */
>> bool optimized_required;
>> bool wm_optimized_required;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool idle_optimizations_allowed;
>> -#endif
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool enable_c20_dtm_b0;
>> -#endif
>>
>> /* Require to maintain clocks and bandwidth for UEFI enabled HW */
>>
>> @@ -835,9 +811,7 @@ struct dc_init_data {
>> uint64_t log_mask;
>>
>> struct dpcd_vendor_signature vendor_signature;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool force_smu_not_present;
>> -#endif
>> };
>>
>> struct dc_callback_init {
>> @@ -1030,9 +1004,7 @@ struct dc_plane_state {
>> struct dc_transfer_func *in_shaper_func;
>> struct dc_transfer_func *blend_tf;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> struct dc_transfer_func *gamcor_tf;
>> -#endif
>> enum surface_pixel_format format;
>> enum dc_rotation_angle rotation;
>> enum plane_stereo_format stereo_format;
>> @@ -1169,13 +1141,11 @@ void dc_resource_state_construct(
>> const struct dc *dc,
>> struct dc_state *dst_ctx);
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool dc_acquire_release_mpc_3dlut(
>> struct dc *dc, bool acquire,
>> struct dc_stream_state *stream,
>> struct dc_3dlut **lut,
>> struct dc_transfer_func **shaper);
>> -#endif
>>
>> void dc_resource_state_copy_construct(
>> const struct dc_state *src_ctx,
>> @@ -1306,10 +1276,8 @@ struct hdcp_caps {
>>
>> #include "dc_link.h"
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
>>
>> -#endif
>> /*******************************************************************************
>> * Sink Interfaces - A sink corresponds to a display output device
>> ******************************************************************************/
>> @@ -1433,7 +1401,6 @@ bool dc_is_dmcu_initialized(struct dc *dc);
>>
>> enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
>> void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>
>> bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
>> struct dc_cursor_attributes *cursor_attr);
>> @@ -1458,13 +1425,9 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
>> /* cleanup on driver unload */
>> void dc_hardware_release(struct dc *dc);
>>
>> -#endif
>> -
>> bool dc_set_psr_allow_active(struct dc *dc, bool enable);
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> void dc_z10_restore(const struct dc *dc);
>> void dc_z10_save_init(struct dc *dc);
>> -#endif
>>
>> bool dc_is_dmub_outbox_supported(struct dc *dc);
>> bool dc_enable_dmub_notifications(struct dc *dc);
>> diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>> index 31109db02e93..fb6a2d7b6470 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>> @@ -160,9 +160,7 @@ void dm_set_dcn_clocks(
>> struct dc_context *ctx,
>> struct dc_clocks *clks);
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable);
>> -#endif
>>
>> void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz);
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>> index 951c9b60917d..26f3a55c35d7 100644
>> --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>> +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>> @@ -33,9 +33,7 @@
>> #include "dc_bios_types.h"
>> #include "mem_input.h"
>> #include "hubp.h"
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> #include "mpc.h"
>> -#endif
>> #include "dwb.h"
>> #include "mcif_wb.h"
>> #include "panel_cntl.h"
>> @@ -181,7 +179,6 @@ struct resource_funcs {
>> void (*update_bw_bounding_box)(
>> struct dc *dc,
>> struct clk_bw_params *bw_params);
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool (*acquire_post_bldn_3dlut)(
>> struct resource_context *res_ctx,
>> const struct resource_pool *pool,
>> @@ -194,7 +191,7 @@ struct resource_funcs {
>> const struct resource_pool *pool,
>> struct dc_3dlut **lut,
>> struct dc_transfer_func **shaper);
>> -#endif
>> +
>> enum dc_status (*add_dsc_to_stream_resource)(
>> struct dc *dc, struct dc_state *state,
>> struct dc_stream_state *stream);
>> @@ -254,10 +251,9 @@ struct resource_pool {
>> struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
>> unsigned int hpo_dp_link_enc_count;
>> struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> struct dc_3dlut *mpc_lut[MAX_PIPES];
>> struct dc_transfer_func *mpc_shaper[MAX_PIPES];
>> -#endif
>> +
>> struct {
>> unsigned int xtalin_clock_inKhz;
>> unsigned int dccg_ref_clock_inKhz;
>> @@ -286,9 +282,7 @@ struct resource_pool {
>> struct dmcu *dmcu;
>> struct dmub_psr *psr;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> struct abm *multiple_abms[MAX_PIPES];
>> -#endif
>>
>> const struct resource_funcs *funcs;
>> const struct resource_caps *res_cap;
>> @@ -380,7 +374,6 @@ struct pipe_ctx {
>> struct pipe_ctx *next_odm_pipe;
>> struct pipe_ctx *prev_odm_pipe;
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> struct _vcs_dpi_display_dlg_regs_st dlg_regs;
>> struct _vcs_dpi_display_ttu_regs_st ttu_regs;
>> struct _vcs_dpi_display_rq_regs_st rq_regs;
>> @@ -390,7 +383,7 @@ struct pipe_ctx {
>> struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
>> int det_buffer_size_kb;
>> bool unbounded_req;
>> -#endif
>> +
>> union pipe_update_flags update_flags;
>> struct dwbc *dwbc;
>> struct mcif_wb *mcif_wb;
>> @@ -419,9 +412,7 @@ struct resource_context {
>> bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
>> unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
>> int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>> bool is_mpc_3dlut_acquired[MAX_PIPES];
>> -#endif
>> };
>>
>> struct dce_bw_output {
>> @@ -484,9 +475,7 @@ struct dc_state {
>>
>> /* Note: these are big structures, do *not* put on stack! */
>> struct dm_pp_display_configuration pp_display_cfg;
>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>> struct dcn_bw_internal_vars dcn_bw_vars;
>> -#endif
>>
>> struct clk_mgr *clk_mgr;
>>
>> --
>> 2.35.1
>>
^ permalink raw reply [flat|nested] 29+ messages in thread* RE: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
2022-05-07 7:39 ` Cui, Flora
@ 2022-05-09 11:57 ` VURDIGERENATARAJ, CHANDAN
2022-05-09 13:22 ` Rodrigo Siqueira Jordao
0 siblings, 1 reply; 29+ messages in thread
From: VURDIGERENATARAJ, CHANDAN @ 2022-05-09 11:57 UTC (permalink / raw)
To: Cui, Flora, Siqueira, Rodrigo, Alex Deucher, Hung, Alex, Wang,
Chao-kai (Stylon)
Cc: Li, Sun peng (Leo), Lakha, Bhawanpreet, Zhuo, Qingqing (Lillian),
Li, Roman, amd-gfx list, Chiu, Solomon, Pillai, Aurabindo, Lin,
Wayne, Wentland, Harry, Gutierrez, Agustin, Kotarac, Pavle
Hi,
Changes are not needed in " drivers/gpu/drm/amd/display/Kconfig" ??
Also, is this change validated on Chrome?
BR,
Chandan V N
>What about arm?
>
>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Rodrigo Siqueira Jordao
>Sent: 2022年5月7日 1:13
>To: Alex Deucher <alexdeucher@gmail.com>; Hung, Alex <Alex.Hung@amd.com>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>
>Cc: Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Li, Roman <Roman.Li@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Chiu, Solomon ><Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
>Subject: Re: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
>
>
>
>On 2022-05-06 11:56, Alex Deucher wrote:
>> On Fri, May 6, 2022 at 11:43 AM Stylon Wang <stylon.wang@amd.com> wrote:
>>>
>>> From: Alex Hung <alex.hung@amd.com>
>>>
>>> [Why & How]
>>> CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but
>>> DC code should be OS-agnostic.
>>>
>>> This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN in
>>> dc and dc/core directories.
>>>
>>> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>> Acked-by: Stylon Wang <stylon.wang@amd.com>
>>> Signed-off-by: Alex Hung <alex.hung@amd.com>
>>
>> I presume the driver still builds properly on configs where
>> CONFIG_DRM_AMD_DC_DCN is not set? E.g., platforms without floating
>> point for example?
>>
>
>Hi Alex,
>
>This is part of our effort to isolate FPU code inside DML (right now, we are only missing DCN30); since we are really close to that, many of these guards become useless. All of these patches were tested in our CI
>against:
>
>1. x86 with DCN
>2. x86 without DCN
>3. Clang
>4. make allmodconfig
>
>Additionally, I think that Alex Hung also checked the compilation with PowerPC.
>
>Thanks
>Siqueira
>
>
>> Alex
>>
>>> ---
>>> drivers/gpu/drm/amd/display/dc/Makefile | 2 -
>>> .../display/dc/bios/command_table_helper2.c | 3 +-
>>> drivers/gpu/drm/amd/display/dc/core/dc.c | 31 ++--------------
>>> .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 -
>>> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -
>>> .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 --
>>> .../drm/amd/display/dc/core/dc_link_dpia.c | 2 -
>>> .../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ++---------
>>> .../gpu/drm/amd/display/dc/core/dc_stream.c | 8 ----
>>> drivers/gpu/drm/amd/display/dc/dc.h | 37 -------------------
>>> drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 -
>>> .../gpu/drm/amd/display/dc/inc/core_types.h | 17 ++-------
>>> 12 files changed, 10 insertions(+), 121 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/Makefile
>>> index f05ab2bf20c5..b4eca0236435 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
>>> @@ -63,9 +63,7 @@ DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink
>>> dc_surface.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
>>> dc_link_enc_cfg.o dc_link_dpia.o dc_link_dpcd.o
>>>
>>> -ifdef CONFIG_DRM_AMD_DC_DCN
>>> DISPLAY_CORE += dc_vm_helper.o
>>> -endif
>>>
>>> AMD_DISPLAY_CORE = $(addprefix
>>> $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
>>>
>>> diff --git
>>> a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>> index dd9704ef4ccc..f3792286f571 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>> @@ -65,7 +65,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>>> case DCE_VERSION_12_1:
>>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>>> return true;
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> case DCN_VERSION_1_0:
>>> case DCN_VERSION_1_01:
>>> case DCN_VERSION_2_0:
>>> @@ -80,7 +79,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>>> case DCN_VERSION_3_16:
>>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>>> return true;
>>> -#endif
>>> +
>>> default:
>>> /* Unsupported DCE */
>>> BREAK_TO_DEBUGGER(); diff --git
>>> a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> index c2fcd67bcc4d..1eeea7c184ae 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> @@ -829,14 +829,12 @@ static void dc_destruct(struct dc *dc)
>>> kfree(dc->bw_dceip);
>>> dc->bw_dceip = NULL;
>>>
>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>> kfree(dc->dcn_soc);
>>> dc->dcn_soc = NULL;
>>>
>>> kfree(dc->dcn_ip);
>>> dc->dcn_ip = NULL;
>>>
>>> -#endif
>>> kfree(dc->vm_helper);
>>> dc->vm_helper = NULL;
>>>
>>> @@ -882,10 +880,8 @@ static bool dc_construct(struct dc *dc,
>>> struct dc_context *dc_ctx;
>>> struct bw_calcs_dceip *dc_dceip;
>>> struct bw_calcs_vbios *dc_vbios; -#ifdef
>>> CONFIG_DRM_AMD_DC_DCN
>>> struct dcn_soc_bounding_box *dcn_soc;
>>> struct dcn_ip_params *dcn_ip; -#endif
>>>
>>> dc->config = init_params->flags;
>>>
>>> @@ -913,7 +909,6 @@ static bool dc_construct(struct dc *dc,
>>> }
>>>
>>> dc->bw_vbios = dc_vbios;
>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>> dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
>>> if (!dcn_soc) {
>>> dm_error("%s: failed to create dcn_soc\n",
>>> __func__); @@ -929,7 +924,6 @@ static bool dc_construct(struct dc *dc,
>>> }
>>>
>>> dc->dcn_ip = dcn_ip;
>>> -#endif
>>>
>>> if (!dc_construct_ctx(dc, init_params)) {
>>> dm_error("%s: failed to create ctx\n", __func__); @@
>>> -1868,7 +1862,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
>>> return (result == DC_OK);
>>> }
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool dc_acquire_release_mpc_3dlut(
>>> struct dc *dc, bool acquire,
>>> struct dc_stream_state *stream, @@ -1904,7 +1897,7
>>> @@ bool dc_acquire_release_mpc_3dlut(
>>> }
>>> return ret;
>>> }
>>> -#endif
>>> +
>>> static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
>>> {
>>> int i;
>>> @@ -1925,7 +1918,6 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
>>> return false;
>>> }
>>>
>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>> /* Perform updates here which need to be deferred until next vupdate
>>> *
>>> * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double
>>> buffered @@ -1944,7 +1936,6 @@ static void process_deferred_updates(struct dc *dc)
>>> dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
>>> }
>>> }
>>> -#endif /* CONFIG_DRM_AMD_DC_DCN */
>>>
>>> void dc_post_update_surfaces_to_stream(struct dc *dc)
>>> {
>>> @@ -1971,9 +1962,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
>>> dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
>>> }
>>>
>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>> process_deferred_updates(dc); -#endif
>>>
>>> dc->hwss.optimize_bandwidth(dc, context);
>>>
>>> @@ -1987,9 +1976,7 @@ static void init_state(struct dc *dc, struct dc_state *context)
>>> * initialize and obtain IP and SOC the base DML instance from DC is
>>> * initially copied into every context
>>> */
>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>> memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct
>>> display_mode_lib)); -#endif
>>> }
>>>
>>> struct dc_state *dc_create_state(struct dc *dc) @@ -2361,11 +2348,9
>>> @@ static enum surface_update_type check_update_surfaces_for_stream(
>>> int i;
>>> enum surface_update_type overall_type = UPDATE_TYPE_FAST;
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> if (dc->idle_optimizations_allowed)
>>> overall_type = UPDATE_TYPE_FULL;
>>>
>>> -#endif
>>> if (stream_status == NULL || stream_status->plane_count != surface_count)
>>> overall_type = UPDATE_TYPE_FULL;
>>>
>>> @@ -2874,10 +2859,8 @@ static void commit_planes_for_stream(struct dc *dc,
>>> }
>>>
>>> if (update_type == UPDATE_TYPE_FULL) { -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> dc_allow_idle_optimizations(dc, false);
>>>
>>> -#endif
>>> if (get_seamless_boot_stream_count(context) == 0)
>>> dc->hwss.prepare_bandwidth(dc, context);
>>>
>>> @@ -2895,7 +2878,6 @@ static void commit_planes_for_stream(struct dc *dc,
>>> }
>>> }
>>>
>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>> if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
>>> struct pipe_ctx *mpcc_pipe;
>>> struct pipe_ctx *odm_pipe; @@ -2904,7 +2886,6 @@
>>> static void commit_planes_for_stream(struct dc *dc,
>>> for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>>> odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
>>> }
>>> -#endif
>>>
>>> if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
>>> if (top_pipe_to_program && @@ -3014,7 +2995,6 @@
>>> static void commit_planes_for_stream(struct dc *dc,
>>> }
>>> if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
>>> dc->hwss.program_front_end_for_ctx(dc, context);
>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>> if (dc->debug.validate_dml_output) {
>>> for (i = 0; i < dc->res_pool->pipe_count; i++) {
>>> struct pipe_ctx *cur_pipe =
>>> &context->res_ctx.pipe_ctx[i]; @@ -3028,7 +3008,6 @@ static void commit_planes_for_stream(struct dc *dc,
>>> &context->res_ctx.pipe_ctx[i].ttu_regs);
>>> }
>>> }
>>> -#endif
>>> }
>>>
>>> // Update Type FAST, Surface updates @@ -3583,8 +3562,6 @@
>>> bool dc_set_psr_allow_active(struct dc *dc, bool enable)
>>> return true;
>>> }
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> -
>>> void dc_allow_idle_optimizations(struct dc *dc, bool allow)
>>> {
>>> if (dc->debug.disable_idle_power_optimizations)
>>> @@ -3740,7 +3717,6 @@ void dc_hardware_release(struct dc *dc)
>>> if (dc->hwss.hardware_release)
>>> dc->hwss.hardware_release(dc);
>>> }
>>> -#endif
>>>
>>> /*
>>>
>>> *********************************************************************
>>> ******** @@ -3760,13 +3736,12 @@ void dc_hardware_release(struct dc
>>> *dc)
>>> */
>>> bool dc_is_dmub_outbox_supported(struct dc *dc)
>>> {
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> - /* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */
>>> + /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts
>>> + */
>>> if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
>>> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
>>> !dc->debug.dpia_debug.bits.disable_dpia)
>>> return true;
>>> -#endif
>>> +
>>> /* dmub aux needs dmub notifications to be enabled */
>>> return dc->debug.enable_dmub_aux_for_legacy_ddc;
>>> }
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>>> index 643762542e4d..72376075db0c 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>>> @@ -345,7 +345,6 @@ void context_clock_trace(
>>> struct dc *dc,
>>> struct dc_state *context)
>>> {
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> DC_LOGGER_INIT(dc->ctx->logger);
>>> CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
>>> "dcfclk_deep_sleep_khz:%d fclk_khz:%d
>>> socclk_khz:%d\n", @@ -363,7 +362,6 @@ void context_clock_trace(
>>> context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
>>> context->bw_ctx.bw.dcn.clk.fclk_khz,
>>> context->bw_ctx.bw.dcn.clk.socclk_khz);
>>> -#endif
>>> }
>>>
>>> /**
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>>> index 07f154fc4e56..9529b924742e 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>>> @@ -804,7 +804,6 @@ static bool wait_for_entering_dp_alt_mode(struct
>>> dc_link *link)
>>>
>>> static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>>> {
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
>>> * reports DSC support.
>>> */
>>> @@ -815,7 +814,6 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>>> link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
>>> !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
>>> link->wa_flags.dpia_mst_dsc_always_on = true;
>>> -#endif
>>> }
>>>
>>> static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> index 5e49e346aa06..975d631534b5 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>> @@ -5127,12 +5127,10 @@ void dp_retrieve_lttpr_cap(struct dc_link *link)
>>> else
>>> link->lttpr_support = LTTPR_CHECK_EXT_SUPPORT;
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> /* Check DP tunnel LTTPR mode debug option. */
>>> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
>>> link->dc->debug.dpia_debug.bits.force_non_lttpr)
>>> link->lttpr_support = LTTPR_UNSUPPORTED; -#endif
>>>
>>> if (link->lttpr_support > LTTPR_UNSUPPORTED) {
>>> /* By reading LTTPR capability, RX assumes that we
>>> will enable @@ -5626,9 +5624,7 @@ static bool retrieve_link_cap(struct dc_link *link)
>>> * only if required.
>>> */
>>> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>
>>> !link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around && -#endif
>>> link->dpcd_caps.is_branch_dev &&
>>> link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
>>> link->dpcd_caps.branch_hw_revision
>>> == DP_BRANCH_HW_REV_10 && diff --git
>>> a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>>> index 0e95bc5df4e7..a5765f36d86f 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>>> @@ -547,11 +547,9 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link,
>>> dp_translate_training_aux_read_interval(
>>>
>>> link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> /* Check debug option for extending aux read interval. */
>>> if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
>>> wait_time_microsec =
>>> DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
>>> -#endif
>>>
>>> return wait_time_microsec;
>>> }
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>> index 147c6a3c6312..f702919a2279 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>> @@ -56,7 +56,6 @@
>>> #include "dce110/dce110_resource.h"
>>> #include "dce112/dce112_resource.h"
>>> #include "dce120/dce120_resource.h"
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> #include "dcn10/dcn10_resource.h"
>>> #include "dcn20/dcn20_resource.h"
>>> #include "dcn21/dcn21_resource.h"
>>> @@ -68,7 +67,6 @@
>>> #include "dcn31/dcn31_resource.h"
>>> #include "dcn315/dcn315_resource.h"
>>> #include "dcn316/dcn316_resource.h"
>>> -#endif
>>>
>>> #define DC_LOGGER_INIT(logger)
>>>
>>> @@ -124,7 +122,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>>> else
>>> dc_version = DCE_VERSION_12_0;
>>> break;
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> case FAMILY_RV:
>>> dc_version = DCN_VERSION_1_0;
>>> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
>>> @@ -165,7 +162,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>>> if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
>>> dc_version = DCN_VERSION_3_16;
>>> break;
>>> -#endif
>>>
>>> default:
>>> dc_version = DCE_VERSION_UNKNOWN; @@ -397,7 +393,6
>>> @@ bool resource_construct(
>>> }
>>> }
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> for (i = 0; i < caps->num_mpc_3dlut; i++) {
>>> pool->mpc_lut[i] = dc_create_3dlut_func();
>>> if (pool->mpc_lut[i] == NULL) @@ -406,7 +401,7 @@
>>> bool resource_construct(
>>> if (pool->mpc_shaper[i] == NULL)
>>> DC_ERR("DC: failed to create MPC shaper!\n");
>>> }
>>> -#endif
>>> +
>>> dc->caps.dynamic_audio = false;
>>> if (pool->audio_count < pool->stream_enc_count) {
>>> dc->caps.dynamic_audio = true; @@ -1369,7 +1364,6 @@
>>> static struct pipe_ctx *acquire_free_pipe_for_head(
>>> return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
>>> }
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> static int acquire_first_split_pipe(
>>> struct resource_context *res_ctx,
>>> const struct resource_pool *pool, @@ -1404,7 +1398,6
>>> @@ static int acquire_first_split_pipe(
>>> }
>>> return -1;
>>> }
>>> -#endif
>>>
>>> bool dc_add_plane_to_context(
>>> const struct dc *dc, @@ -1447,13 +1440,12 @@ bool
>>> dc_add_plane_to_context(
>>> while (head_pipe) {
>>> free_pipe = acquire_free_pipe_for_head(context,
>>> pool, head_pipe);
>>>
>>> - #if defined(CONFIG_DRM_AMD_DC_DCN)
>>> if (!free_pipe) {
>>> int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
>>> if (pipe_idx >= 0)
>>> free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
>>> }
>>> - #endif
>>> +
>>> if (!free_pipe) {
>>> dc_plane_state_release(plane_state);
>>> return false; @@ -2259,10 +2251,8 @@ enum
>>> dc_status resource_map_pool_resources(
>>> /* acquire new resources */
>>> pipe_idx =
>>> acquire_first_free_pipe(&context->res_ctx, pool, stream);
>>>
>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>> if (pipe_idx < 0)
>>> pipe_idx =
>>> acquire_first_split_pipe(&context->res_ctx, pool, stream); -#endif
>>>
>>> if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
>>> return DC_NO_CONTROLLER_RESOURCE; @@ -2453,7 +2443,6
>>> @@ enum dc_status dc_validate_global_state(
>>> if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
>>> result = DC_FAIL_BANDWIDTH_VALIDATE;
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> /*
>>> * Only update link encoder to stream assignment after bandwidth validation passed.
>>> * TODO: Split out assignment and validation.
>>> @@ -2461,7 +2450,6 @@ enum dc_status dc_validate_global_state(
>>> if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
>>> dc->res_pool->funcs->link_encs_assign(
>>> dc, new_ctx, new_ctx->streams,
>>> new_ctx->stream_count); -#endif
>>>
>>> return result;
>>> }
>>> @@ -3189,10 +3177,8 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
>>> case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
>>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
>>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
>>> case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
>>> -#endif
>>> return 32;
>>> case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
>>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
>>> @@ -3345,7 +3331,6 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
>>> /* TODO - get transmitter to phy idx mapping from DMUB */
>>> uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
>>> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
>>> switch (transmitter) { @@ -3369,7 +3354,7 @@ uint8_t
>>> resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
>>> break;
>>> }
>>> }
>>> -#endif
>>> +
>>> return phy_idx;
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>>> index c4e871f358ab..acca35d86c10 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>>> @@ -314,9 +314,7 @@ bool dc_stream_set_cursor_attributes(
>>> const struct dc_cursor_attributes *attributes)
>>> {
>>> struct dc *dc;
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool reset_idle_optimizations = false; -#endif
>>>
>>> if (NULL == stream) {
>>> dm_error("DC: dc_stream is NULL!\n"); @@ -346,12
>>> +344,10 @@ bool dc_stream_set_cursor_attributes(
>>> #endif
>>> program_cursor_attributes(dc, stream, attributes);
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> /* re-enable idle optimizations if necessary */
>>> if (reset_idle_optimizations)
>>> dc_allow_idle_optimizations(dc, true);
>>>
>>> -#endif
>>> return true;
>>> }
>>>
>>> @@ -396,9 +392,7 @@ bool dc_stream_set_cursor_position(
>>> const struct dc_cursor_position *position)
>>> {
>>> struct dc *dc;
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool reset_idle_optimizations = false; -#endif
>>>
>>> if (NULL == stream) {
>>> dm_error("DC: dc_stream is NULL!\n"); @@ -424,12
>>> +418,10 @@ bool dc_stream_set_cursor_position(
>>> stream->cursor_position = *position;
>>>
>>> program_cursor_position(dc, stream, position); -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> /* re-enable idle optimizations if necessary */
>>> if (reset_idle_optimizations)
>>> dc_allow_idle_optimizations(dc, true);
>>>
>>> -#endif
>>> return true;
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
>>> b/drivers/gpu/drm/amd/display/dc/dc.h
>>> index e37d9c19f089..0f86bb809e04 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dc.h
>>> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
>>> @@ -222,7 +222,6 @@ struct dc_dcc_setting {
>>> unsigned int max_compressed_blk_size;
>>> unsigned int max_uncompressed_blk_size;
>>> bool independent_64b_blks;
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> //These bitfields to be used starting with DCN
>>> struct {
>>> uint32_t dcc_256_64_64 : 1;//available in ASICs
>>> before DCN (the worst compression case) @@ -230,7 +229,6 @@ struct dc_dcc_setting {
>>> uint32_t dcc_256_128_128 : 1; //available starting with DCN
>>> uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
>>> } dcc_controls;
>>> -#endif
>>> };
>>>
>>> struct dc_surface_dcc_cap {
>>> @@ -332,9 +330,7 @@ struct dc_config {
>>> bool enable_4to1MPC;
>>> bool enable_windowed_mpo_odm;
>>> bool allow_edp_hotplug_detection; -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool clamp_min_dcfclk;
>>> -#endif
>>> uint64_t vblank_alignment_dto_params;
>>> uint8_t vblank_alignment_max_frame_time_diff;
>>> bool is_asymmetric_memory;
>>> @@ -395,14 +391,12 @@ enum dcn_pwr_state {
>>> DCN_PWR_STATE_LOW_POWER = 3,
>>> };
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> enum dcn_zstate_support_state {
>>> DCN_ZSTATE_SUPPORT_UNKNOWN,
>>> DCN_ZSTATE_SUPPORT_ALLOW,
>>> DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
>>> DCN_ZSTATE_SUPPORT_DISALLOW,
>>> };
>>> -#endif
>>> /*
>>> * For any clocks that may differ per pipe
>>> * only the max is stored in this structure @@ -420,10 +414,8 @@
>>> struct dc_clocks {
>>> int phyclk_khz;
>>> int dramclk_khz;
>>> bool p_state_change_support; -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> enum dcn_zstate_support_state zstate_support;
>>> bool dtbclk_en;
>>> -#endif
>>> enum dcn_pwr_state pwr_state;
>>> /*
>>> * Elements below are not compared for the purposes of @@
>>> -653,9 +645,7 @@ struct dc_debug_options {
>>> bool disable_pplib_clock_request;
>>> bool disable_clock_gate;
>>> bool disable_mem_low_power;
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool pstate_enabled;
>>> -#endif
>>> bool disable_dmcu;
>>> bool disable_psr;
>>> bool force_abm_enable;
>>> @@ -673,20 +663,16 @@ struct dc_debug_options {
>>> bool remove_disconnect_edp;
>>> unsigned int force_odm_combine; //bit vector based on otg inst
>>> unsigned int seamless_boot_odm_combine; -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> unsigned int force_odm_combine_4to1; //bit vector based on otg inst
>>> bool disable_z9_mpc;
>>> -#endif
>>> unsigned int force_fclk_khz;
>>> bool enable_tri_buf;
>>> bool dmub_offload_enabled;
>>> bool dmcub_emulation;
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool disable_idle_power_optimizations;
>>> unsigned int mall_size_override;
>>> unsigned int mall_additional_timer_percent;
>>> bool mall_error_as_fatal;
>>> -#endif
>>> bool dmub_command_table; /* for testing only */
>>> struct dc_bw_validation_profile bw_val_profile;
>>> bool disable_fec;
>>> @@ -695,9 +681,7 @@ struct dc_debug_options {
>>> * watermarks are not affected.
>>> */
>>> unsigned int force_min_dcfclk_mhz; -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> int dwb_fi_phase;
>>> -#endif
>>> bool disable_timing_sync;
>>> bool cm_in_bypass;
>>> int force_clock_mode;/*every mode change.*/ @@ -729,11
>>> +713,9 @@ struct dc_debug_options {
>>> enum det_size crb_alloc_policy;
>>> int crb_alloc_policy_min_disp_count;
>>> bool disable_z10;
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool enable_z9_disable_interface;
>>> bool enable_sw_cntl_psr;
>>> union dpia_debug_options dpia_debug; -#endif
>>> bool apply_vendor_specific_lttpr_wa;
>>> bool extended_blank_optimization;
>>> union aux_wake_wa_options aux_wake_wa; @@ -767,11 +749,9 @@
>>> struct dc {
>>> /* Inputs into BW and WM calculations. */
>>> struct bw_calcs_dceip *bw_dceip;
>>> struct bw_calcs_vbios *bw_vbios; -#ifdef
>>> CONFIG_DRM_AMD_DC_DCN
>>> struct dcn_soc_bounding_box *dcn_soc;
>>> struct dcn_ip_params *dcn_ip;
>>> struct display_mode_lib dml; -#endif
>>>
>>> /* HW functions */
>>> struct hw_sequencer_funcs hwss; @@ -780,12 +760,8 @@ struct
>>> dc {
>>> /* Require to optimize clocks and bandwidth for added/removed planes */
>>> bool optimized_required;
>>> bool wm_optimized_required;
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool idle_optimizations_allowed; -#endif -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool enable_c20_dtm_b0;
>>> -#endif
>>>
>>> /* Require to maintain clocks and bandwidth for UEFI enabled
>>> HW */
>>>
>>> @@ -835,9 +811,7 @@ struct dc_init_data {
>>> uint64_t log_mask;
>>>
>>> struct dpcd_vendor_signature vendor_signature; -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool force_smu_not_present;
>>> -#endif
>>> };
>>>
>>> struct dc_callback_init {
>>> @@ -1030,9 +1004,7 @@ struct dc_plane_state {
>>> struct dc_transfer_func *in_shaper_func;
>>> struct dc_transfer_func *blend_tf;
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> struct dc_transfer_func *gamcor_tf; -#endif
>>> enum surface_pixel_format format;
>>> enum dc_rotation_angle rotation;
>>> enum plane_stereo_format stereo_format; @@ -1169,13 +1141,11
>>> @@ void dc_resource_state_construct(
>>> const struct dc *dc,
>>> struct dc_state *dst_ctx);
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool dc_acquire_release_mpc_3dlut(
>>> struct dc *dc, bool acquire,
>>> struct dc_stream_state *stream,
>>> struct dc_3dlut **lut,
>>> struct dc_transfer_func **shaper); -#endif
>>>
>>> void dc_resource_state_copy_construct(
>>> const struct dc_state *src_ctx, @@ -1306,10 +1276,8
>>> @@ struct hdcp_caps {
>>>
>>> #include "dc_link.h"
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state
>>> *plane);
>>>
>>> -#endif
>>> /*******************************************************************************
>>> * Sink Interfaces - A sink corresponds to a display output device
>>>
>>> *********************************************************************
>>> *********/ @@ -1433,7 +1401,6 @@ bool dc_is_dmcu_initialized(struct
>>> dc *dc);
>>>
>>> enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
>>> void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type,
>>> struct dc_clock_config *clock_cfg); -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>
>>> bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
>>> struct dc_cursor_attributes
>>> *cursor_attr); @@ -1458,13 +1425,9 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
>>> /* cleanup on driver unload */
>>> void dc_hardware_release(struct dc *dc);
>>>
>>> -#endif
>>> -
>>> bool dc_set_psr_allow_active(struct dc *dc, bool enable); -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> void dc_z10_restore(const struct dc *dc);
>>> void dc_z10_save_init(struct dc *dc); -#endif
>>>
>>> bool dc_is_dmub_outbox_supported(struct dc *dc);
>>> bool dc_enable_dmub_notifications(struct dc *dc); diff --git
>>> a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>>> b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>>> index 31109db02e93..fb6a2d7b6470 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>>> +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>>> @@ -160,9 +160,7 @@ void dm_set_dcn_clocks(
>>> struct dc_context *ctx,
>>> struct dc_clocks *clks);
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> void dm_helpers_enable_periodic_detection(struct dc_context *ctx,
>>> bool enable); -#endif
>>>
>>> void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz);
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>>> b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>>> index 951c9b60917d..26f3a55c35d7 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>>> +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>>> @@ -33,9 +33,7 @@
>>> #include "dc_bios_types.h"
>>> #include "mem_input.h"
>>> #include "hubp.h"
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> #include "mpc.h"
>>> -#endif
>>> #include "dwb.h"
>>> #include "mcif_wb.h"
>>> #include "panel_cntl.h"
>>> @@ -181,7 +179,6 @@ struct resource_funcs {
>>> void (*update_bw_bounding_box)(
>>> struct dc *dc,
>>> struct clk_bw_params *bw_params); -#if
>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool (*acquire_post_bldn_3dlut)(
>>> struct resource_context *res_ctx,
>>> const struct resource_pool *pool, @@ -194,7
>>> +191,7 @@ struct resource_funcs {
>>> const struct resource_pool *pool,
>>> struct dc_3dlut **lut,
>>> struct dc_transfer_func **shaper); -#endif
>>> +
>>> enum dc_status (*add_dsc_to_stream_resource)(
>>> struct dc *dc, struct dc_state *state,
>>> struct dc_stream_state *stream); @@ -254,10
>>> +251,9 @@ struct resource_pool {
>>> struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
>>> unsigned int hpo_dp_link_enc_count;
>>> struct hpo_dp_link_encoder
>>> *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> struct dc_3dlut *mpc_lut[MAX_PIPES];
>>> struct dc_transfer_func *mpc_shaper[MAX_PIPES]; -#endif
>>> +
>>> struct {
>>> unsigned int xtalin_clock_inKhz;
>>> unsigned int dccg_ref_clock_inKhz; @@ -286,9 +282,7
>>> @@ struct resource_pool {
>>> struct dmcu *dmcu;
>>> struct dmub_psr *psr;
>>>
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> struct abm *multiple_abms[MAX_PIPES]; -#endif
>>>
>>> const struct resource_funcs *funcs;
>>> const struct resource_caps *res_cap; @@ -380,7 +374,6 @@
>>> struct pipe_ctx {
>>> struct pipe_ctx *next_odm_pipe;
>>> struct pipe_ctx *prev_odm_pipe;
>>>
>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>> struct _vcs_dpi_display_dlg_regs_st dlg_regs;
>>> struct _vcs_dpi_display_ttu_regs_st ttu_regs;
>>> struct _vcs_dpi_display_rq_regs_st rq_regs; @@ -390,7 +383,7
>>> @@ struct pipe_ctx {
>>> struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
>>> int det_buffer_size_kb;
>>> bool unbounded_req;
>>> -#endif
>>> +
>>> union pipe_update_flags update_flags;
>>> struct dwbc *dwbc;
>>> struct mcif_wb *mcif_wb;
>>> @@ -419,9 +412,7 @@ struct resource_context {
>>> bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
>>> unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
>>> int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> bool is_mpc_3dlut_acquired[MAX_PIPES]; -#endif
>>> };
>>>
>>> struct dce_bw_output {
>>> @@ -484,9 +475,7 @@ struct dc_state {
>>>
>>> /* Note: these are big structures, do *not* put on stack! */
>>> struct dm_pp_display_configuration pp_display_cfg; -#ifdef
>>> CONFIG_DRM_AMD_DC_DCN
>>> struct dcn_bw_internal_vars dcn_bw_vars; -#endif
>>>
>>> struct clk_mgr *clk_mgr;
>>>
>>> --
>>> 2.35.1
>>>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
2022-05-09 11:57 ` VURDIGERENATARAJ, CHANDAN
@ 2022-05-09 13:22 ` Rodrigo Siqueira Jordao
0 siblings, 0 replies; 29+ messages in thread
From: Rodrigo Siqueira Jordao @ 2022-05-09 13:22 UTC (permalink / raw)
To: VURDIGERENATARAJ, CHANDAN, Cui, Flora, Alex Deucher, Hung, Alex,
Wang, Chao-kai (Stylon),
Daniel Wheeler
Cc: Li, Sun peng (Leo), Lakha, Bhawanpreet, Zhuo, Qingqing (Lillian),
Li, Roman, amd-gfx list, Chiu, Solomon, Pillai, Aurabindo, Lin,
Wayne, Wentland, Harry, Gutierrez, Agustin, Kotarac, Pavle
See my comments inline
On 2022-05-09 07:57, VURDIGERENATARAJ, CHANDAN wrote:
> Hi,
>
> Changes are not needed in " drivers/gpu/drm/amd/display/Kconfig" ??
I don't think so, unless I'm missing something. We are not dropping the
CONFIG_DRM_AMD_DC_DCN config; we are just removing it from some places
that we don't need anymore. Do you have a specific concern?
> Also, is this change validated on Chrome?
I don't see any good reason why ChromeOS will not work with that; we are
not sending this change to the stable kernel since it depends on our FPU
code as well.
Daniel tested it on ChromeOS (amd-staging-drm-next); he will probably
send his test result as a reply to the cover letter. Afik, everything is
alright.
> BR,
> Chandan V N
>
>> What about arm?
The community dropped support for ARM from RDNA1 (and above) a few years
ago because of how we were handling the FPU code on the display side.
However, we have been working on that for a couple of months; we are
close to completing this work and re-enabling ARM + DCN soon.
Thanks
Siqueira
>>
>> -----Original Message-----
>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Rodrigo Siqueira Jordao
>> Sent: 2022年5月7日 1:13
>> To: Alex Deucher <alexdeucher@gmail.com>; Hung, Alex <Alex.Hung@amd.com>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>
>> Cc: Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Li, Roman <Roman.Li@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Chiu, Solomon ><Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
>> Subject: Re: [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
>>
>>
>>
>> On 2022-05-06 11:56, Alex Deucher wrote:
>>> On Fri, May 6, 2022 at 11:43 AM Stylon Wang <stylon.wang@amd.com> wrote:
>>>>
>>>> From: Alex Hung <alex.hung@amd.com>
>>>>
>>>> [Why & How]
>>>> CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but
>>>> DC code should be OS-agnostic.
>>>>
>>>> This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN in
>>>> dc and dc/core directories.
>>>>
>>>> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>>> Acked-by: Stylon Wang <stylon.wang@amd.com>
>>>> Signed-off-by: Alex Hung <alex.hung@amd.com>
>>>
>>> I presume the driver still builds properly on configs where
>>> CONFIG_DRM_AMD_DC_DCN is not set? E.g., platforms without floating
>>> point for example?
>>>
>>
>> Hi Alex,
>>
>> This is part of our effort to isolate FPU code inside DML (right now, we are only missing DCN30); since we are really close to that, many of these guards become useless. All of these patches were tested in our CI
>> against:
>>
>> 1. x86 with DCN
>> 2. x86 without DCN
>> 3. Clang
>> 4. make allmodconfig
>>
>> Additionally, I think that Alex Hung also checked the compilation with PowerPC.
>>
>> Thanks
>> Siqueira
>>
>>
>>> Alex
>>>
>>>> ---
>>>> drivers/gpu/drm/amd/display/dc/Makefile | 2 -
>>>> .../display/dc/bios/command_table_helper2.c | 3 +-
>>>> drivers/gpu/drm/amd/display/dc/core/dc.c | 31 ++--------------
>>>> .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 -
>>>> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -
>>>> .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 --
>>>> .../drm/amd/display/dc/core/dc_link_dpia.c | 2 -
>>>> .../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ++---------
>>>> .../gpu/drm/amd/display/dc/core/dc_stream.c | 8 ----
>>>> drivers/gpu/drm/amd/display/dc/dc.h | 37 -------------------
>>>> drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 -
>>>> .../gpu/drm/amd/display/dc/inc/core_types.h | 17 ++-------
>>>> 12 files changed, 10 insertions(+), 121 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>>>> b/drivers/gpu/drm/amd/display/dc/Makefile
>>>> index f05ab2bf20c5..b4eca0236435 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/Makefile
>>>> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
>>>> @@ -63,9 +63,7 @@ DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink
>>>> dc_surface.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
>>>> dc_link_enc_cfg.o dc_link_dpia.o dc_link_dpcd.o
>>>>
>>>> -ifdef CONFIG_DRM_AMD_DC_DCN
>>>> DISPLAY_CORE += dc_vm_helper.o
>>>> -endif
>>>>
>>>> AMD_DISPLAY_CORE = $(addprefix
>>>> $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
>>>>
>>>> diff --git
>>>> a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>>> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>>> index dd9704ef4ccc..f3792286f571 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>>> @@ -65,7 +65,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>>>> case DCE_VERSION_12_1:
>>>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>>>> return true;
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> case DCN_VERSION_1_0:
>>>> case DCN_VERSION_1_01:
>>>> case DCN_VERSION_2_0:
>>>> @@ -80,7 +79,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>>>> case DCN_VERSION_3_16:
>>>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>>>> return true;
>>>> -#endif
>>>> +
>>>> default:
>>>> /* Unsupported DCE */
>>>> BREAK_TO_DEBUGGER(); diff --git
>>>> a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>> b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>> index c2fcd67bcc4d..1eeea7c184ae 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>> @@ -829,14 +829,12 @@ static void dc_destruct(struct dc *dc)
>>>> kfree(dc->bw_dceip);
>>>> dc->bw_dceip = NULL;
>>>>
>>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>>> kfree(dc->dcn_soc);
>>>> dc->dcn_soc = NULL;
>>>>
>>>> kfree(dc->dcn_ip);
>>>> dc->dcn_ip = NULL;
>>>>
>>>> -#endif
>>>> kfree(dc->vm_helper);
>>>> dc->vm_helper = NULL;
>>>>
>>>> @@ -882,10 +880,8 @@ static bool dc_construct(struct dc *dc,
>>>> struct dc_context *dc_ctx;
>>>> struct bw_calcs_dceip *dc_dceip;
>>>> struct bw_calcs_vbios *dc_vbios; -#ifdef
>>>> CONFIG_DRM_AMD_DC_DCN
>>>> struct dcn_soc_bounding_box *dcn_soc;
>>>> struct dcn_ip_params *dcn_ip; -#endif
>>>>
>>>> dc->config = init_params->flags;
>>>>
>>>> @@ -913,7 +909,6 @@ static bool dc_construct(struct dc *dc,
>>>> }
>>>>
>>>> dc->bw_vbios = dc_vbios;
>>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>>> dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
>>>> if (!dcn_soc) {
>>>> dm_error("%s: failed to create dcn_soc\n",
>>>> __func__); @@ -929,7 +924,6 @@ static bool dc_construct(struct dc *dc,
>>>> }
>>>>
>>>> dc->dcn_ip = dcn_ip;
>>>> -#endif
>>>>
>>>> if (!dc_construct_ctx(dc, init_params)) {
>>>> dm_error("%s: failed to create ctx\n", __func__); @@
>>>> -1868,7 +1862,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
>>>> return (result == DC_OK);
>>>> }
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool dc_acquire_release_mpc_3dlut(
>>>> struct dc *dc, bool acquire,
>>>> struct dc_stream_state *stream, @@ -1904,7 +1897,7
>>>> @@ bool dc_acquire_release_mpc_3dlut(
>>>> }
>>>> return ret;
>>>> }
>>>> -#endif
>>>> +
>>>> static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
>>>> {
>>>> int i;
>>>> @@ -1925,7 +1918,6 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
>>>> return false;
>>>> }
>>>>
>>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>>> /* Perform updates here which need to be deferred until next vupdate
>>>> *
>>>> * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double
>>>> buffered @@ -1944,7 +1936,6 @@ static void process_deferred_updates(struct dc *dc)
>>>> dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
>>>> }
>>>> }
>>>> -#endif /* CONFIG_DRM_AMD_DC_DCN */
>>>>
>>>> void dc_post_update_surfaces_to_stream(struct dc *dc)
>>>> {
>>>> @@ -1971,9 +1962,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
>>>> dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
>>>> }
>>>>
>>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>>> process_deferred_updates(dc); -#endif
>>>>
>>>> dc->hwss.optimize_bandwidth(dc, context);
>>>>
>>>> @@ -1987,9 +1976,7 @@ static void init_state(struct dc *dc, struct dc_state *context)
>>>> * initialize and obtain IP and SOC the base DML instance from DC is
>>>> * initially copied into every context
>>>> */
>>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>>> memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct
>>>> display_mode_lib)); -#endif
>>>> }
>>>>
>>>> struct dc_state *dc_create_state(struct dc *dc) @@ -2361,11 +2348,9
>>>> @@ static enum surface_update_type check_update_surfaces_for_stream(
>>>> int i;
>>>> enum surface_update_type overall_type = UPDATE_TYPE_FAST;
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> if (dc->idle_optimizations_allowed)
>>>> overall_type = UPDATE_TYPE_FULL;
>>>>
>>>> -#endif
>>>> if (stream_status == NULL || stream_status->plane_count != surface_count)
>>>> overall_type = UPDATE_TYPE_FULL;
>>>>
>>>> @@ -2874,10 +2859,8 @@ static void commit_planes_for_stream(struct dc *dc,
>>>> }
>>>>
>>>> if (update_type == UPDATE_TYPE_FULL) { -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> dc_allow_idle_optimizations(dc, false);
>>>>
>>>> -#endif
>>>> if (get_seamless_boot_stream_count(context) == 0)
>>>> dc->hwss.prepare_bandwidth(dc, context);
>>>>
>>>> @@ -2895,7 +2878,6 @@ static void commit_planes_for_stream(struct dc *dc,
>>>> }
>>>> }
>>>>
>>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>>> if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
>>>> struct pipe_ctx *mpcc_pipe;
>>>> struct pipe_ctx *odm_pipe; @@ -2904,7 +2886,6 @@
>>>> static void commit_planes_for_stream(struct dc *dc,
>>>> for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>>>> odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
>>>> }
>>>> -#endif
>>>>
>>>> if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
>>>> if (top_pipe_to_program && @@ -3014,7 +2995,6 @@
>>>> static void commit_planes_for_stream(struct dc *dc,
>>>> }
>>>> if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
>>>> dc->hwss.program_front_end_for_ctx(dc, context);
>>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>>> if (dc->debug.validate_dml_output) {
>>>> for (i = 0; i < dc->res_pool->pipe_count; i++) {
>>>> struct pipe_ctx *cur_pipe =
>>>> &context->res_ctx.pipe_ctx[i]; @@ -3028,7 +3008,6 @@ static void commit_planes_for_stream(struct dc *dc,
>>>> &context->res_ctx.pipe_ctx[i].ttu_regs);
>>>> }
>>>> }
>>>> -#endif
>>>> }
>>>>
>>>> // Update Type FAST, Surface updates @@ -3583,8 +3562,6 @@
>>>> bool dc_set_psr_allow_active(struct dc *dc, bool enable)
>>>> return true;
>>>> }
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> -
>>>> void dc_allow_idle_optimizations(struct dc *dc, bool allow)
>>>> {
>>>> if (dc->debug.disable_idle_power_optimizations)
>>>> @@ -3740,7 +3717,6 @@ void dc_hardware_release(struct dc *dc)
>>>> if (dc->hwss.hardware_release)
>>>> dc->hwss.hardware_release(dc);
>>>> }
>>>> -#endif
>>>>
>>>> /*
>>>>
>>>> *********************************************************************
>>>> ******** @@ -3760,13 +3736,12 @@ void dc_hardware_release(struct dc
>>>> *dc)
>>>> */
>>>> bool dc_is_dmub_outbox_supported(struct dc *dc)
>>>> {
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> - /* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */
>>>> + /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts
>>>> + */
>>>> if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
>>>> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
>>>> !dc->debug.dpia_debug.bits.disable_dpia)
>>>> return true;
>>>> -#endif
>>>> +
>>>> /* dmub aux needs dmub notifications to be enabled */
>>>> return dc->debug.enable_dmub_aux_for_legacy_ddc;
>>>> }
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>>>> b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>>>> index 643762542e4d..72376075db0c 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>>>> @@ -345,7 +345,6 @@ void context_clock_trace(
>>>> struct dc *dc,
>>>> struct dc_state *context)
>>>> {
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> DC_LOGGER_INIT(dc->ctx->logger);
>>>> CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
>>>> "dcfclk_deep_sleep_khz:%d fclk_khz:%d
>>>> socclk_khz:%d\n", @@ -363,7 +362,6 @@ void context_clock_trace(
>>>> context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
>>>> context->bw_ctx.bw.dcn.clk.fclk_khz,
>>>> context->bw_ctx.bw.dcn.clk.socclk_khz);
>>>> -#endif
>>>> }
>>>>
>>>> /**
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>>>> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>>>> index 07f154fc4e56..9529b924742e 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>>>> @@ -804,7 +804,6 @@ static bool wait_for_entering_dp_alt_mode(struct
>>>> dc_link *link)
>>>>
>>>> static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>>>> {
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
>>>> * reports DSC support.
>>>> */
>>>> @@ -815,7 +814,6 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>>>> link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
>>>> !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
>>>> link->wa_flags.dpia_mst_dsc_always_on = true;
>>>> -#endif
>>>> }
>>>>
>>>> static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> index 5e49e346aa06..975d631534b5 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>>>> @@ -5127,12 +5127,10 @@ void dp_retrieve_lttpr_cap(struct dc_link *link)
>>>> else
>>>> link->lttpr_support = LTTPR_CHECK_EXT_SUPPORT;
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> /* Check DP tunnel LTTPR mode debug option. */
>>>> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
>>>> link->dc->debug.dpia_debug.bits.force_non_lttpr)
>>>> link->lttpr_support = LTTPR_UNSUPPORTED; -#endif
>>>>
>>>> if (link->lttpr_support > LTTPR_UNSUPPORTED) {
>>>> /* By reading LTTPR capability, RX assumes that we
>>>> will enable @@ -5626,9 +5624,7 @@ static bool retrieve_link_cap(struct dc_link *link)
>>>> * only if required.
>>>> */
>>>> if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>>
>>>> !link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around && -#endif
>>>> link->dpcd_caps.is_branch_dev &&
>>>> link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
>>>> link->dpcd_caps.branch_hw_revision
>>>> == DP_BRANCH_HW_REV_10 && diff --git
>>>> a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>>>> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>>>> index 0e95bc5df4e7..a5765f36d86f 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
>>>> @@ -547,11 +547,9 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link,
>>>> dp_translate_training_aux_read_interval(
>>>>
>>>> link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> /* Check debug option for extending aux read interval. */
>>>> if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
>>>> wait_time_microsec =
>>>> DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
>>>> -#endif
>>>>
>>>> return wait_time_microsec;
>>>> }
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>>> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>>> index 147c6a3c6312..f702919a2279 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>>> @@ -56,7 +56,6 @@
>>>> #include "dce110/dce110_resource.h"
>>>> #include "dce112/dce112_resource.h"
>>>> #include "dce120/dce120_resource.h"
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> #include "dcn10/dcn10_resource.h"
>>>> #include "dcn20/dcn20_resource.h"
>>>> #include "dcn21/dcn21_resource.h"
>>>> @@ -68,7 +67,6 @@
>>>> #include "dcn31/dcn31_resource.h"
>>>> #include "dcn315/dcn315_resource.h"
>>>> #include "dcn316/dcn316_resource.h"
>>>> -#endif
>>>>
>>>> #define DC_LOGGER_INIT(logger)
>>>>
>>>> @@ -124,7 +122,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>>>> else
>>>> dc_version = DCE_VERSION_12_0;
>>>> break;
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> case FAMILY_RV:
>>>> dc_version = DCN_VERSION_1_0;
>>>> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
>>>> @@ -165,7 +162,6 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>>>> if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
>>>> dc_version = DCN_VERSION_3_16;
>>>> break;
>>>> -#endif
>>>>
>>>> default:
>>>> dc_version = DCE_VERSION_UNKNOWN; @@ -397,7 +393,6
>>>> @@ bool resource_construct(
>>>> }
>>>> }
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> for (i = 0; i < caps->num_mpc_3dlut; i++) {
>>>> pool->mpc_lut[i] = dc_create_3dlut_func();
>>>> if (pool->mpc_lut[i] == NULL) @@ -406,7 +401,7 @@
>>>> bool resource_construct(
>>>> if (pool->mpc_shaper[i] == NULL)
>>>> DC_ERR("DC: failed to create MPC shaper!\n");
>>>> }
>>>> -#endif
>>>> +
>>>> dc->caps.dynamic_audio = false;
>>>> if (pool->audio_count < pool->stream_enc_count) {
>>>> dc->caps.dynamic_audio = true; @@ -1369,7 +1364,6 @@
>>>> static struct pipe_ctx *acquire_free_pipe_for_head(
>>>> return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
>>>> }
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> static int acquire_first_split_pipe(
>>>> struct resource_context *res_ctx,
>>>> const struct resource_pool *pool, @@ -1404,7 +1398,6
>>>> @@ static int acquire_first_split_pipe(
>>>> }
>>>> return -1;
>>>> }
>>>> -#endif
>>>>
>>>> bool dc_add_plane_to_context(
>>>> const struct dc *dc, @@ -1447,13 +1440,12 @@ bool
>>>> dc_add_plane_to_context(
>>>> while (head_pipe) {
>>>> free_pipe = acquire_free_pipe_for_head(context,
>>>> pool, head_pipe);
>>>>
>>>> - #if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> if (!free_pipe) {
>>>> int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
>>>> if (pipe_idx >= 0)
>>>> free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
>>>> }
>>>> - #endif
>>>> +
>>>> if (!free_pipe) {
>>>> dc_plane_state_release(plane_state);
>>>> return false; @@ -2259,10 +2251,8 @@ enum
>>>> dc_status resource_map_pool_resources(
>>>> /* acquire new resources */
>>>> pipe_idx =
>>>> acquire_first_free_pipe(&context->res_ctx, pool, stream);
>>>>
>>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>>> if (pipe_idx < 0)
>>>> pipe_idx =
>>>> acquire_first_split_pipe(&context->res_ctx, pool, stream); -#endif
>>>>
>>>> if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
>>>> return DC_NO_CONTROLLER_RESOURCE; @@ -2453,7 +2443,6
>>>> @@ enum dc_status dc_validate_global_state(
>>>> if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
>>>> result = DC_FAIL_BANDWIDTH_VALIDATE;
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> /*
>>>> * Only update link encoder to stream assignment after bandwidth validation passed.
>>>> * TODO: Split out assignment and validation.
>>>> @@ -2461,7 +2450,6 @@ enum dc_status dc_validate_global_state(
>>>> if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
>>>> dc->res_pool->funcs->link_encs_assign(
>>>> dc, new_ctx, new_ctx->streams,
>>>> new_ctx->stream_count); -#endif
>>>>
>>>> return result;
>>>> }
>>>> @@ -3189,10 +3177,8 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
>>>> case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
>>>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
>>>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
>>>> case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
>>>> -#endif
>>>> return 32;
>>>> case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
>>>> case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
>>>> @@ -3345,7 +3331,6 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
>>>> /* TODO - get transmitter to phy idx mapping from DMUB */
>>>> uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
>>>> dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
>>>> switch (transmitter) { @@ -3369,7 +3354,7 @@ uint8_t
>>>> resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr
>>>> break;
>>>> }
>>>> }
>>>> -#endif
>>>> +
>>>> return phy_idx;
>>>> }
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>>>> b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>>>> index c4e871f358ab..acca35d86c10 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>>>> @@ -314,9 +314,7 @@ bool dc_stream_set_cursor_attributes(
>>>> const struct dc_cursor_attributes *attributes)
>>>> {
>>>> struct dc *dc;
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool reset_idle_optimizations = false; -#endif
>>>>
>>>> if (NULL == stream) {
>>>> dm_error("DC: dc_stream is NULL!\n"); @@ -346,12
>>>> +344,10 @@ bool dc_stream_set_cursor_attributes(
>>>> #endif
>>>> program_cursor_attributes(dc, stream, attributes);
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> /* re-enable idle optimizations if necessary */
>>>> if (reset_idle_optimizations)
>>>> dc_allow_idle_optimizations(dc, true);
>>>>
>>>> -#endif
>>>> return true;
>>>> }
>>>>
>>>> @@ -396,9 +392,7 @@ bool dc_stream_set_cursor_position(
>>>> const struct dc_cursor_position *position)
>>>> {
>>>> struct dc *dc;
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool reset_idle_optimizations = false; -#endif
>>>>
>>>> if (NULL == stream) {
>>>> dm_error("DC: dc_stream is NULL!\n"); @@ -424,12
>>>> +418,10 @@ bool dc_stream_set_cursor_position(
>>>> stream->cursor_position = *position;
>>>>
>>>> program_cursor_position(dc, stream, position); -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> /* re-enable idle optimizations if necessary */
>>>> if (reset_idle_optimizations)
>>>> dc_allow_idle_optimizations(dc, true);
>>>>
>>>> -#endif
>>>> return true;
>>>> }
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
>>>> b/drivers/gpu/drm/amd/display/dc/dc.h
>>>> index e37d9c19f089..0f86bb809e04 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/dc.h
>>>> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
>>>> @@ -222,7 +222,6 @@ struct dc_dcc_setting {
>>>> unsigned int max_compressed_blk_size;
>>>> unsigned int max_uncompressed_blk_size;
>>>> bool independent_64b_blks;
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> //These bitfields to be used starting with DCN
>>>> struct {
>>>> uint32_t dcc_256_64_64 : 1;//available in ASICs
>>>> before DCN (the worst compression case) @@ -230,7 +229,6 @@ struct dc_dcc_setting {
>>>> uint32_t dcc_256_128_128 : 1; //available starting with DCN
>>>> uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
>>>> } dcc_controls;
>>>> -#endif
>>>> };
>>>>
>>>> struct dc_surface_dcc_cap {
>>>> @@ -332,9 +330,7 @@ struct dc_config {
>>>> bool enable_4to1MPC;
>>>> bool enable_windowed_mpo_odm;
>>>> bool allow_edp_hotplug_detection; -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool clamp_min_dcfclk;
>>>> -#endif
>>>> uint64_t vblank_alignment_dto_params;
>>>> uint8_t vblank_alignment_max_frame_time_diff;
>>>> bool is_asymmetric_memory;
>>>> @@ -395,14 +391,12 @@ enum dcn_pwr_state {
>>>> DCN_PWR_STATE_LOW_POWER = 3,
>>>> };
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> enum dcn_zstate_support_state {
>>>> DCN_ZSTATE_SUPPORT_UNKNOWN,
>>>> DCN_ZSTATE_SUPPORT_ALLOW,
>>>> DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
>>>> DCN_ZSTATE_SUPPORT_DISALLOW,
>>>> };
>>>> -#endif
>>>> /*
>>>> * For any clocks that may differ per pipe
>>>> * only the max is stored in this structure @@ -420,10 +414,8 @@
>>>> struct dc_clocks {
>>>> int phyclk_khz;
>>>> int dramclk_khz;
>>>> bool p_state_change_support; -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> enum dcn_zstate_support_state zstate_support;
>>>> bool dtbclk_en;
>>>> -#endif
>>>> enum dcn_pwr_state pwr_state;
>>>> /*
>>>> * Elements below are not compared for the purposes of @@
>>>> -653,9 +645,7 @@ struct dc_debug_options {
>>>> bool disable_pplib_clock_request;
>>>> bool disable_clock_gate;
>>>> bool disable_mem_low_power;
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool pstate_enabled;
>>>> -#endif
>>>> bool disable_dmcu;
>>>> bool disable_psr;
>>>> bool force_abm_enable;
>>>> @@ -673,20 +663,16 @@ struct dc_debug_options {
>>>> bool remove_disconnect_edp;
>>>> unsigned int force_odm_combine; //bit vector based on otg inst
>>>> unsigned int seamless_boot_odm_combine; -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> unsigned int force_odm_combine_4to1; //bit vector based on otg inst
>>>> bool disable_z9_mpc;
>>>> -#endif
>>>> unsigned int force_fclk_khz;
>>>> bool enable_tri_buf;
>>>> bool dmub_offload_enabled;
>>>> bool dmcub_emulation;
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool disable_idle_power_optimizations;
>>>> unsigned int mall_size_override;
>>>> unsigned int mall_additional_timer_percent;
>>>> bool mall_error_as_fatal;
>>>> -#endif
>>>> bool dmub_command_table; /* for testing only */
>>>> struct dc_bw_validation_profile bw_val_profile;
>>>> bool disable_fec;
>>>> @@ -695,9 +681,7 @@ struct dc_debug_options {
>>>> * watermarks are not affected.
>>>> */
>>>> unsigned int force_min_dcfclk_mhz; -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> int dwb_fi_phase;
>>>> -#endif
>>>> bool disable_timing_sync;
>>>> bool cm_in_bypass;
>>>> int force_clock_mode;/*every mode change.*/ @@ -729,11
>>>> +713,9 @@ struct dc_debug_options {
>>>> enum det_size crb_alloc_policy;
>>>> int crb_alloc_policy_min_disp_count;
>>>> bool disable_z10;
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool enable_z9_disable_interface;
>>>> bool enable_sw_cntl_psr;
>>>> union dpia_debug_options dpia_debug; -#endif
>>>> bool apply_vendor_specific_lttpr_wa;
>>>> bool extended_blank_optimization;
>>>> union aux_wake_wa_options aux_wake_wa; @@ -767,11 +749,9 @@
>>>> struct dc {
>>>> /* Inputs into BW and WM calculations. */
>>>> struct bw_calcs_dceip *bw_dceip;
>>>> struct bw_calcs_vbios *bw_vbios; -#ifdef
>>>> CONFIG_DRM_AMD_DC_DCN
>>>> struct dcn_soc_bounding_box *dcn_soc;
>>>> struct dcn_ip_params *dcn_ip;
>>>> struct display_mode_lib dml; -#endif
>>>>
>>>> /* HW functions */
>>>> struct hw_sequencer_funcs hwss; @@ -780,12 +760,8 @@ struct
>>>> dc {
>>>> /* Require to optimize clocks and bandwidth for added/removed planes */
>>>> bool optimized_required;
>>>> bool wm_optimized_required;
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool idle_optimizations_allowed; -#endif -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool enable_c20_dtm_b0;
>>>> -#endif
>>>>
>>>> /* Require to maintain clocks and bandwidth for UEFI enabled
>>>> HW */
>>>>
>>>> @@ -835,9 +811,7 @@ struct dc_init_data {
>>>> uint64_t log_mask;
>>>>
>>>> struct dpcd_vendor_signature vendor_signature; -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool force_smu_not_present;
>>>> -#endif
>>>> };
>>>>
>>>> struct dc_callback_init {
>>>> @@ -1030,9 +1004,7 @@ struct dc_plane_state {
>>>> struct dc_transfer_func *in_shaper_func;
>>>> struct dc_transfer_func *blend_tf;
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> struct dc_transfer_func *gamcor_tf; -#endif
>>>> enum surface_pixel_format format;
>>>> enum dc_rotation_angle rotation;
>>>> enum plane_stereo_format stereo_format; @@ -1169,13 +1141,11
>>>> @@ void dc_resource_state_construct(
>>>> const struct dc *dc,
>>>> struct dc_state *dst_ctx);
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool dc_acquire_release_mpc_3dlut(
>>>> struct dc *dc, bool acquire,
>>>> struct dc_stream_state *stream,
>>>> struct dc_3dlut **lut,
>>>> struct dc_transfer_func **shaper); -#endif
>>>>
>>>> void dc_resource_state_copy_construct(
>>>> const struct dc_state *src_ctx, @@ -1306,10 +1276,8
>>>> @@ struct hdcp_caps {
>>>>
>>>> #include "dc_link.h"
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state
>>>> *plane);
>>>>
>>>> -#endif
>>>> /*******************************************************************************
>>>> * Sink Interfaces - A sink corresponds to a display output device
>>>>
>>>> *********************************************************************
>>>> *********/ @@ -1433,7 +1401,6 @@ bool dc_is_dmcu_initialized(struct
>>>> dc *dc);
>>>>
>>>> enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
>>>> void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type,
>>>> struct dc_clock_config *clock_cfg); -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>>
>>>> bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
>>>> struct dc_cursor_attributes
>>>> *cursor_attr); @@ -1458,13 +1425,9 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
>>>> /* cleanup on driver unload */
>>>> void dc_hardware_release(struct dc *dc);
>>>>
>>>> -#endif
>>>> -
>>>> bool dc_set_psr_allow_active(struct dc *dc, bool enable); -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> void dc_z10_restore(const struct dc *dc);
>>>> void dc_z10_save_init(struct dc *dc); -#endif
>>>>
>>>> bool dc_is_dmub_outbox_supported(struct dc *dc);
>>>> bool dc_enable_dmub_notifications(struct dc *dc); diff --git
>>>> a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>>>> b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>>>> index 31109db02e93..fb6a2d7b6470 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>>>> +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
>>>> @@ -160,9 +160,7 @@ void dm_set_dcn_clocks(
>>>> struct dc_context *ctx,
>>>> struct dc_clocks *clks);
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> void dm_helpers_enable_periodic_detection(struct dc_context *ctx,
>>>> bool enable); -#endif
>>>>
>>>> void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz);
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>>>> b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>>>> index 951c9b60917d..26f3a55c35d7 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>>>> +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>>>> @@ -33,9 +33,7 @@
>>>> #include "dc_bios_types.h"
>>>> #include "mem_input.h"
>>>> #include "hubp.h"
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> #include "mpc.h"
>>>> -#endif
>>>> #include "dwb.h"
>>>> #include "mcif_wb.h"
>>>> #include "panel_cntl.h"
>>>> @@ -181,7 +179,6 @@ struct resource_funcs {
>>>> void (*update_bw_bounding_box)(
>>>> struct dc *dc,
>>>> struct clk_bw_params *bw_params); -#if
>>>> defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool (*acquire_post_bldn_3dlut)(
>>>> struct resource_context *res_ctx,
>>>> const struct resource_pool *pool, @@ -194,7
>>>> +191,7 @@ struct resource_funcs {
>>>> const struct resource_pool *pool,
>>>> struct dc_3dlut **lut,
>>>> struct dc_transfer_func **shaper); -#endif
>>>> +
>>>> enum dc_status (*add_dsc_to_stream_resource)(
>>>> struct dc *dc, struct dc_state *state,
>>>> struct dc_stream_state *stream); @@ -254,10
>>>> +251,9 @@ struct resource_pool {
>>>> struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
>>>> unsigned int hpo_dp_link_enc_count;
>>>> struct hpo_dp_link_encoder
>>>> *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> struct dc_3dlut *mpc_lut[MAX_PIPES];
>>>> struct dc_transfer_func *mpc_shaper[MAX_PIPES]; -#endif
>>>> +
>>>> struct {
>>>> unsigned int xtalin_clock_inKhz;
>>>> unsigned int dccg_ref_clock_inKhz; @@ -286,9 +282,7
>>>> @@ struct resource_pool {
>>>> struct dmcu *dmcu;
>>>> struct dmub_psr *psr;
>>>>
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> struct abm *multiple_abms[MAX_PIPES]; -#endif
>>>>
>>>> const struct resource_funcs *funcs;
>>>> const struct resource_caps *res_cap; @@ -380,7 +374,6 @@
>>>> struct pipe_ctx {
>>>> struct pipe_ctx *next_odm_pipe;
>>>> struct pipe_ctx *prev_odm_pipe;
>>>>
>>>> -#ifdef CONFIG_DRM_AMD_DC_DCN
>>>> struct _vcs_dpi_display_dlg_regs_st dlg_regs;
>>>> struct _vcs_dpi_display_ttu_regs_st ttu_regs;
>>>> struct _vcs_dpi_display_rq_regs_st rq_regs; @@ -390,7 +383,7
>>>> @@ struct pipe_ctx {
>>>> struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
>>>> int det_buffer_size_kb;
>>>> bool unbounded_req;
>>>> -#endif
>>>> +
>>>> union pipe_update_flags update_flags;
>>>> struct dwbc *dwbc;
>>>> struct mcif_wb *mcif_wb;
>>>> @@ -419,9 +412,7 @@ struct resource_context {
>>>> bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
>>>> unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
>>>> int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
>>>> -#if defined(CONFIG_DRM_AMD_DC_DCN)
>>>> bool is_mpc_3dlut_acquired[MAX_PIPES]; -#endif
>>>> };
>>>>
>>>> struct dce_bw_output {
>>>> @@ -484,9 +475,7 @@ struct dc_state {
>>>>
>>>> /* Note: these are big structures, do *not* put on stack! */
>>>> struct dm_pp_display_configuration pp_display_cfg; -#ifdef
>>>> CONFIG_DRM_AMD_DC_DCN
>>>> struct dcn_bw_internal_vars dcn_bw_vars; -#endif
>>>>
>>>> struct clk_mgr *clk_mgr;
>>>>
>>>> --
>>>> 2.35.1
>>>>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 08/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dce
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (6 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 07/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 09/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in gpio Stylon Wang
` (7 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
Alex Hung, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Alex Hung <alex.hung@amd.com>
[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.
This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in dce directory.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
.../drm/amd/display/dc/dce/dce_clock_source.c | 15 +------------
.../drm/amd/display/dc/dce/dce_clock_source.h | 12 +----------
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 10 ---------
.../amd/display/dc/dce/dce_stream_encoder.c | 21 +------------------
.../display/dc/dce110/dce110_hw_sequencer.c | 2 --
5 files changed, 3 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 760653e2b607..5e6fea85a7b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -918,7 +918,6 @@ static bool dce112_program_pix_clk(
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
struct bp_pixel_clock_parameters bp_pc_params = {0};
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
unsigned dp_dto_ref_100hz = 7000000;
@@ -932,7 +931,6 @@ static bool dce112_program_pix_clk(
REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
return true;
}
-#endif
/* First disable SS
* ATOMBIOS will enable by default SS on PLL for DP,
* do not disable it here
@@ -971,7 +969,6 @@ static bool dce112_program_pix_clk(
return true;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
static bool dcn31_program_pix_clk(
struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params,
@@ -1062,7 +1059,6 @@ static bool dcn31_program_pix_clk(
return true;
}
-#endif
static bool dce110_clock_source_power_down(
struct clock_source *clk_src)
@@ -1121,7 +1117,6 @@ static bool get_pixel_clk_frequency_100hz(
return false;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
// /1.001 rates
@@ -1171,7 +1166,6 @@ const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
return NULL;
}
-#endif
static bool dcn20_program_pix_clk(
struct clock_source *clock_source,
@@ -1218,7 +1212,6 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = {
.override_dp_pix_clk = dcn20_override_dp_pix_clk
};
-#if defined(CONFIG_DRM_AMD_DC_DCN)
static bool dcn3_program_pix_clk(
struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params,
@@ -1304,7 +1297,7 @@ static const struct clock_source_funcs dcn31_clk_src_funcs = {
.get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
};
-#endif
+
/*****************************************/
/* Constructor */
/*****************************************/
@@ -1690,7 +1683,6 @@ bool dcn20_clk_src_construct(
return ret;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dcn3_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
@@ -1706,9 +1698,7 @@ bool dcn3_clk_src_construct(
return ret;
}
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dcn31_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
@@ -1724,9 +1714,7 @@ bool dcn31_clk_src_construct(
return ret;
}
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dcn301_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
@@ -1742,4 +1730,3 @@ bool dcn301_clk_src_construct(
return ret;
}
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 069de7649c8c..9eec3524335f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -100,7 +100,6 @@
SRII(PIXEL_RATE_CNTL, OTG, 2),\
SRII(PIXEL_RATE_CNTL, OTG, 3)
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \
SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
SRII(PHASE, DP_DTO, 0),\
@@ -130,9 +129,7 @@
SRII(PIXEL_RATE_CNTL, OTG, 1),\
SRII(PIXEL_RATE_CNTL, OTG, 2),\
SRII(PIXEL_RATE_CNTL, OTG, 3)
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \
SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
SRII(PHASE, DP_DTO, 0),\
@@ -160,15 +157,13 @@
SRII(PIXEL_RATE_CNTL, OTG, 0),\
SRII(PIXEL_RATE_CNTL, OTG, 1)
-#endif
+
#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-
#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
SRII(PHASE, DP_DTO, 0),\
@@ -190,7 +185,6 @@
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
-#endif
#define CS_REG_FIELD_LIST(type) \
type PLL_REF_DIV_SRC; \
@@ -274,7 +268,6 @@ bool dcn20_clk_src_construct(
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dcn3_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
@@ -301,7 +294,6 @@ bool dcn31_clk_src_construct(
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask);
-#endif
/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
struct pixel_rate_range_table_entry {
@@ -312,10 +304,8 @@ struct pixel_rate_range_table_entry {
unsigned short div_factor;
};
-#if defined(CONFIG_DRM_AMD_DC_DCN)
extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
unsigned int pixel_rate_khz);
-#endif
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 8cd841320ded..7183ac5780a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -70,9 +70,7 @@
//Register access policy version
#define mmMP0_SMN_C2PMSG_91 0x1609B
-#if defined(CONFIG_DRM_AMD_DC_DCN)
static const uint32_t abm_gain_stepsize = 0x0060;
-#endif
static bool dce_dmcu_init(struct dmcu *dmcu)
{
@@ -333,7 +331,6 @@ static void dce_get_psr_wait_loop(
return;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
static void dcn10_get_dmcu_version(struct dmcu *dmcu)
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
@@ -930,7 +927,6 @@ static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset)
return false;
}
-#endif //(CONFIG_DRM_AMD_DC_DCN)
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
static void dcn10_forward_crc_window(struct dmcu *dmcu,
@@ -1021,7 +1017,6 @@ static const struct dmcu_funcs dce_funcs = {
.is_dmcu_initialized = dce_is_dmcu_initialized
};
-#if defined(CONFIG_DRM_AMD_DC_DCN)
static const struct dmcu_funcs dcn10_funcs = {
.dmcu_init = dcn10_dmcu_init,
.load_iram = dcn10_dmcu_load_iram,
@@ -1065,7 +1060,6 @@ static const struct dmcu_funcs dcn21_funcs = {
.lock_phy = dcn20_lock_phy,
.unlock_phy = dcn20_unlock_phy
};
-#endif
static void dce_dmcu_construct(
struct dce_dmcu *dmcu_dce,
@@ -1085,7 +1079,6 @@ static void dce_dmcu_construct(
dmcu_dce->dmcu_mask = dmcu_mask;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
static void dcn21_dmcu_construct(
struct dce_dmcu *dmcu_dce,
struct dc_context *ctx,
@@ -1103,7 +1096,6 @@ static void dcn21_dmcu_construct(
dmcu_dce->base.psp_version = psp_version;
}
}
-#endif
struct dmcu *dce_dmcu_create(
struct dc_context *ctx,
@@ -1126,7 +1118,6 @@ struct dmcu *dce_dmcu_create(
return &dmcu_dce->base;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
struct dmcu *dcn10_dmcu_create(
struct dc_context *ctx,
const struct dce_dmcu_registers *regs,
@@ -1189,7 +1180,6 @@ struct dmcu *dcn21_dmcu_create(
return &dmcu_dce->base;
}
-#endif
void dce_dmcu_destroy(struct dmcu **dmcu)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 779bc92a2968..a8c92b517df1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -136,7 +136,7 @@ static void dce110_update_generic_info_packet(
AFMT_GENERIC0_UPDATE, (packet_index == 0),
AFMT_GENERIC2_UPDATE, (packet_index == 2));
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
+
if (REG(AFMT_VBI_PACKET_CONTROL1)) {
switch (packet_index) {
case 0:
@@ -175,7 +175,6 @@ static void dce110_update_generic_info_packet(
break;
}
}
-#endif
}
static void dce110_update_hdmi_info_packet(
@@ -230,7 +229,6 @@ static void dce110_update_hdmi_info_packet(
HDMI_GENERIC1_SEND, send,
HDMI_GENERIC1_LINE, line);
break;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
case 4:
if (REG(HDMI_GENERIC_PACKET_CONTROL2))
REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
@@ -259,7 +257,6 @@ static void dce110_update_hdmi_info_packet(
HDMI_GENERIC1_SEND, send,
HDMI_GENERIC1_LINE, line);
break;
-#endif
default:
/* invalid HW packet index */
DC_LOG_WARNING(
@@ -277,7 +274,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
bool use_vsc_sdp_for_colorimetry,
uint32_t enable_sdp_splitting)
{
-#if defined(CONFIG_DRM_AMD_DC_DCN)
uint32_t h_active_start;
uint32_t v_active_start;
uint32_t misc0 = 0;
@@ -288,7 +284,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
uint8_t colorimetry_bpc;
uint8_t dynamic_range_rgb = 0; /*full range*/
uint8_t dynamic_range_ycbcr = 1; /*bt709*/
-#endif
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
@@ -329,10 +324,8 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (enc110->se_mask->DP_VID_N_MUL)
REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
-#endif
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
@@ -340,10 +333,8 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (REG(DP_MSA_MISC))
misc1 = REG_READ(DP_MSA_MISC);
-#endif
/* set color depth */
@@ -374,7 +365,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
/* set dynamic range and YCbCr range */
-#if defined(CONFIG_DRM_AMD_DC_DCN)
switch (hw_crtc_timing.display_color_depth) {
case COLOR_DEPTH_666:
colorimetry_bpc = 0;
@@ -454,7 +444,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
DP_DYN_RANGE, dynamic_range_rgb,
DP_YCBCR_RANGE, dynamic_range_ycbcr);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (REG(DP_MSA_COLORIMETRY))
REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
@@ -468,7 +457,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
DP_MSA_HTOTAL, hw_crtc_timing.h_total,
DP_MSA_VTOTAL, hw_crtc_timing.v_total);
-#endif
/* calcuate from vesa timing parameters
* h_active_start related to leading edge of sync
@@ -489,7 +477,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
hw_crtc_timing.v_front_porch;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* start at begining of left border */
if (REG(DP_MSA_TIMING_PARAM2))
REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
@@ -514,9 +501,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
-#endif
}
-#endif
}
static void dce110_stream_encoder_set_stream_attribute_helper(
@@ -787,7 +772,6 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (enc110->se_mask->HDMI_DB_DISABLE) {
/* for bring up, disable dp double TODO */
if (REG(HDMI_DB_CONTROL))
@@ -799,7 +783,6 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
}
-#endif
}
static void dce110_stream_encoder_stop_hdmi_info_packets(
@@ -825,7 +808,6 @@ static void dce110_stream_encoder_stop_hdmi_info_packets(
HDMI_GENERIC1_LINE, 0,
HDMI_GENERIC1_SEND, 0);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* stop generic packets 2 & 3 on HDMI */
if (REG(HDMI_GENERIC_PACKET_CONTROL2))
REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
@@ -844,7 +826,6 @@ static void dce110_stream_encoder_stop_hdmi_info_packets(
HDMI_GENERIC1_CONT, 0,
HDMI_GENERIC1_LINE, 0,
HDMI_GENERIC1_SEND, 0);
-#endif
}
static void dce110_stream_encoder_update_dp_info_packets(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 9fc1ba12ec19..7eff7811769d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1365,11 +1365,9 @@ static void program_scaler(const struct dc *dc,
{
struct tg_color color = {0};
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* TOFPGA */
if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
return;
-#endif
if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
get_surface_visual_confirm_color(pipe_ctx, &color);
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 09/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in gpio
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (7 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 08/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dce Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 10/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in irq Stylon Wang
` (6 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
Alex Hung, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Alex Hung <alex.hung@amd.com>
[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.
This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in gpio directory.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 3 +--
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c | 2 --
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h | 2 --
.../gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c | 2 --
.../gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h | 2 --
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 ----
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 4 ----
7 files changed, 1 insertion(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index d1c2ec58676d..0f4a22be8c40 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -73,7 +73,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120)
###############################################################################
# DCN 1x
###############################################################################
-ifdef CONFIG_DRM_AMD_DC_DCN
GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o
AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10))
@@ -114,7 +113,7 @@ GPIO_DCN315 = hw_translate_dcn315.o hw_factory_dcn315.o
AMD_DAL_GPIO_DCN315 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn315/,$(GPIO_DCN315))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN315)
-endif
+
###############################################################################
# Diagnostics on FPGA
###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
index 3b7df1ac26be..687d4f128480 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
@@ -22,7 +22,6 @@
* Authors: AMD
*
*/
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dm_services.h"
#include "include/gpio_types.h"
#include "../hw_factory.h"
@@ -266,4 +265,3 @@ void dal_hw_factory_dcn30_init(struct hw_factory *factory)
factory->funcs = &funcs;
}
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h
index 131e742b050a..e491af845b83 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h
@@ -22,7 +22,6 @@
* Authors: AMD
*
*/
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#ifndef __DAL_HW_FACTORY_DCN30_H__
#define __DAL_HW_FACTORY_DCN30_H__
@@ -30,4 +29,3 @@
void dal_hw_factory_dcn30_init(struct hw_factory *factory);
#endif /* __DAL_HW_FACTORY_DCN30_H__ */
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
index 6b6b7c7bd12f..3169c567475f 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
@@ -26,7 +26,6 @@
/*
* Pre-requisites: headers required by header of this unit
*/
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "hw_translate_dcn30.h"
#include "dm_services.h"
@@ -384,4 +383,3 @@ void dal_hw_translate_dcn30_init(struct hw_translate *tr)
tr->funcs = &funcs;
}
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h
index ed55410b7a4e..511a0dd49140 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h
@@ -22,7 +22,6 @@
* Authors: AMD
*
*/
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#ifndef __DAL_HW_TRANSLATE_DCN30_H__
#define __DAL_HW_TRANSLATE_DCN30_H__
@@ -32,4 +31,3 @@ struct hw_translate;
void dal_hw_translate_dcn30_init(struct hw_translate *tr);
#endif /* __DAL_HW_TRANSLATE_DCN30_H__ */
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 5c00ffde3996..ef4f69612097 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -48,13 +48,11 @@
#include "dce80/hw_factory_dce80.h"
#include "dce110/hw_factory_dce110.h"
#include "dce120/hw_factory_dce120.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dcn10/hw_factory_dcn10.h"
#include "dcn20/hw_factory_dcn20.h"
#include "dcn21/hw_factory_dcn21.h"
#include "dcn30/hw_factory_dcn30.h"
#include "dcn315/hw_factory_dcn315.h"
-#endif
#include "diagnostics/hw_factory_diag.h"
@@ -98,7 +96,6 @@ bool dal_hw_factory_init(
case DCE_VERSION_12_1:
dal_hw_factory_dce120_init(factory);
return true;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
case DCN_VERSION_1_0:
case DCN_VERSION_1_01:
dal_hw_factory_dcn10_init(factory);
@@ -121,7 +118,6 @@ bool dal_hw_factory_init(
case DCN_VERSION_3_15:
dal_hw_factory_dcn315_init(factory);
return true;
-#endif
default:
ASSERT_CRITICAL(false);
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 7a39cbc01f63..1db4f1414d7e 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -46,13 +46,11 @@
#include "dce80/hw_translate_dce80.h"
#include "dce110/hw_translate_dce110.h"
#include "dce120/hw_translate_dce120.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dcn10/hw_translate_dcn10.h"
#include "dcn20/hw_translate_dcn20.h"
#include "dcn21/hw_translate_dcn21.h"
#include "dcn30/hw_translate_dcn30.h"
#include "dcn315/hw_translate_dcn315.h"
-#endif
#include "diagnostics/hw_translate_diag.h"
@@ -93,7 +91,6 @@ bool dal_hw_translate_init(
case DCE_VERSION_12_1:
dal_hw_translate_dce120_init(translate);
return true;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
case DCN_VERSION_1_0:
case DCN_VERSION_1_01:
dal_hw_translate_dcn10_init(translate);
@@ -116,7 +113,6 @@ bool dal_hw_translate_init(
case DCN_VERSION_3_15:
dal_hw_translate_dcn315_init(translate);
return true;
-#endif
default:
BREAK_TO_DEBUGGER();
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 10/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in irq
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (8 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 09/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in gpio Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 11/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN for z10 Stylon Wang
` (5 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
Alex Hung, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Alex Hung <alex.hung@amd.com>
[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.
This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in irq directory.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
drivers/gpu/drm/amd/display/dc/irq/Makefile | 3 +--
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c | 3 ---
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h | 3 ---
drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 -----
4 files changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index f305d4c9a122..5f49048dde47 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -71,7 +71,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12)
###############################################################################
# DCN 1x
###############################################################################
-ifdef CONFIG_DRM_AMD_DC_DCN
IRQ_DCN1 = irq_service_dcn10.o
AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1))
@@ -136,7 +135,7 @@ IRQ_DCN31 = irq_service_dcn31.o
AMD_DAL_IRQ_DCN31= $(addprefix $(AMDDALPATH)/dc/irq/dcn31/,$(IRQ_DCN31))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN31)
-endif
+
###############################################################################
# DCN 315
###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
index ac0c6a62d17b..146cd1819912 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
@@ -22,8 +22,6 @@
*
*/
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-
#include "dm_services.h"
#include "include/logger_interface.h"
@@ -450,4 +448,3 @@ struct irq_service *dal_irq_service_dcn30_create(
return irq_service;
}
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h
index 080e21239688..c6c7b184d3c1 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h
@@ -23,8 +23,6 @@
*
*/
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-
#ifndef __DAL_IRQ_SERVICE_DCN30_H__
#define __DAL_IRQ_SERVICE_DCN30_H__
@@ -34,4 +32,3 @@ struct irq_service *dal_irq_service_dcn30_create(
struct irq_service_init_data *init_data);
#endif /* __DAL_IRQ_SERVICE_DCN30_H__ */
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
index a2a4fbeb83f8..cb38d4c527d4 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
@@ -37,13 +37,8 @@
#endif
#include "dce80/irq_service_dce80.h"
-
#include "dce120/irq_service_dce120.h"
-
-
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dcn10/irq_service_dcn10.h"
-#endif
#include "reg_helper.h"
#include "irq_service.h"
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 11/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN for z10
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (9 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 10/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in irq Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 12/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in amdgpu_dm Stylon Wang
` (4 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
Alex Hung, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Alex Hung <alex.hung@amd.com>
[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.
This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
for enabling z10.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++--------
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ----
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ----
3 files changed, 2 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1eeea7c184ae..e41a48f596a3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1674,7 +1674,6 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
return stream_mask;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
void dc_z10_restore(const struct dc *dc)
{
if (dc->hwss.z10_restore)
@@ -1686,7 +1685,7 @@ void dc_z10_save_init(struct dc *dc)
if (dc->hwss.z10_save_init)
dc->hwss.z10_save_init(dc);
}
-#endif
+
/*
* Applies given context to HW and copy it into current context.
* It's up to the user to release the src context afterwards.
@@ -1700,10 +1699,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
struct dc_state *old_state;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_z10_restore(dc);
dc_allow_idle_optimizations(dc, false);
-#endif
for (i = 0; i < context->stream_count; i++)
dc_streams[i] = context->streams[i];
@@ -2839,9 +2836,7 @@ static void commit_planes_for_stream(struct dc *dc,
struct pipe_ctx *top_pipe_to_program = NULL;
bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_z10_restore(dc);
-#endif
if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
/* Optimize seamless boot flag keeps clocks and watermarks high until
@@ -3298,9 +3293,8 @@ void dc_set_power_state(
case DC_ACPI_CM_POWER_STATE_D0:
dc_resource_state_construct(dc, dc->current_state);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_z10_restore(dc);
-#endif
+
if (dc->ctx->dmub_srv)
dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 9529b924742e..67ef357e5798 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -879,9 +879,7 @@ static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
{
-#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_z10_restore(dc);
-#endif
clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
}
@@ -3098,10 +3096,8 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active
if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
link->psr_settings.psr_allow_active = *allow_active;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (!link->psr_settings.psr_allow_active)
dc_z10_restore(dc);
-#endif
if (psr != NULL && link->psr_settings.psr_feature_enabled) {
psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index acca35d86c10..de8b214132a2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -333,7 +333,6 @@ bool dc_stream_set_cursor_attributes(
dc = stream->ctx->dc;
stream->cursor_attributes = *attributes;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_z10_restore(dc);
/* disable idle optimizations while updating cursor */
if (dc->idle_optimizations_allowed) {
@@ -341,7 +340,6 @@ bool dc_stream_set_cursor_attributes(
reset_idle_optimizations = true;
}
-#endif
program_cursor_attributes(dc, stream, attributes);
/* re-enable idle optimizations if necessary */
@@ -405,7 +403,6 @@ bool dc_stream_set_cursor_position(
}
dc = stream->ctx->dc;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_z10_restore(dc);
/* disable idle optimizations if enabling cursor */
@@ -414,7 +411,6 @@ bool dc_stream_set_cursor_position(
reset_idle_optimizations = true;
}
-#endif
stream->cursor_position = *position;
program_cursor_position(dc, stream, position);
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 12/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in amdgpu_dm
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (10 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 11/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN for z10 Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 13/15] drm/amd/display: remove unnecessary else by CONFIG_DRM_AMD_DC_DCN Stylon Wang
` (3 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
Alex Hung, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Alex Hung <alex.hung@amd.com>
[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.
This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in amdgpu_dm directory.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 ++-----------------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 6 ---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 ---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 -
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 -
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 --
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 4 --
7 files changed, 3 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 00ebda0bea44..2ea20dd7fccf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -83,7 +83,6 @@
#include <drm/drm_vblank.h>
#include <drm/drm_audio_component.h>
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
#include "dcn/dcn_1_0_offset.h"
@@ -92,7 +91,6 @@
#include "vega10_ip_offset.h"
#include "soc15_common.h"
-#endif
#include "modules/inc/mod_freesync.h"
#include "modules/power/power_helpers.h"
@@ -603,7 +601,6 @@ static void dm_crtc_high_irq(void *interrupt_params)
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
/**
* dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
@@ -827,7 +824,6 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
if (count > DMUB_TRACE_MAX_READ)
DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
}
-#endif /* CONFIG_DRM_AMD_DC_DCN */
static int dm_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
@@ -1125,9 +1121,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */
hw_params.dpia_supported = true;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
-#endif
break;
default:
break;
@@ -1189,7 +1183,6 @@ static void dm_dmub_hw_resume(struct amdgpu_device *adev)
}
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
{
uint64_t pt_base;
@@ -1244,8 +1237,7 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
pa_config->is_hvm_enabled = 0;
}
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN)
+
static void vblank_control_worker(struct work_struct *work)
{
struct vblank_control_work *vblank_work =
@@ -1282,8 +1274,6 @@ static void vblank_control_worker(struct work_struct *work)
kfree(vblank_work);
}
-#endif
-
static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
{
struct hpd_rx_irq_offload_work *offload_work;
@@ -1410,9 +1400,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
mutex_init(&adev->dm.dc_lock);
mutex_init(&adev->dm.audio_lock);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
spin_lock_init(&adev->dm.vblank_lock);
-#endif
if(amdgpu_dm_irq_init(adev)) {
DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
@@ -1505,12 +1493,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
init_data.flags.edp_no_power_sequencing = true;
-#ifdef CONFIG_DRM_AMD_DC_DCN
if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
-#endif
init_data.flags.seamless_boot_edp_requested = false;
@@ -1566,7 +1552,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
goto error;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
struct dc_phy_addr_space_config pa_config;
@@ -1575,7 +1560,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
// Call the DC init_memory func
dc_setup_system_context(adev->dm.dc, &pa_config);
}
-#endif
adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
if (!adev->dm.freesync_module) {
@@ -1587,14 +1571,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
amdgpu_dm_init_color_mod();
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (adev->dm.dc->caps.max_links > 0) {
adev->dm.vblank_control_workqueue =
create_singlethread_workqueue("dm_vblank_control_workqueue");
if (!adev->dm.vblank_control_workqueue)
DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
}
-#endif
#ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
@@ -1626,7 +1608,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
}
amdgpu_dm_outbox_init(adev);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
dmub_aux_setconfig_callback, false)) {
DRM_ERROR("amdgpu: fail to register dmub aux callback");
@@ -1640,7 +1621,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
DRM_ERROR("amdgpu: fail to register dmub hpd callback");
goto error;
}
-#endif /* CONFIG_DRM_AMD_DC_DCN */
}
if (amdgpu_dm_initialize_drm_device(adev)) {
@@ -1687,12 +1667,10 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
{
int i;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (adev->dm.vblank_control_workqueue) {
destroy_workqueue(adev->dm.vblank_control_workqueue);
adev->dm.vblank_control_workqueue = NULL;
}
-#endif
for (i = 0; i < adev->dm.display_indexes_num; i++) {
drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
@@ -2403,9 +2381,7 @@ static int dm_suspend(void *handle)
if (amdgpu_in_reset(adev)) {
mutex_lock(&dm->dc_lock);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_allow_idle_optimizations(adev->dm.dc, false);
-#endif
dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
@@ -3558,7 +3534,6 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
return 0;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Register IRQ sources and initialize IRQ callbacks */
static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
{
@@ -3747,7 +3722,6 @@ static int register_outbox_irq_handlers(struct amdgpu_device *adev)
return 0;
}
-#endif
/*
* Acquires the lock for the atomic state object and returns
@@ -4251,7 +4225,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
goto fail;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Use Outbox interrupt */
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(3, 0, 0):
@@ -4284,7 +4257,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break;
}
}
-#endif
/* Disable vblank IRQs aggressively for power-saving. */
adev_to_drm(adev)->vblank_disable_immediate = true;
@@ -4380,7 +4352,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
}
break;
default:
-#if defined(CONFIG_DRM_AMD_DC_DCN)
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
@@ -4406,7 +4377,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
adev->ip_versions[DCE_HWIP][0]);
goto fail;
}
-#endif
break;
}
@@ -4555,7 +4525,7 @@ static int dm_early_init(void *handle)
adev->mode_info.num_dig = 6;
break;
default:
-#if defined(CONFIG_DRM_AMD_DC_DCN)
+
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 0, 2):
case IP_VERSION(3, 0, 0):
@@ -4592,7 +4562,6 @@ static int dm_early_init(void *handle)
adev->ip_versions[DCE_HWIP][0]);
return -EINVAL;
}
-#endif
break;
}
@@ -6646,10 +6615,8 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
struct amdgpu_display_manager *dm = &adev->dm;
struct vblank_control_work *work;
-#endif
int rc = 0;
if (enable) {
@@ -6672,7 +6639,6 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
if (amdgpu_in_reset(adev))
return 0;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dm->vblank_control_workqueue) {
work = kzalloc(sizeof(*work), GFP_ATOMIC);
if (!work)
@@ -6690,7 +6656,6 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
queue_work(dm->vblank_control_workqueue, &work->work);
}
-#endif
return 0;
}
@@ -9362,14 +9327,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
/* Update the planes if changed or disable if we don't have any. */
if ((planes_count || acrtc_state->active_planes == 0) &&
acrtc_state->stream) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/*
* If PSR or idle optimizations are enabled then flush out
* any pending work before hardware programming.
*/
if (dm->vblank_control_workqueue)
flush_workqueue(dm->vblank_control_workqueue);
-#endif
bundle->stream_update.stream = acrtc_state->stream;
if (new_pcrtc_state->mode_changed) {
@@ -9702,21 +9665,18 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
if (dc_state) {
/* if there mode set or reset, disable eDP PSR */
if (mode_set_reset_required) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dm->vblank_control_workqueue)
flush_workqueue(dm->vblank_control_workqueue);
-#endif
+
amdgpu_dm_psr_disable_all(dm);
}
dm_enable_per_frame_crtc_master_sync(dc_state);
mutex_lock(&dm->dc_lock);
WARN_ON(!dc_commit_state(dm->dc, dc_state));
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Allow idle optimization when vblank count is 0 for display off */
if (dm->active_vblank_irq_count == 0)
dc_allow_idle_optimizations(dm->dc,true);
-#endif
mutex_unlock(&dm->dc_lock);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 321279bc877b..3cc5c15303e6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -358,14 +358,12 @@ struct amdgpu_display_manager {
*/
struct mutex audio_lock;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/**
* @vblank_lock:
*
* Guards access to deferred vblank work state.
*/
spinlock_t vblank_lock;
-#endif
/**
* @audio_component:
@@ -469,14 +467,12 @@ struct amdgpu_display_manager {
struct hdcp_workqueue *hdcp_workqueue;
#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/**
* @vblank_control_workqueue:
*
* Deferred work for vblank control events.
*/
struct workqueue_struct *vblank_control_workqueue;
-#endif
struct drm_atomic_state *cached_state;
struct dc_state *cached_dc_state;
@@ -493,14 +489,12 @@ struct amdgpu_display_manager {
*/
const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/**
* @active_vblank_irq_count:
*
* number of currently active vblank irqs
*/
uint32_t active_vblank_irq_count;
-#endif
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
/**
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 5193afb067d3..9a406378d906 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -295,9 +295,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
case LINK_RATE_RBR2:
case LINK_RATE_HIGH2:
case LINK_RATE_HIGH3:
-#if defined(CONFIG_DRM_AMD_DC_DCN)
case LINK_RATE_UHBR10:
-#endif
break;
default:
valid_input = false;
@@ -3415,7 +3413,6 @@ static int disable_hpd_get(void *data, u64 *val)
DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
disable_hpd_set, "%llu\n");
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/*
* Temporary w/a to force sst sequence in M42D DP2 mst receiver
* Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
@@ -3463,7 +3460,6 @@ static int dp_ignore_cable_id_get(void *data, u64 *val)
}
DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
dp_ignore_cable_id_set, "%llu\n");
-#endif
/*
* Sets the DC visual confirm debug option from the given string.
@@ -3612,12 +3608,10 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
adev, &mst_topo_fops);
debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
&dtn_log_fops);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
&dp_set_mst_en_for_sst_ops);
debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
&dp_ignore_cable_id_ops);
-#endif
debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
&visual_confirm_fops);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 28cf24f6ab32..7c799ddc1d27 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -977,9 +977,7 @@ void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
// TODO
}
-#if defined(CONFIG_DRM_AMD_DC_DCN)
void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
{
/* TODO: add periodic detection implementation */
}
-#endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 0542034530b1..23e82b839c20 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -45,12 +45,10 @@
#include "amdgpu_dm_debugfs.h"
#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dc/dcn20/dcn20_resource.h"
bool is_timing_changed(struct dc_stream_state *cur_stream,
struct dc_stream_state *new_stream);
-#endif
static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index c561e0d872d6..85628ad59e6c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -46,8 +46,6 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
void
dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-
struct dsc_mst_fairness_vars {
int pbn;
bool dsc_enabled;
@@ -64,6 +62,5 @@ bool needs_dsc_aux_workaround(struct dc_link *link);
void pre_validate_dsc(struct drm_atomic_state *state,
struct dm_atomic_state **dm_state_ptr,
struct dsc_mst_fairness_vars *vars);
-#endif
#endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 13b1751e69bf..141fd2721501 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -29,7 +29,6 @@
#include "amdgpu_dm.h"
#include "modules/power/power_helpers.h"
-#ifdef CONFIG_DRM_AMD_DC_DCN
static bool link_supports_psrsu(struct dc_link *link)
{
struct dc *dc = link->ctx->dc;
@@ -53,7 +52,6 @@ static bool link_supports_psrsu(struct dc_link *link)
return true;
}
-#endif
/*
* amdgpu_dm_set_psr_caps() - set link psr capabilities
@@ -73,11 +71,9 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link)
link->psr_settings.psr_feature_enabled = false;
} else {
-#ifdef CONFIG_DRM_AMD_DC_DCN
if (link_supports_psrsu(link))
link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
else
-#endif
link->psr_settings.psr_version = DC_PSR_VERSION_1;
link->psr_settings.psr_feature_enabled = true;
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 13/15] drm/amd/display: remove unnecessary else by CONFIG_DRM_AMD_DC_DCN
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (11 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 12/15] drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in amdgpu_dm Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 14/15] Revert "drm/amd/display: Fix DCN3 B0 DP Alt Mapping" Stylon Wang
` (2 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
Alex Hung, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Alex Hung <alex.hung@amd.com>
[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.
This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
guards for #if-#else clause.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f702919a2279..6774dd8bb53e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2315,14 +2315,10 @@ enum dc_status resource_map_pool_resources(
/* Add ABM to the resource if on EDP */
if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (pool->abm)
pipe_ctx->stream_res.abm = pool->abm;
else
pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
-#else
- pipe_ctx->stream_res.abm = pool->abm;
-#endif
}
for (i = 0; i < context->stream_count; i++)
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 14/15] Revert "drm/amd/display: Fix DCN3 B0 DP Alt Mapping"
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (12 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 13/15] drm/amd/display: remove unnecessary else by CONFIG_DRM_AMD_DC_DCN Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-06 15:42 ` [PATCH 15/15] drm/amd/display: 3.2.185 Stylon Wang
2022-05-09 13:14 ` [PATCH 00/15] DC Patches May 9, 2022 Wheeler, Daniel
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
wayne.lin, Bhawanpreet.Lakha, Nicholas Kazlauskas,
agustin.gutierrez, pavle.kotarac
This reverts commit 4b7786d87fb3adf3e534c4f1e4f824d8700b786b.
Commit 4b7786d87fb3 "drm/amd/display: Fix DCN3 B0 DP Alt
Mapping" is causing 2nd USB-C display not lighting up.
Phy id remapping is done differently than is assumed in this
patch.
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index f3ef52350b03..ccf1b71a8269 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1248,12 +1248,6 @@ static struct stream_encoder *dcn31_stream_encoder_create(
return NULL;
}
- if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
- ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
- if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD))
- eng_id = eng_id + 3; // For B0 only. C->F, D->G.
- }
-
dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
eng_id, vpg, afmt,
&stream_enc_regs[eng_id],
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 15/15] drm/amd/display: 3.2.185
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (13 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 14/15] Revert "drm/amd/display: Fix DCN3 B0 DP Alt Mapping" Stylon Wang
@ 2022-05-06 15:42 ` Stylon Wang
2022-05-09 13:14 ` [PATCH 00/15] DC Patches May 9, 2022 Wheeler, Daniel
15 siblings, 0 replies; 29+ messages in thread
From: Stylon Wang @ 2022-05-06 15:42 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Aric Cyr, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, solomon.chiu, Aurabindo.Pillai,
wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Aric Cyr <aric.cyr@amd.com>
This version brings along following fixes:
- Refactor LTTPR code
- Fix PSR after hibernate
- Fix DC build errors
- Fix IRQ unregister error when unloading amdgpu
- Improve DP link training
- Fix stutter
- Remove redundant CONFIG_DRM_AMD_DC_DCN guards
- Fix 2nd connected USB-C display not lighting up
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 0f86bb809e04..26c24db8f1da 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.184"
+#define DC_VER "3.2.185"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.35.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* RE: [PATCH 00/15] DC Patches May 9, 2022
2022-05-06 15:41 [PATCH 00/15] DC Patches May 9, 2022 Stylon Wang
` (14 preceding siblings ...)
2022-05-06 15:42 ` [PATCH 15/15] drm/amd/display: 3.2.185 Stylon Wang
@ 2022-05-09 13:14 ` Wheeler, Daniel
2022-05-09 13:56 ` Paul Menzel
2022-05-09 14:00 ` How are the DC patches tested? (was: [PATCH 00/15] DC Patches May 9, 2022) Paul Menzel
15 siblings, 2 replies; 29+ messages in thread
From: Wheeler, Daniel @ 2022-05-09 13:14 UTC (permalink / raw)
To: Wang, Chao-kai (Stylon), amd-gfx
Cc: Wang, Chao-kai (Stylon), Li, Sun peng (Leo),
Lakha, Bhawanpreet, Zhuo, Qingqing (Lillian),
Siqueira, Rodrigo, Li, Roman, Chiu, Solomon, Pillai, Aurabindo,
Lin, Wayne, Wentland, Harry, Gutierrez, Agustin, Kotarac, Pavle
[Public]
Hi all,
This week this patchset was tested on the following systems:
Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Sapphire Pulse RX5700XT with the following display types:
4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Reference AMD RX6800 with the following display types:
4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz and DSC via USB-C to DP DSC Hub with 3x 4k 60hz.
Tested on Ubuntu 22.04 with Kernel Version 5.16, and ChromeOS
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook | Twitter | amd.com
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Stylon Wang
Sent: May 6, 2022 11:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
Subject: [PATCH 00/15] DC Patches May 9, 2022
This DC patchset brings improvements in multiple areas. In summary, we highlight:
- Refactor LTTPR code
- Fix PSR after hibernate
- Fix DC build errors
- Fix IRQ unregister error when unloading amdgpu
- Improve DP link training
- Fix stutter
- Remove redundant CONFIG_DRM_AMD_DC_DCN guards
- Fix 2nd connected USB-C display not lighting up
---
Alan Liu (1):
drm/amd/display: do not disable an invalid irq source in hdp finish
Alex Hung (7):
drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc
drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dce
drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in gpio
drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in irq
drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN for z10
drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in amdgpu_dm
drm/amd/display: remove unnecessary else by CONFIG_DRM_AMD_DC_DCN
Aric Cyr (1):
drm/amd/display: 3.2.185
Evgenii Krasnikov (1):
drm/amd/display: Reset cached PSR parameters after hibernate
Josip Pavic (2):
drm/amd/display: move definition of dc_flip_addrs struct
drm/amd/display: do not wait for vblank during pipe programming
Michael Strauss (1):
drm/amd/display: Refactor LTTPR cap retrieval
Stylon Wang (1):
Revert "drm/amd/display: Fix DCN3 B0 DP Alt Mapping"
Wenjing Liu (1):
drm/amd/display: do not calculate DP2.0 SST payload when link is off
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 +----
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 6 -
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 -
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 -
.../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 6 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 -
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 -
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 4 -
drivers/gpu/drm/amd/display/dc/Makefile | 2 -
.../display/dc/bios/command_table_helper2.c | 3 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 41 +---
.../gpu/drm/amd/display/dc/core/dc_debug.c | 2 -
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 179 ++++++++++--------
.../drm/amd/display/dc/core/dc_link_dpia.c | 2 -
.../gpu/drm/amd/display/dc/core/dc_resource.c | 25 +--
.../gpu/drm/amd/display/dc/core/dc_stream.c | 12 --
drivers/gpu/drm/amd/display/dc/dc.h | 51 +----
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 16 ++
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 +
.../drm/amd/display/dc/dce/dce_clock_source.c | 15 +- .../drm/amd/display/dc/dce/dce_clock_source.h | 12 +- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 10 -
.../amd/display/dc/dce/dce_stream_encoder.c | 21 +-
.../display/dc/dce110/dce110_hw_sequencer.c | 2 -
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 -
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 6 -
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 -
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 3 +-
.../display/dc/gpio/dcn30/hw_factory_dcn30.c | 2 -
.../display/dc/gpio/dcn30/hw_factory_dcn30.h | 2 -
.../dc/gpio/dcn30/hw_translate_dcn30.c | 2 -
.../dc/gpio/dcn30/hw_translate_dcn30.h | 2 -
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 -
.../drm/amd/display/dc/gpio/hw_translate.c | 4 -
.../gpu/drm/amd/display/dc/inc/core_types.h | 17 +-
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 3 +-
drivers/gpu/drm/amd/display/dc/irq/Makefile | 3 +-
.../display/dc/irq/dcn30/irq_service_dcn30.c | 3 -
.../display/dc/irq/dcn30/irq_service_dcn30.h | 3 -
.../gpu/drm/amd/display/dc/irq/irq_service.c | 5 -
.../amd/display/include/link_service_types.h | 6 +
42 files changed, 161 insertions(+), 391 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 00/15] DC Patches May 9, 2022
2022-05-09 13:14 ` [PATCH 00/15] DC Patches May 9, 2022 Wheeler, Daniel
@ 2022-05-09 13:56 ` Paul Menzel
2022-05-09 14:00 ` How are the DC patches tested? (was: [PATCH 00/15] DC Patches May 9, 2022) Paul Menzel
1 sibling, 0 replies; 29+ messages in thread
From: Paul Menzel @ 2022-05-09 13:56 UTC (permalink / raw)
To: Daniel Wheeler
Cc: Chao-kai Wang, Sun Peng Li, Harry Wentland, Qingqing Zhuo,
Rodrigo Siqueira, Roman Li, amd-gfx, Solomon Chiu,
Aurabindo Pillai, Wayne Lin, Bhawanpreet Lakha,
Agustin Gutierrez, Pavle Kotarac
Dear Daniel,
Am 09.05.22 um 15:14 schrieb Wheeler, Daniel:
[…]
> This week this patchset was tested on the following systems:
>
> Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following
> display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p
> 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and
> then DP to DVI/VGA)
>
> Sapphire Pulse RX5700XT with the following display types: 4k 60hz
> (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to
> DVI/VGA)
>
> Reference AMD RX6800 with the following display types: 4k 60hz (via
> DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and
> USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
>
> Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz and
> DSC via USB-C to DP DSC Hub with 3x 4k 60hz.
>
> Tested on Ubuntu 22.04 with Kernel Version 5.16, and ChromeOS
Kind regards,
Paul
^ permalink raw reply [flat|nested] 29+ messages in thread
* How are the DC patches tested? (was: [PATCH 00/15] DC Patches May 9, 2022)
2022-05-09 13:14 ` [PATCH 00/15] DC Patches May 9, 2022 Wheeler, Daniel
2022-05-09 13:56 ` Paul Menzel
@ 2022-05-09 14:00 ` Paul Menzel
2022-05-09 14:15 ` Rodrigo Siqueira Jordao
1 sibling, 1 reply; 29+ messages in thread
From: Paul Menzel @ 2022-05-09 14:00 UTC (permalink / raw)
To: Daniel Wheeler
Cc: Chao-kai Wang, Sun Peng Li, Harry Wentland, Qingqing Zhuo,
Rodrigo Siqueira, Roman Li, amd-gfx, Solomon Chiu,
Aurabindo Pillai, Wayne Lin, Bhawanpreet Lakha,
Agustin Gutierrez, Pavle Kotarac
[Sorry for the incomplete first message.]
Dear Daniel,
Am 09.05.22 um 15:14 schrieb Wheeler, Daniel:
[…]
> This week this patchset was tested on the following systems:
>
> Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following
> display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p
> 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and
> then DP to DVI/VGA)
>
> Sapphire Pulse RX5700XT with the following display types: 4k 60hz
> (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to
> DVI/VGA)
>
> Reference AMD RX6800 with the following display types: 4k 60hz (via
> DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and
> USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
>
> Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz and
> DSC via USB-C to DP DSC Hub with 3x 4k 60hz.
>
> Tested on Ubuntu 22.04 with Kernel Version 5.16, and ChromeOS
I am curious, what this means exactly? You clone the Ubuntu Linux 5.16
kernel source, and then apply your patches on top? (Do they even apply?)
The same for Chrome OS. Do you use Chrome OS Flex [1] with the systems
you listed? If not, what Google Chromebooks/-boxes did you test with?
The Linux kernel version is also tied for a device and Chrome OS
release. Please mention those too.
Is it documented somewhere, what tests you run exactly?
Kind regards,
Paul
[1]: https://chromeenterprise.google/os/chromeosflex/
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: How are the DC patches tested? (was: [PATCH 00/15] DC Patches May 9, 2022)
2022-05-09 14:00 ` How are the DC patches tested? (was: [PATCH 00/15] DC Patches May 9, 2022) Paul Menzel
@ 2022-05-09 14:15 ` Rodrigo Siqueira Jordao
2022-05-09 14:28 ` How are the DC patches tested? Paul Menzel
0 siblings, 1 reply; 29+ messages in thread
From: Rodrigo Siqueira Jordao @ 2022-05-09 14:15 UTC (permalink / raw)
To: Paul Menzel, Daniel Wheeler
Cc: Chao-kai Wang, Sun Peng Li, Harry Wentland, Qingqing Zhuo,
Roman Li, amd-gfx, Solomon Chiu, Aurabindo Pillai, Wayne Lin,
Bhawanpreet Lakha, Agustin Gutierrez, Pavle Kotarac
On 2022-05-09 10:00, Paul Menzel wrote:
> [Sorry for the incomplete first message.]
>
> Dear Daniel,
>
>
> Am 09.05.22 um 15:14 schrieb Wheeler, Daniel:
>
> […]
>
>> This week this patchset was tested on the following systems:
>>
>> Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following
>> display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p
>> 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and
>> then DP to DVI/VGA)
>>
>> Sapphire Pulse RX5700XT with the following display types: 4k 60hz
>> (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to
>> DVI/VGA)
>>
>> Reference AMD RX6800 with the following display types: 4k 60hz (via
>> DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and
>> USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
>>
>> Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz and
>> DSC via USB-C to DP DSC Hub with 3x 4k 60hz.
>>
>> Tested on Ubuntu 22.04 with Kernel Version 5.16, and ChromeOS
>
> I am curious, what this means exactly? You clone the Ubuntu Linux 5.16
> kernel source, and then apply your patches on top? (Do they even apply?)
All of these "promotion" patches are tested by using
amd-staging-drm-next. In a few words:
1. We get the latest code from amd-staging-drm-next;
2. We apply these weekly promotion patches on top of it;
3. We compile, run unit tests, and run many manual tests (Daniel does that).
If everything is alright with Daniel's tests, we feel confident to merge
these series on top amd-staging-drm-next (we are basically trying to
avoid regressions here).
Anyway, maybe we can rephrase:
Tested on Ubuntu 22.04 with Kernel Version 5.16, and ChromeOS
to
Tested on Ubuntu 22.04 and ChromeOS with amd-staging-drm-next +
promotion patches.
> The same for Chrome OS. Do you use Chrome OS Flex [1] with the systems
> you listed? If not, what Google Chromebooks/-boxes did you test with?
> The Linux kernel version is also tied for a device and Chrome OS
> release. Please mention those too.
>
> Is it documented somewhere, what tests you run exactly?
We run IGT tests, some scripts that validate some specific areas, and
Daniel has an extensive set of manual tests.
Thanks
Siqueira
>
> Kind regards,
>
> Paul
>
>
> [1]:
> https://chromeenterprise.google/os/chromeosflex/
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: How are the DC patches tested?
2022-05-09 14:15 ` Rodrigo Siqueira Jordao
@ 2022-05-09 14:28 ` Paul Menzel
2022-05-09 15:21 ` Wheeler, Daniel
0 siblings, 1 reply; 29+ messages in thread
From: Paul Menzel @ 2022-05-09 14:28 UTC (permalink / raw)
To: Rodrigo Siqueira Jordao
Cc: Chao-kai Wang, Sun Peng Li, Bhawanpreet Lakha, Qingqing Zhuo,
Roman Li, amd-gfx, Solomon Chiu, Daniel Wheeler,
Aurabindo Pillai, Wayne Lin, Harry Wentland, Agustin Gutierrez,
Pavle Kotarac
Dear Rodrigo,
Thank you for the quick response.
Am 09.05.22 um 16:15 schrieb Rodrigo Siqueira Jordao:
> On 2022-05-09 10:00, Paul Menzel wrote:
>> Am 09.05.22 um 15:14 schrieb Wheeler, Daniel:
>>
>> […]
>>
>>> This week this patchset was tested on the following systems:
>>>
>>> Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following
>>> display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p
>>> 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and
>>> then DP to DVI/VGA)
>>>
>>> Sapphire Pulse RX5700XT with the following display types: 4k 60hz
>>> (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to
>>> DVI/VGA)
>>>
>>> Reference AMD RX6800 with the following display types: 4k 60hz (via
>>> DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and
>>> USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
>>>
>>> Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz and
>>> DSC via USB-C to DP DSC Hub with 3x 4k 60hz.
>>>
>>> Tested on Ubuntu 22.04 with Kernel Version 5.16, and ChromeOS
>>
>> I am curious, what this means exactly? You clone the Ubuntu Linux 5.16
>> kernel source, and then apply your patches on top? (Do they even apply?)
>
> All of these "promotion" patches are tested by using
> amd-staging-drm-next. In a few words:
>
> 1. We get the latest code from amd-staging-drm-next;
> 2. We apply these weekly promotion patches on top of it;
> 3. We compile, run unit tests, and run many manual tests (Daniel does
> that).
>
> If everything is alright with Daniel's tests, we feel confident to merge
> these series on top amd-staging-drm-next (we are basically trying to
> avoid regressions here).
>
> Anyway, maybe we can rephrase:
>
> Tested on Ubuntu 22.04 with Kernel Version 5.16, and ChromeOS
>
> to
>
> Tested on Ubuntu 22.04 and ChromeOS with amd-staging-drm-next +
> promotion patches.
Yes, that’d be great. Maybe even reference the commit hash from the
commit on top of *amd-staging-drm-next*.
(Nit: ChromeOS → Chrome OS)
>> The same for Chrome OS. Do you use Chrome OS Flex [1] with the systems
>> you listed? If not, what Google Chromebooks/-boxes did you test with?
>> The Linux kernel version is also tied for a device and Chrome OS
>> release. Please mention those too.
As written, the used Chrome OS version (and devices) would be helpful too.
>> Is it documented somewhere, what tests you run exactly?
>
> We run IGT tests, some scripts that validate some specific areas, and
> Daniel has an extensive set of manual tests.
Kind regards,
Paul
^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: How are the DC patches tested?
2022-05-09 14:28 ` How are the DC patches tested? Paul Menzel
@ 2022-05-09 15:21 ` Wheeler, Daniel
2022-05-10 10:53 ` Paul Menzel
0 siblings, 1 reply; 29+ messages in thread
From: Wheeler, Daniel @ 2022-05-09 15:21 UTC (permalink / raw)
To: Paul Menzel, Siqueira, Rodrigo
Cc: Wang, Chao-kai (Stylon), Li, Sun peng (Leo),
Lakha, Bhawanpreet, Zhuo, Qingqing (Lillian),
Li, Roman, amd-gfx, Chiu, Solomon, Pillai, Aurabindo, Lin,
Wayne, Wentland, Harry, Gutierrez, Agustin, Kotarac, Pavle
[Public]
Hi Paul,
I've made some edits to my cover letter to hopefully make it clearer with what is being done.
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U
Lenovo Thinkpad T14s Gen2, with AMD Ryzen 5 5650U
Sapphire Pulse RX5700XT
Reference AMD RX6800
Engineering board with Ryzen 9 5900H
These systems were tested on the following display types:
eDP, (1080p 60hz [4500U, 5650U, 5900H])
VGA and DVI (1680x1050 60HZ [DP to VGA/DVI, USB-C to DVI/VGA])
DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz [Includes USB-C to DP/HDMI adapters])
MST tested with Startech MST14DP123DP and 2x 4k 60Hz displays
DSC tested with Cable Matters 101075 (DP to 3x DP), and 201375 (USB-C to 3x DP) with 3x 4k60 displays
The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to):
Changing display configurations and settings
Benchmark testing
Feature testing (Freesync, etc.)
Automated testing includes (but is not limited to):
Script testing (scripts to automate some of the manual checks)
IGT testing
The patchset consists of the most recent amd-staging-drm-next branch with a selection of patches added on top of it. This goes for both Ubuntu testing and Chrome OS testing.
Tested on Ubuntu 22.04 and Chrome OS
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com
-----Original Message-----
From: Paul Menzel <pmenzel@molgen.mpg.de>
Sent: May 9, 2022 10:28 AM
To: Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>
Cc: Wheeler, Daniel <Daniel.Wheeler@amd.com>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Li, Roman <Roman.Li@amd.com>; amd-gfx@lists.freedesktop.org; Chiu, Solomon <Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
Subject: Re: How are the DC patches tested?
Dear Rodrigo,
Thank you for the quick response.
Am 09.05.22 um 16:15 schrieb Rodrigo Siqueira Jordao:
> On 2022-05-09 10:00, Paul Menzel wrote:
>> Am 09.05.22 um 15:14 schrieb Wheeler, Daniel:
>>
>> […]
>>
>>> This week this patchset was tested on the following systems:
>>>
>>> Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following
>>> display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI),
>>> 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP
>>> and then DP to DVI/VGA)
>>>
>>> Sapphire Pulse RX5700XT with the following display types: 4k 60hz
>>> (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to
>>> DVI/VGA)
>>>
>>> Reference AMD RX6800 with the following display types: 4k 60hz (via
>>> DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and
>>> USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
>>>
>>> Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz and
>>> DSC via USB-C to DP DSC Hub with 3x 4k 60hz.
>>>
>>> Tested on Ubuntu 22.04 with Kernel Version 5.16, and ChromeOS
>>
>> I am curious, what this means exactly? You clone the Ubuntu Linux
>> 5.16 kernel source, and then apply your patches on top? (Do they even
>> apply?)
>
> All of these "promotion" patches are tested by using
> amd-staging-drm-next. In a few words:
>
> 1. We get the latest code from amd-staging-drm-next; 2. We apply these
> weekly promotion patches on top of it; 3. We compile, run unit tests,
> and run many manual tests (Daniel does that).
>
> If everything is alright with Daniel's tests, we feel confident to
> merge these series on top amd-staging-drm-next (we are basically
> trying to avoid regressions here).
>
> Anyway, maybe we can rephrase:
>
> Tested on Ubuntu 22.04 with Kernel Version 5.16, and ChromeOS
>
> to
>
> Tested on Ubuntu 22.04 and ChromeOS with amd-staging-drm-next +
> promotion patches.
Yes, that’d be great. Maybe even reference the commit hash from the commit on top of *amd-staging-drm-next*.
(Nit: ChromeOS → Chrome OS)
>> The same for Chrome OS. Do you use Chrome OS Flex [1] with the
>> systems you listed? If not, what Google Chromebooks/-boxes did you test with?
>> The Linux kernel version is also tied for a device and Chrome OS
>> release. Please mention those too.
As written, the used Chrome OS version (and devices) would be helpful too.
>> Is it documented somewhere, what tests you run exactly?
>
> We run IGT tests, some scripts that validate some specific areas, and
> Daniel has an extensive set of manual tests.
Kind regards,
Paul
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: How are the DC patches tested?
2022-05-09 15:21 ` Wheeler, Daniel
@ 2022-05-10 10:53 ` Paul Menzel
0 siblings, 0 replies; 29+ messages in thread
From: Paul Menzel @ 2022-05-10 10:53 UTC (permalink / raw)
To: Daniel Wheeler
Cc: Chao-kai Wang, Sun peng Li, Harry Wentland, Qingqing Zhuo,
Rodrigo Siqueira, Roman Li, amd-gfx, Solomon Chiu,
Aurabindo Pillai, Wayne Lin, Bhawanpreet Lakha,
Agustin Gutierrez, Pavle Kotarac
Dear Daniel,
Am 09.05.22 um 17:21 schrieb Wheeler, Daniel:
> I've made some edits to my cover letter to hopefully make it clearer
> with what is being done.
Thank you.
> Hi all,
>
> This week this patchset was tested on the following systems:
>
> HP Envy 360, with Ryzen 5 4500U
> Lenovo Thinkpad T14s Gen2, with AMD Ryzen 5 5650U
> Sapphire Pulse RX5700XT
> Reference AMD RX6800
> Engineering board with Ryzen 9 5900H
>
> These systems were tested on the following display types:
> eDP, (1080p 60hz [4500U, 5650U, 5900H])
> VGA and DVI (1680x1050 60HZ [DP to VGA/DVI, USB-C to DVI/VGA])
> DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz [Includes USB-C to DP/HDMI adapters])
>
> MST tested with Startech MST14DP123DP and 2x 4k 60Hz displays
> DSC tested with Cable Matters 101075 (DP to 3x DP), and 201375 (USB-C to 3x DP) with 3x 4k60 displays
>
> The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to):
> Changing display configurations and settings
> Benchmark testing
> Feature testing (Freesync, etc.)
>
> Automated testing includes (but is not limited to):
> Script testing (scripts to automate some of the manual checks)
> IGT testing
>
> The patchset consists of the most recent amd-staging-drm-next branch with a selection of patches added on top of it. This goes for both Ubuntu testing and Chrome OS testing.
Please mention the commit hash of the commit at the top of
amd-staging-drm-next.
>
> Tested on Ubuntu 22.04 and Chrome OS
I still do not see the Chrome OS version and devices listed. I think,
that information would be valuable.
>
> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Kind regards,
Paul
^ permalink raw reply [flat|nested] 29+ messages in thread