[PATCH v2 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl

[PATCH v2 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl

[Maíra Canal]

As the enum entries dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp
are not used on the codebase, drop those entries from enum
dm_swizzle_mode.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
v1 -> v2:
- Replace "enum" to "enum entries" (André Almeida).
- Describe changes in imperative mood (André Almeida).
---
 .../dc/dml/dcn20/display_mode_vba_20.c        | 26 +++++-------------
 .../dc/dml/dcn20/display_mode_vba_20v2.c      | 26 +++++-------------
 .../dc/dml/dcn21/display_mode_vba_21.c        | 27 +++++--------------
 .../amd/display/dc/dml/display_mode_enums.h   |  2 --
 .../display/dc/dml/dml_wrapper_translation.c  |  9 -------
 5 files changed, 19 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index d3b5b6fedf04..4e4cb0927057 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -938,7 +938,7 @@ static unsigned int CalculateVMAndRowBytes(
 		*MetaRowByte = 0;
 	}
 
-	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
+	if (SurfaceTiling == dm_sw_linear) {
 		MacroTileSizeBytes = 256;
 		MacroTileHeight = BlockHeight256Bytes;
 	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
@@ -3347,26 +3347,12 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 										== dm_420_8
 								|| mode_lib->vba.SourcePixelFormat[k]
 										== dm_420_10))
-				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
-						|| mode_lib->vba.SurfaceTiling[k]
-								== dm_sw_gfx7_2d_thin_l_vp)
-						&& !((mode_lib->vba.SourcePixelFormat[k]
-								== dm_444_64
+				|| (mode_lib->vba.DCCEnable[k] == true
+						&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
 								|| mode_lib->vba.SourcePixelFormat[k]
-										== dm_444_32)
-								&& mode_lib->vba.SourceScan[k]
-										== dm_horz
-								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
-										== true
-								&& mode_lib->vba.DCCEnable[k]
-										== false))
-						|| (mode_lib->vba.DCCEnable[k] == true
-								&& (mode_lib->vba.SurfaceTiling[k]
-										== dm_sw_linear
-										|| mode_lib->vba.SourcePixelFormat[k]
-												== dm_420_8
-										|| mode_lib->vba.SourcePixelFormat[k]
-												== dm_420_10)))) {
+										== dm_420_8
+								|| mode_lib->vba.SourcePixelFormat[k]
+										== dm_420_10))) {
 			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 63bbdf8b8678..eaa0cdb599ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -998,7 +998,7 @@ static unsigned int CalculateVMAndRowBytes(
 		*MetaRowByte = 0;
 	}
 
-	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
+	if (SurfaceTiling == dm_sw_linear) {
 		MacroTileSizeBytes = 256;
 		MacroTileHeight = BlockHeight256Bytes;
 	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
@@ -3454,26 +3454,12 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
 										== dm_420_8
 								|| mode_lib->vba.SourcePixelFormat[k]
 										== dm_420_10))
-				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
-						|| mode_lib->vba.SurfaceTiling[k]
-								== dm_sw_gfx7_2d_thin_l_vp)
-						&& !((mode_lib->vba.SourcePixelFormat[k]
-								== dm_444_64
+				|| (mode_lib->vba.DCCEnable[k] == true
+						&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
 								|| mode_lib->vba.SourcePixelFormat[k]
-										== dm_444_32)
-								&& mode_lib->vba.SourceScan[k]
-										== dm_horz
-								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
-										== true
-								&& mode_lib->vba.DCCEnable[k]
-										== false))
-						|| (mode_lib->vba.DCCEnable[k] == true
-								&& (mode_lib->vba.SurfaceTiling[k]
-										== dm_sw_linear
-										|| mode_lib->vba.SourcePixelFormat[k]
-												== dm_420_8
-										|| mode_lib->vba.SourcePixelFormat[k]
-												== dm_420_10)))) {
+										== dm_420_8
+								|| mode_lib->vba.SourcePixelFormat[k]
+										== dm_420_10))) {
 			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 8a7485e21d53..198d81861ac5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -1342,7 +1342,7 @@ static unsigned int CalculateVMAndRowBytes(
 		*MetaRowByte = 0;
 	}
 
-	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
+	if (SurfaceTiling == dm_sw_linear) {
 		MacroTileSizeBytes = 256;
 		MacroTileHeight = BlockHeight256Bytes;
 	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
@@ -3579,26 +3579,13 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 										== dm_420_8
 								|| mode_lib->vba.SourcePixelFormat[k]
 										== dm_420_10))
-				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
-						|| mode_lib->vba.SurfaceTiling[k]
-								== dm_sw_gfx7_2d_thin_l_vp)
-						&& !((mode_lib->vba.SourcePixelFormat[k]
-								== dm_444_64
+				|| (mode_lib->vba.DCCEnable[k] == true
+						&& (mode_lib->vba.SurfaceTiling[k]
+								== dm_sw_linear
 								|| mode_lib->vba.SourcePixelFormat[k]
-										== dm_444_32)
-								&& mode_lib->vba.SourceScan[k]
-										== dm_horz
-								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
-										== true
-								&& mode_lib->vba.DCCEnable[k]
-										== false))
-						|| (mode_lib->vba.DCCEnable[k] == true
-								&& (mode_lib->vba.SurfaceTiling[k]
-										== dm_sw_linear
-										|| mode_lib->vba.SourcePixelFormat[k]
-												== dm_420_8
-										|| mode_lib->vba.SourcePixelFormat[k]
-												== dm_420_10)))) {
+										== dm_420_8
+								|| mode_lib->vba.SourcePixelFormat[k]
+										== dm_420_10))) {
 			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index f394b3f3922a..0e06727d40b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -89,8 +89,6 @@ enum dm_swizzle_mode {
 	dm_sw_var_s_x = 29,
 	dm_sw_var_d_x = 30,
 	dm_sw_var_r_x = 31,
-	dm_sw_gfx7_2d_thin_l_vp,
-	dm_sw_gfx7_2d_thin_gl,
 };
 enum lb_depth {
 	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
index 4ec5310a2962..9edcb6fc83c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
@@ -35,15 +35,6 @@ static void gfx10array_mode_to_dml_params(
 	case DC_ARRAY_LINEAR_GENERAL:
 		*sw_mode = dm_sw_linear;
 		break;
-	case DC_ARRAY_2D_TILED_THIN1:
-// DC_LEGACY_TILING_ADDR_GEN_ZERO - undefined as per current code hence removed
-#if 0
-		if (compat_level == DC_LEGACY_TILING_ADDR_GEN_ZERO)
-			*sw_mode = dm_sw_gfx7_2d_thin_l_vp;
-		else
-			*sw_mode = dm_sw_gfx7_2d_thin_gl;
-#endif
-		break;
 	default:
 		ASSERT(0); /* Not supported */
 		break;
-- 
2.36.1

[PATCH v2 2/4] drm/amd/display: Remove duplicated CalculateWriteBackDISPCLK

[Maíra Canal]

The functions dml30_CalculateWriteBackDISPCLK and
dml31_CalculateWriteBackDISPCLK are identical. Therefor, to avoid code
duplication, replace dml31_CalculateWriteBackDISPCLK by
dml30_CalculateWriteBackDISPCLK

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
v1 -> v2:
- Describe changes in imperative mood (André Almeida).
---
 .../dc/dml/dcn31/display_mode_vba_31.c        | 24 ++-----------------
 .../dc/dml/dcn31/display_mode_vba_31.h        | 11 ---------
 2 files changed, 2 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 3fab19134480..3bc529f0b0fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -2085,7 +2085,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 		if (v->WritebackEnable[k]) {
 			v->WritebackDISPCLK = dml_max(
 					v->WritebackDISPCLK,
-					dml31_CalculateWriteBackDISPCLK(
+					dml30_CalculateWriteBackDISPCLK(
 							v->WritebackPixelFormat[k],
 							v->PixelClock[k],
 							v->WritebackHRatio[k],
@@ -3470,26 +3470,6 @@ static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLa
 	}
 }
 
-double dml31_CalculateWriteBackDISPCLK(
-		enum source_format_class WritebackPixelFormat,
-		double PixelClock,
-		double WritebackHRatio,
-		double WritebackVRatio,
-		unsigned int WritebackHTaps,
-		unsigned int WritebackVTaps,
-		long WritebackSourceWidth,
-		long WritebackDestinationWidth,
-		unsigned int HTotal,
-		unsigned int WritebackLineBufferSize)
-{
-	double DISPCLK_H, DISPCLK_V, DISPCLK_HB;
-
-	DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
-	DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal;
-	DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth;
-	return dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB);
-}
-
 static double CalculateWriteBackDelay(
 		enum source_format_class WritebackPixelFormat,
 		double WritebackHRatio,
@@ -4055,7 +4035,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		if (v->WritebackEnable[k] == true) {
 			v->WritebackRequiredDISPCLK = dml_max(
 					v->WritebackRequiredDISPCLK,
-					dml31_CalculateWriteBackDISPCLK(
+					dml30_CalculateWriteBackDISPCLK(
 							v->WritebackPixelFormat[k],
 							v->PixelClock[k],
 							v->WritebackHRatio[k],
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
index 90be612f26b2..654362adcaa9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
@@ -28,16 +28,5 @@
 
 void dml31_recalculate(struct display_mode_lib *mode_lib);
 void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
-double dml31_CalculateWriteBackDISPCLK(
-		enum source_format_class WritebackPixelFormat,
-		double PixelClock,
-		double WritebackHRatio,
-		double WritebackVRatio,
-		unsigned int WritebackHTaps,
-		unsigned int WritebackVTaps,
-		long   WritebackSourceWidth,
-		long   WritebackDestinationWidth,
-		unsigned int HTotal,
-		unsigned int WritebackLineBufferSize);
 
 #endif /* __DML31_DISPLAY_MODE_VBA_H__ */
-- 
2.36.1

[PATCH v2 3/4] drm/amd/display: Remove parameters from rq_dlg_get_dlg_reg

[Maíra Canal]

Across all DCN's (except DCN32, that has a separate
rq_dlg_get_dlg_reg), the parameters const bool vm_en, const bool
ignore_viewport_pos, and const bool immediate_flip_support are not used
on the function. Therefore, change the rq_dlg_get_dlg_reg signature
by deleting those parameters.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
v1 -> v2:
- Replace "enum" to "enum entries" (André Almeida).
---
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  |  3 +--
 .../dc/dml/dcn20/display_rq_dlg_calc_20.c     |  5 +----
 .../dc/dml/dcn20/display_rq_dlg_calc_20.h     |  5 +----
 .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c   |  5 +----
 .../dc/dml/dcn20/display_rq_dlg_calc_20v2.h   |  5 +----
 .../dc/dml/dcn21/display_rq_dlg_calc_21.c     |  5 +----
 .../dc/dml/dcn21/display_rq_dlg_calc_21.h     |  5 +----
 .../dc/dml/dcn30/display_rq_dlg_calc_30.c     | 18 +++---------------
 .../dc/dml/dcn30/display_rq_dlg_calc_30.h     |  5 +----
 .../dc/dml/dcn31/display_rq_dlg_calc_31.c     | 19 +++----------------
 .../dc/dml/dcn31/display_rq_dlg_calc_31.h     |  5 +----
 .../dc/dml/dcn314/display_rq_dlg_calc_314.c   | 15 ++-------------
 .../dc/dml/dcn314/display_rq_dlg_calc_314.h   |  5 +----
 .../drm/amd/display/dc/dml/display_mode_lib.h |  5 +----
 .../gpu/drm/amd/display/dc/dml/dml_wrapper.c  |  3 +--
 15 files changed, 20 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index dc60b835e938..d9cfb29a2651 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -857,8 +857,7 @@ void dcn20_calculate_dlg_params(
 				pipe_cnt,
 				pipe_idx,
 				cstate_en,
-				context->bw_ctx.bw.dcn.clk.p_state_change_support,
-				false, false, true);
+				context->bw_ctx.bw.dcn.clk.p_state_change_support);
 
 		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
 				&context->res_ctx.pipe_ctx[i].rq_regs,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index 548cdef8a8ad..d0a4c69b47c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -1553,10 +1553,7 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
 		const unsigned int num_pipes,
 		const unsigned int pipe_idx,
 		const bool cstate_en,
-		const bool pstate_en,
-		const bool vm_en,
-		const bool ignore_viewport_pos,
-		const bool immediate_flip_support)
+		const bool pstate_en)
 {
 	display_rq_params_st rq_param = {0};
 	display_dlg_sys_params_st dlg_sys_param = {0};
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
index 8b23867e97c1..36c3692e53b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
@@ -65,9 +65,6 @@ void dml20_rq_dlg_get_dlg_reg(
 		const unsigned int num_pipes,
 		const unsigned int pipe_idx,
 		const bool cstate_en,
-		const bool pstate_en,
-		const bool vm_en,
-		const bool ignore_viewport_pos,
-		const bool immediate_flip_support);
+		const bool pstate_en);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
index 0fc9f3e3ffae..17df9d31c11f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
@@ -1554,10 +1554,7 @@ void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
 		const unsigned int num_pipes,
 		const unsigned int pipe_idx,
 		const bool cstate_en,
-		const bool pstate_en,
-		const bool vm_en,
-		const bool ignore_viewport_pos,
-		const bool immediate_flip_support)
+		const bool pstate_en)
 {
 	display_rq_params_st rq_param = {0};
 	display_dlg_sys_params_st dlg_sys_param = {0};
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
index 2b4e46ea1c3d..f524f1ccfe41 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
@@ -65,9 +65,6 @@ void dml20v2_rq_dlg_get_dlg_reg(
 		const unsigned int num_pipes,
 		const unsigned int pipe_idx,
 		const bool cstate_en,
-		const bool pstate_en,
-		const bool vm_en,
-		const bool ignore_viewport_pos,
-		const bool immediate_flip_support);
+		const bool pstate_en);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index 618f4b682ab1..502dafc6dd79 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -1662,10 +1662,7 @@ void dml21_rq_dlg_get_dlg_reg(
 		const unsigned int num_pipes,
 		const unsigned int pipe_idx,
 		const bool cstate_en,
-		const bool pstate_en,
-		const bool vm_en,
-		const bool ignore_viewport_pos,
-		const bool immediate_flip_support)
+		const bool pstate_en)
 {
 	display_rq_params_st rq_param = {0};
 	display_dlg_sys_params_st dlg_sys_param = {0};
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
index af6ad0ca9cf8..822c68089ca8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
@@ -65,9 +65,6 @@ void dml21_rq_dlg_get_dlg_reg(
 		const unsigned int num_pipes,
 		const unsigned int pipe_idx,
 		const bool cstate_en,
-		const bool pstate_en,
-		const bool vm_en,
-		const bool ignore_viewport_pos,
-		const bool immediate_flip_support);
+		const bool pstate_en);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
index 8179be1f34bb..b3bdb7283a7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
@@ -898,10 +898,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
 	const display_rq_dlg_params_st rq_dlg_param,
 	const display_dlg_sys_params_st dlg_sys_param,
 	const bool cstate_en,
-	const bool pstate_en,
-	const bool vm_en,
-	const bool ignore_viewport_pos,
-	const bool immediate_flip_support)
+	const bool pstate_en)
 {
 	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
 	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
@@ -1031,9 +1028,6 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
 
 	dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
 	dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
-	dml_print("DML_DLG: %s:  vm_en     = %d\n", __func__, vm_en);
-	dml_print("DML_DLG: %s:  ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
-	dml_print("DML_DLG: %s:  immediate_flip_support  = %d\n", __func__, immediate_flip_support);
 
 	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
 	dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
@@ -1746,10 +1740,7 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
 	const unsigned int num_pipes,
 	const unsigned int pipe_idx,
 	const bool cstate_en,
-	const bool pstate_en,
-	const bool vm_en,
-	const bool ignore_viewport_pos,
-	const bool immediate_flip_support)
+	const bool pstate_en)
 {
 	display_rq_params_st rq_param = { 0 };
 	display_dlg_sys_params_st dlg_sys_param = { 0 };
@@ -1785,10 +1776,7 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
 		rq_param.dlg,
 		dlg_sys_param,
 		cstate_en,
-		pstate_en,
-		vm_en,
-		ignore_viewport_pos,
-		immediate_flip_support);
+		pstate_en);
 	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
index 625e41f8d575..d28ed3ae3f94 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
@@ -61,9 +61,6 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
 		const unsigned int            num_pipes,
 		const unsigned int            pipe_idx,
 		const bool                    cstate_en,
-		const bool                    pstate_en,
-		const bool                    vm_en,
-		const bool                    ignore_viewport_pos,
-		const bool                    immediate_flip_support);
+		const bool                    pstate_en);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
index 66b82e4f05c6..c36dd3a79871 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
@@ -859,10 +859,7 @@ static void dml_rq_dlg_get_dlg_params(
 		const display_rq_dlg_params_st *rq_dlg_param,
 		const display_dlg_sys_params_st *dlg_sys_param,
 		const bool cstate_en,
-		const bool pstate_en,
-		const bool vm_en,
-		const bool ignore_viewport_pos,
-		const bool immediate_flip_support)
+		const bool pstate_en)
 {
 	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
 	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
@@ -970,9 +967,6 @@ static void dml_rq_dlg_get_dlg_params(
 
 	dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
 	dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
-	dml_print("DML_DLG: %s: vm_en     = %d\n", __func__, vm_en);
-	dml_print("DML_DLG: %s: ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
-	dml_print("DML_DLG: %s: immediate_flip_support  = %d\n", __func__, immediate_flip_support);
 
 	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
 	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
@@ -983,7 +977,6 @@ static void dml_rq_dlg_get_dlg_params(
 	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
 	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end;	// 15 bits
 
-	//set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
 	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);	// From VBA
 
 	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
@@ -1576,10 +1569,7 @@ void dml31_rq_dlg_get_dlg_reg(
 		const unsigned int num_pipes,
 		const unsigned int pipe_idx,
 		const bool cstate_en,
-		const bool pstate_en,
-		const bool vm_en,
-		const bool ignore_viewport_pos,
-		const bool immediate_flip_support)
+		const bool pstate_en)
 {
 	display_rq_params_st rq_param = {0};
 	display_dlg_sys_params_st dlg_sys_param = {0};
@@ -1610,10 +1600,7 @@ void dml31_rq_dlg_get_dlg_reg(
 			&rq_param.dlg,
 			&dlg_sys_param,
 			cstate_en,
-			pstate_en,
-			vm_en,
-			ignore_viewport_pos,
-			immediate_flip_support);
+			pstate_en);
 	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
index 8ee991351699..5b0b438a9804 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
@@ -61,9 +61,6 @@ void dml31_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
 		const unsigned int            num_pipes,
 		const unsigned int            pipe_idx,
 		const bool                    cstate_en,
-		const bool                    pstate_en,
-		const bool                    vm_en,
-		const bool                    ignore_viewport_pos,
-		const bool                    immediate_flip_support);
+		const bool                    pstate_en);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
index 61ee9ba063a7..37ecc4a6ae11 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
@@ -943,11 +943,7 @@ static void dml_rq_dlg_get_dlg_params(
 		display_ttu_regs_st *disp_ttu_regs,
 		const display_rq_dlg_params_st *rq_dlg_param,
 		const display_dlg_sys_params_st *dlg_sys_param,
-		const bool cstate_en,
-		const bool pstate_en,
-		const bool vm_en,
-		const bool ignore_viewport_pos,
-		const bool immediate_flip_support)
+		const bool cstate_en)
 {
 	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
 	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
@@ -1060,9 +1056,6 @@ static void dml_rq_dlg_get_dlg_params(
 
 	dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
 	dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
-	dml_print("DML_DLG: %s: vm_en     = %d\n", __func__, vm_en);
-	dml_print("DML_DLG: %s: ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
-	dml_print("DML_DLG: %s: immediate_flip_support  = %d\n", __func__, immediate_flip_support);
 
 	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
 	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
@@ -1073,7 +1066,6 @@ static void dml_rq_dlg_get_dlg_params(
 	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
 	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end;	// 15 bits
 
-	//set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
 	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);	// From VBA
 
 	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
@@ -1725,9 +1717,6 @@ void dml314_rq_dlg_get_dlg_reg(
 			&rq_param.dlg,
 			&dlg_sys_param,
 			cstate_en,
-			pstate_en,
-			vm_en,
-			ignore_viewport_pos,
-			immediate_flip_support);
+			pstate_en);
 	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
index 49cb85d1056c..d2c1ba8b7ebf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
@@ -62,9 +62,6 @@ void dml314_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
 		const unsigned int            num_pipes,
 		const unsigned int            pipe_idx,
 		const bool                    cstate_en,
-		const bool                    pstate_en,
-		const bool                    vm_en,
-		const bool                    ignore_viewport_pos,
-		const bool                    immediate_flip_support);
+		const bool                    pstate_en);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index 2bdd6ed22611..8a4b60a278b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -55,10 +55,7 @@ struct dml_funcs {
 			const unsigned int num_pipes,
 			const unsigned int pipe_idx,
 			const bool cstate_en,
-			const bool pstate_en,
-			const bool vm_en,
-			const bool ignore_viewport_pos,
-			const bool immediate_flip_support);
+			const bool pstate_en);
 	void (*rq_dlg_get_rq_reg)(
 		struct display_mode_lib *mode_lib,
 		display_rq_regs_st *rq_regs,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
index b4b51e51fc25..e39e2363ea0a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
@@ -1647,8 +1647,7 @@ static void dml_calculate_dlg_params(
 				pipe_cnt,
 				pipe_idx,
 				cstate_en,
-				context->bw_ctx.bw.dcn.clk.p_state_change_support,
-				false, false, true);
+				context->bw_ctx.bw.dcn.clk.p_state_change_support);
 
 		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
 				&context->res_ctx.pipe_ctx[i].rq_regs,
-- 
2.36.1

Re: [PATCH v2 3/4] drm/amd/display: Remove parameters from rq_dlg_get_dlg_reg

[Rodrigo Siqueira Jordao]

Hi Maira,

First of all, thanks a lot for this patch. This change is really helpful 
for reducing the stack size. I just have few comments inline.

On 2022-07-21 14:36, Maíra Canal wrote:
> Across all DCN's (except DCN32, that has a separate
> rq_dlg_get_dlg_reg), the parameters const bool vm_en, const bool
> ignore_viewport_pos, and const bool immediate_flip_support are not used
> on the function. Therefore, change the rq_dlg_get_dlg_reg signature
> by deleting those parameters.
> 
> Signed-off-by: Maíra Canal <mairacanal@riseup.net>
> ---
> v1 -> v2:
> - Replace "enum" to "enum entries" (André Almeida).
> ---
>   .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  |  3 +--
>   .../dc/dml/dcn20/display_rq_dlg_calc_20.c     |  5 +----
>   .../dc/dml/dcn20/display_rq_dlg_calc_20.h     |  5 +----
>   .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c   |  5 +----
>   .../dc/dml/dcn20/display_rq_dlg_calc_20v2.h   |  5 +----
>   .../dc/dml/dcn21/display_rq_dlg_calc_21.c     |  5 +----
>   .../dc/dml/dcn21/display_rq_dlg_calc_21.h     |  5 +----
>   .../dc/dml/dcn30/display_rq_dlg_calc_30.c     | 18 +++---------------
>   .../dc/dml/dcn30/display_rq_dlg_calc_30.h     |  5 +----
>   .../dc/dml/dcn31/display_rq_dlg_calc_31.c     | 19 +++----------------
>   .../dc/dml/dcn31/display_rq_dlg_calc_31.h     |  5 +----
>   .../dc/dml/dcn314/display_rq_dlg_calc_314.c   | 15 ++-------------
>   .../dc/dml/dcn314/display_rq_dlg_calc_314.h   |  5 +----
>   .../drm/amd/display/dc/dml/display_mode_lib.h |  5 +----
>   .../gpu/drm/amd/display/dc/dml/dml_wrapper.c  |  3 +--
>   15 files changed, 20 insertions(+), 88 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> index dc60b835e938..d9cfb29a2651 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> @@ -857,8 +857,7 @@ void dcn20_calculate_dlg_params(
>   				pipe_cnt,
>   				pipe_idx,
>   				cstate_en,
> -				context->bw_ctx.bw.dcn.clk.p_state_change_support,
> -				false, false, true);
> +				context->bw_ctx.bw.dcn.clk.p_state_change_support);
>   
>   		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
>   				&context->res_ctx.pipe_ctx[i].rq_regs,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
> index 548cdef8a8ad..d0a4c69b47c8 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
> @@ -1553,10 +1553,7 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
>   		const unsigned int num_pipes,
>   		const unsigned int pipe_idx,
>   		const bool cstate_en,
> -		const bool pstate_en,
> -		const bool vm_en,
> -		const bool ignore_viewport_pos,
> -		const bool immediate_flip_support)
> +		const bool pstate_en)
>   {
>   	display_rq_params_st rq_param = {0};
>   	display_dlg_sys_params_st dlg_sys_param = {0};
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
> index 8b23867e97c1..36c3692e53b8 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
> @@ -65,9 +65,6 @@ void dml20_rq_dlg_get_dlg_reg(
>   		const unsigned int num_pipes,
>   		const unsigned int pipe_idx,
>   		const bool cstate_en,
> -		const bool pstate_en,
> -		const bool vm_en,
> -		const bool ignore_viewport_pos,
> -		const bool immediate_flip_support);
> +		const bool pstate_en);
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
> index 0fc9f3e3ffae..17df9d31c11f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
> @@ -1554,10 +1554,7 @@ void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
>   		const unsigned int num_pipes,
>   		const unsigned int pipe_idx,
>   		const bool cstate_en,
> -		const bool pstate_en,
> -		const bool vm_en,
> -		const bool ignore_viewport_pos,
> -		const bool immediate_flip_support)
> +		const bool pstate_en)
>   {
>   	display_rq_params_st rq_param = {0};
>   	display_dlg_sys_params_st dlg_sys_param = {0};
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
> index 2b4e46ea1c3d..f524f1ccfe41 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
> @@ -65,9 +65,6 @@ void dml20v2_rq_dlg_get_dlg_reg(
>   		const unsigned int num_pipes,
>   		const unsigned int pipe_idx,
>   		const bool cstate_en,
> -		const bool pstate_en,
> -		const bool vm_en,
> -		const bool ignore_viewport_pos,
> -		const bool immediate_flip_support);
> +		const bool pstate_en);
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
> index 618f4b682ab1..502dafc6dd79 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
> @@ -1662,10 +1662,7 @@ void dml21_rq_dlg_get_dlg_reg(
>   		const unsigned int num_pipes,
>   		const unsigned int pipe_idx,
>   		const bool cstate_en,
> -		const bool pstate_en,
> -		const bool vm_en,
> -		const bool ignore_viewport_pos,
> -		const bool immediate_flip_support)
> +		const bool pstate_en)
>   {
>   	display_rq_params_st rq_param = {0};
>   	display_dlg_sys_params_st dlg_sys_param = {0};
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
> index af6ad0ca9cf8..822c68089ca8 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
> @@ -65,9 +65,6 @@ void dml21_rq_dlg_get_dlg_reg(
>   		const unsigned int num_pipes,
>   		const unsigned int pipe_idx,
>   		const bool cstate_en,
> -		const bool pstate_en,
> -		const bool vm_en,
> -		const bool ignore_viewport_pos,
> -		const bool immediate_flip_support);
> +		const bool pstate_en);
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
> index 8179be1f34bb..b3bdb7283a7e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
> @@ -898,10 +898,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
>   	const display_rq_dlg_params_st rq_dlg_param,
>   	const display_dlg_sys_params_st dlg_sys_param,
>   	const bool cstate_en,
> -	const bool pstate_en,
> -	const bool vm_en,
> -	const bool ignore_viewport_pos,
> -	const bool immediate_flip_support)
> +	const bool pstate_en)
>   {
>   	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
>   	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
> @@ -1031,9 +1028,6 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
>   
>   	dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
>   	dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
> -	dml_print("DML_DLG: %s:  vm_en     = %d\n", __func__, vm_en);
> -	dml_print("DML_DLG: %s:  ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
> -	dml_print("DML_DLG: %s:  immediate_flip_support  = %d\n", __func__, immediate_flip_support);
>   
>   	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
>   	dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
> @@ -1746,10 +1740,7 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
>   	const unsigned int num_pipes,
>   	const unsigned int pipe_idx,
>   	const bool cstate_en,
> -	const bool pstate_en,
> -	const bool vm_en,
> -	const bool ignore_viewport_pos,
> -	const bool immediate_flip_support)
> +	const bool pstate_en)
>   {
>   	display_rq_params_st rq_param = { 0 };
>   	display_dlg_sys_params_st dlg_sys_param = { 0 };
> @@ -1785,10 +1776,7 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
>   		rq_param.dlg,
>   		dlg_sys_param,
>   		cstate_en,
> -		pstate_en,
> -		vm_en,
> -		ignore_viewport_pos,
> -		immediate_flip_support);
> +		pstate_en);
>   	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
>   }
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
> index 625e41f8d575..d28ed3ae3f94 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
> @@ -61,9 +61,6 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
>   		const unsigned int            num_pipes,
>   		const unsigned int            pipe_idx,
>   		const bool                    cstate_en,
> -		const bool                    pstate_en,
> -		const bool                    vm_en,
> -		const bool                    ignore_viewport_pos,
> -		const bool                    immediate_flip_support);
> +		const bool                    pstate_en);
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> index 66b82e4f05c6..c36dd3a79871 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> @@ -859,10 +859,7 @@ static void dml_rq_dlg_get_dlg_params(
>   		const display_rq_dlg_params_st *rq_dlg_param,
>   		const display_dlg_sys_params_st *dlg_sys_param,
>   		const bool cstate_en,
> -		const bool pstate_en,
> -		const bool vm_en,
> -		const bool ignore_viewport_pos,
> -		const bool immediate_flip_support)
> +		const bool pstate_en)
>   {
>   	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
>   	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
> @@ -970,9 +967,6 @@ static void dml_rq_dlg_get_dlg_params(
>   
>   	dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
>   	dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
> -	dml_print("DML_DLG: %s: vm_en     = %d\n", __func__, vm_en);
> -	dml_print("DML_DLG: %s: ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
> -	dml_print("DML_DLG: %s: immediate_flip_support  = %d\n", __func__, immediate_flip_support);
>   
>   	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
>   	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
> @@ -983,7 +977,6 @@ static void dml_rq_dlg_get_dlg_params(
>   	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
>   	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end;	// 15 bits
>   
> -	//set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
>   	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);	// From VBA
>   
>   	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
> @@ -1576,10 +1569,7 @@ void dml31_rq_dlg_get_dlg_reg(
>   		const unsigned int num_pipes,
>   		const unsigned int pipe_idx,
>   		const bool cstate_en,
> -		const bool pstate_en,
> -		const bool vm_en,
> -		const bool ignore_viewport_pos,
> -		const bool immediate_flip_support)
> +		const bool pstate_en)
>   {
>   	display_rq_params_st rq_param = {0};
>   	display_dlg_sys_params_st dlg_sys_param = {0};
> @@ -1610,10 +1600,7 @@ void dml31_rq_dlg_get_dlg_reg(
>   			&rq_param.dlg,
>   			&dlg_sys_param,
>   			cstate_en,
> -			pstate_en,
> -			vm_en,
> -			ignore_viewport_pos,
> -			immediate_flip_support);
> +			pstate_en);
>   	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
>   }
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
> index 8ee991351699..5b0b438a9804 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
> @@ -61,9 +61,6 @@ void dml31_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
>   		const unsigned int            num_pipes,
>   		const unsigned int            pipe_idx,
>   		const bool                    cstate_en,
> -		const bool                    pstate_en,
> -		const bool                    vm_en,
> -		const bool                    ignore_viewport_pos,
> -		const bool                    immediate_flip_support);
> +		const bool                    pstate_en);
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
> index 61ee9ba063a7..37ecc4a6ae11 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
> @@ -943,11 +943,7 @@ static void dml_rq_dlg_get_dlg_params(
>   		display_ttu_regs_st *disp_ttu_regs,
>   		const display_rq_dlg_params_st *rq_dlg_param,
>   		const display_dlg_sys_params_st *dlg_sys_param,
> -		const bool cstate_en,
> -		const bool pstate_en,
> -		const bool vm_en,
> -		const bool ignore_viewport_pos,
> -		const bool immediate_flip_support)
> +		const bool cstate_en)
>   {
>   	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
>   	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
> @@ -1060,9 +1056,6 @@ static void dml_rq_dlg_get_dlg_params(
>   
>   	dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
>   	dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);

hmmm... I'm not sure if I missed something, but you dropped the variable 
pstate_en from the parameter list, but you still have it here. Is this 
correct?

> -	dml_print("DML_DLG: %s: vm_en     = %d\n", __func__, vm_en);
> -	dml_print("DML_DLG: %s: ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
> -	dml_print("DML_DLG: %s: immediate_flip_support  = %d\n", __func__, immediate_flip_support);

Why are we dropping these logs? It is already hard to debug DML code, 
and reducing the amount of information that we can get does not sound 
good to me.

Thanks
Siqueira

>   
>   	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
>   	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
> @@ -1073,7 +1066,6 @@ static void dml_rq_dlg_get_dlg_params(
>   	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
>   	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end;	// 15 bits
>   
> -	//set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
>   	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);	// From VBA
>   
>   	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
> @@ -1725,9 +1717,6 @@ void dml314_rq_dlg_get_dlg_reg(
>   			&rq_param.dlg,
>   			&dlg_sys_param,
>   			cstate_en,
> -			pstate_en,
> -			vm_en,
> -			ignore_viewport_pos,
> -			immediate_flip_support);
> +			pstate_en);
>   	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
>   }
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
> index 49cb85d1056c..d2c1ba8b7ebf 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
> @@ -62,9 +62,6 @@ void dml314_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
>   		const unsigned int            num_pipes,
>   		const unsigned int            pipe_idx,
>   		const bool                    cstate_en,
> -		const bool                    pstate_en,
> -		const bool                    vm_en,
> -		const bool                    ignore_viewport_pos,
> -		const bool                    immediate_flip_support);
> +		const bool                    pstate_en);
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
> index 2bdd6ed22611..8a4b60a278b5 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
> @@ -55,10 +55,7 @@ struct dml_funcs {
>   			const unsigned int num_pipes,
>   			const unsigned int pipe_idx,
>   			const bool cstate_en,
> -			const bool pstate_en,
> -			const bool vm_en,
> -			const bool ignore_viewport_pos,
> -			const bool immediate_flip_support);
> +			const bool pstate_en);
>   	void (*rq_dlg_get_rq_reg)(
>   		struct display_mode_lib *mode_lib,
>   		display_rq_regs_st *rq_regs,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
> index b4b51e51fc25..e39e2363ea0a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
> @@ -1647,8 +1647,7 @@ static void dml_calculate_dlg_params(
>   				pipe_cnt,
>   				pipe_idx,
>   				cstate_en,
> -				context->bw_ctx.bw.dcn.clk.p_state_change_support,
> -				false, false, true);
> +				context->bw_ctx.bw.dcn.clk.p_state_change_support);
>   
>   		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
>   				&context->res_ctx.pipe_ctx[i].rq_regs,

Re: [PATCH v2 3/4] drm/amd/display: Remove parameters from rq_dlg_get_dlg_reg

[Maíra Canal]

Hi Siqueira,

On 7/22/22 17:11, Rodrigo Siqueira Jordao wrote:
> Hi Maira,
> 
> First of all, thanks a lot for this patch. This change is really helpful
> for reducing the stack size. I just have few comments inline.


Thank you for the feedback!

> 
> On 2022-07-21 14:36, Maíra Canal wrote:
>> Across all DCN's (except DCN32, that has a separate
>> rq_dlg_get_dlg_reg), the parameters const bool vm_en, const bool
>> ignore_viewport_pos, and const bool immediate_flip_support are not used
>> on the function. Therefore, change the rq_dlg_get_dlg_reg signature
>> by deleting those parameters.
>>
>> Signed-off-by: Maíra Canal <mairacanal@riseup.net>
>> ---
>> v1 -> v2:
>> - Replace "enum" to "enum entries" (André Almeida).
>> ---
>>   .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  |  3 +--
>>   .../dc/dml/dcn20/display_rq_dlg_calc_20.c     |  5 +----
>>   .../dc/dml/dcn20/display_rq_dlg_calc_20.h     |  5 +----
>>   .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c   |  5 +----
>>   .../dc/dml/dcn20/display_rq_dlg_calc_20v2.h   |  5 +----
>>   .../dc/dml/dcn21/display_rq_dlg_calc_21.c     |  5 +----
>>   .../dc/dml/dcn21/display_rq_dlg_calc_21.h     |  5 +----
>>   .../dc/dml/dcn30/display_rq_dlg_calc_30.c     | 18 +++---------------
>>   .../dc/dml/dcn30/display_rq_dlg_calc_30.h     |  5 +----
>>   .../dc/dml/dcn31/display_rq_dlg_calc_31.c     | 19 +++----------------
>>   .../dc/dml/dcn31/display_rq_dlg_calc_31.h     |  5 +----
>>   .../dc/dml/dcn314/display_rq_dlg_calc_314.c   | 15 ++-------------
>>   .../dc/dml/dcn314/display_rq_dlg_calc_314.h   |  5 +----
>>   .../drm/amd/display/dc/dml/display_mode_lib.h |  5 +----
>>   .../gpu/drm/amd/display/dc/dml/dml_wrapper.c  |  3 +--
>>   15 files changed, 20 insertions(+), 88 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
>> index dc60b835e938..d9cfb29a2651 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
>> @@ -857,8 +857,7 @@ void dcn20_calculate_dlg_params(
>>                   pipe_cnt,
>>                   pipe_idx,
>>                   cstate_en,
>> -                context->bw_ctx.bw.dcn.clk.p_state_change_support,
>> -                false, false, true);
>> +                context->bw_ctx.bw.dcn.clk.p_state_change_support);
>>            
>> context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
>>                   &context->res_ctx.pipe_ctx[i].rq_regs,
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
>> index 548cdef8a8ad..d0a4c69b47c8 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
>> @@ -1553,10 +1553,7 @@ void dml20_rq_dlg_get_dlg_reg(struct
>> display_mode_lib *mode_lib,
>>           const unsigned int num_pipes,
>>           const unsigned int pipe_idx,
>>           const bool cstate_en,
>> -        const bool pstate_en,
>> -        const bool vm_en,
>> -        const bool ignore_viewport_pos,
>> -        const bool immediate_flip_support)
>> +        const bool pstate_en)
>>   {
>>       display_rq_params_st rq_param = {0};
>>       display_dlg_sys_params_st dlg_sys_param = {0};
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
>> index 8b23867e97c1..36c3692e53b8 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
>> @@ -65,9 +65,6 @@ void dml20_rq_dlg_get_dlg_reg(
>>           const unsigned int num_pipes,
>>           const unsigned int pipe_idx,
>>           const bool cstate_en,
>> -        const bool pstate_en,
>> -        const bool vm_en,
>> -        const bool ignore_viewport_pos,
>> -        const bool immediate_flip_support);
>> +        const bool pstate_en);
>>     #endif
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
>> index 0fc9f3e3ffae..17df9d31c11f 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
>> @@ -1554,10 +1554,7 @@ void dml20v2_rq_dlg_get_dlg_reg(struct
>> display_mode_lib *mode_lib,
>>           const unsigned int num_pipes,
>>           const unsigned int pipe_idx,
>>           const bool cstate_en,
>> -        const bool pstate_en,
>> -        const bool vm_en,
>> -        const bool ignore_viewport_pos,
>> -        const bool immediate_flip_support)
>> +        const bool pstate_en)
>>   {
>>       display_rq_params_st rq_param = {0};
>>       display_dlg_sys_params_st dlg_sys_param = {0};
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
>> index 2b4e46ea1c3d..f524f1ccfe41 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
>> @@ -65,9 +65,6 @@ void dml20v2_rq_dlg_get_dlg_reg(
>>           const unsigned int num_pipes,
>>           const unsigned int pipe_idx,
>>           const bool cstate_en,
>> -        const bool pstate_en,
>> -        const bool vm_en,
>> -        const bool ignore_viewport_pos,
>> -        const bool immediate_flip_support);
>> +        const bool pstate_en);
>>     #endif
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
>> index 618f4b682ab1..502dafc6dd79 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
>> @@ -1662,10 +1662,7 @@ void dml21_rq_dlg_get_dlg_reg(
>>           const unsigned int num_pipes,
>>           const unsigned int pipe_idx,
>>           const bool cstate_en,
>> -        const bool pstate_en,
>> -        const bool vm_en,
>> -        const bool ignore_viewport_pos,
>> -        const bool immediate_flip_support)
>> +        const bool pstate_en)
>>   {
>>       display_rq_params_st rq_param = {0};
>>       display_dlg_sys_params_st dlg_sys_param = {0};
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
>> index af6ad0ca9cf8..822c68089ca8 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
>> @@ -65,9 +65,6 @@ void dml21_rq_dlg_get_dlg_reg(
>>           const unsigned int num_pipes,
>>           const unsigned int pipe_idx,
>>           const bool cstate_en,
>> -        const bool pstate_en,
>> -        const bool vm_en,
>> -        const bool ignore_viewport_pos,
>> -        const bool immediate_flip_support);
>> +        const bool pstate_en);
>>     #endif
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
>> index 8179be1f34bb..b3bdb7283a7e 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
>> @@ -898,10 +898,7 @@ static void dml_rq_dlg_get_dlg_params(struct
>> display_mode_lib *mode_lib,
>>       const display_rq_dlg_params_st rq_dlg_param,
>>       const display_dlg_sys_params_st dlg_sys_param,
>>       const bool cstate_en,
>> -    const bool pstate_en,
>> -    const bool vm_en,
>> -    const bool ignore_viewport_pos,
>> -    const bool immediate_flip_support)
>> +    const bool pstate_en)
>>   {
>>       const display_pipe_source_params_st *src =
>> &e2e_pipe_param[pipe_idx].pipe.src;
>>       const display_pipe_dest_params_st *dst =
>> &e2e_pipe_param[pipe_idx].pipe.dest;
>> @@ -1031,9 +1028,6 @@ static void dml_rq_dlg_get_dlg_params(struct
>> display_mode_lib *mode_lib,
>>         dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
>>       dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
>> -    dml_print("DML_DLG: %s:  vm_en     = %d\n", __func__, vm_en);
>> -    dml_print("DML_DLG: %s:  ignore_viewport_pos  = %d\n", __func__,
>> ignore_viewport_pos);
>> -    dml_print("DML_DLG: %s:  immediate_flip_support  = %d\n",
>> __func__, immediate_flip_support);
>>         dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n",
>> __func__, dppclk_freq_in_mhz);
>>       dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n",
>> __func__, dispclk_freq_in_mhz);
>> @@ -1746,10 +1740,7 @@ void dml30_rq_dlg_get_dlg_reg(struct
>> display_mode_lib *mode_lib,
>>       const unsigned int num_pipes,
>>       const unsigned int pipe_idx,
>>       const bool cstate_en,
>> -    const bool pstate_en,
>> -    const bool vm_en,
>> -    const bool ignore_viewport_pos,
>> -    const bool immediate_flip_support)
>> +    const bool pstate_en)
>>   {
>>       display_rq_params_st rq_param = { 0 };
>>       display_dlg_sys_params_st dlg_sys_param = { 0 };
>> @@ -1785,10 +1776,7 @@ void dml30_rq_dlg_get_dlg_reg(struct
>> display_mode_lib *mode_lib,
>>           rq_param.dlg,
>>           dlg_sys_param,
>>           cstate_en,
>> -        pstate_en,
>> -        vm_en,
>> -        ignore_viewport_pos,
>> -        immediate_flip_support);
>> +        pstate_en);
>>       dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
>>   }
>>   diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
>> index 625e41f8d575..d28ed3ae3f94 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
>> @@ -61,9 +61,6 @@ void dml30_rq_dlg_get_dlg_reg(struct
>> display_mode_lib             *mode_lib,
>>           const unsigned int            num_pipes,
>>           const unsigned int            pipe_idx,
>>           const bool                    cstate_en,
>> -        const bool                    pstate_en,
>> -        const bool                    vm_en,
>> -        const bool                    ignore_viewport_pos,
>> -        const bool                    immediate_flip_support);
>> +        const bool                    pstate_en);
>>     #endif
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
>> index 66b82e4f05c6..c36dd3a79871 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
>> @@ -859,10 +859,7 @@ static void dml_rq_dlg_get_dlg_params(
>>           const display_rq_dlg_params_st *rq_dlg_param,
>>           const display_dlg_sys_params_st *dlg_sys_param,
>>           const bool cstate_en,
>> -        const bool pstate_en,
>> -        const bool vm_en,
>> -        const bool ignore_viewport_pos,
>> -        const bool immediate_flip_support)
>> +        const bool pstate_en)
>>   {
>>       const display_pipe_source_params_st *src =
>> &e2e_pipe_param[pipe_idx].pipe.src;
>>       const display_pipe_dest_params_st *dst =
>> &e2e_pipe_param[pipe_idx].pipe.dest;
>> @@ -970,9 +967,6 @@ static void dml_rq_dlg_get_dlg_params(
>>         dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
>>       dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
>> -    dml_print("DML_DLG: %s: vm_en     = %d\n", __func__, vm_en);
>> -    dml_print("DML_DLG: %s: ignore_viewport_pos  = %d\n", __func__,
>> ignore_viewport_pos);
>> -    dml_print("DML_DLG: %s: immediate_flip_support  = %d\n",
>> __func__, immediate_flip_support);
>>         dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n",
>> __func__, dppclk_freq_in_mhz);
>>       dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n",
>> __func__, refclk_freq_in_mhz);
>> @@ -983,7 +977,6 @@ static void dml_rq_dlg_get_dlg_params(
>>       disp_dlg_regs->refcyc_per_htotal = (unsigned int)
>> (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
>>       disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) :
>> vblank_end;    // 15 bits
>>   -    //set_prefetch_mode(mode_lib, cstate_en, pstate_en,
>> ignore_viewport_pos, immediate_flip_support);
>>       min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib,
>> e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
>>         dlg_vblank_start = interlaced ? (vblank_start / 2) :
>> vblank_start;
>> @@ -1576,10 +1569,7 @@ void dml31_rq_dlg_get_dlg_reg(
>>           const unsigned int num_pipes,
>>           const unsigned int pipe_idx,
>>           const bool cstate_en,
>> -        const bool pstate_en,
>> -        const bool vm_en,
>> -        const bool ignore_viewport_pos,
>> -        const bool immediate_flip_support)
>> +        const bool pstate_en)
>>   {
>>       display_rq_params_st rq_param = {0};
>>       display_dlg_sys_params_st dlg_sys_param = {0};
>> @@ -1610,10 +1600,7 @@ void dml31_rq_dlg_get_dlg_reg(
>>               &rq_param.dlg,
>>               &dlg_sys_param,
>>               cstate_en,
>> -            pstate_en,
>> -            vm_en,
>> -            ignore_viewport_pos,
>> -            immediate_flip_support);
>> +            pstate_en);
>>       dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
>>   }
>>   diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
>> index 8ee991351699..5b0b438a9804 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
>> @@ -61,9 +61,6 @@ void dml31_rq_dlg_get_dlg_reg(struct
>> display_mode_lib             *mode_lib,
>>           const unsigned int            num_pipes,
>>           const unsigned int            pipe_idx,
>>           const bool                    cstate_en,
>> -        const bool                    pstate_en,
>> -        const bool                    vm_en,
>> -        const bool                    ignore_viewport_pos,
>> -        const bool                    immediate_flip_support);
>> +        const bool                    pstate_en);
>>     #endif
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
>> index 61ee9ba063a7..37ecc4a6ae11 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
>> @@ -943,11 +943,7 @@ static void dml_rq_dlg_get_dlg_params(
>>           display_ttu_regs_st *disp_ttu_regs,
>>           const display_rq_dlg_params_st *rq_dlg_param,
>>           const display_dlg_sys_params_st *dlg_sys_param,
>> -        const bool cstate_en,
>> -        const bool pstate_en,
>> -        const bool vm_en,
>> -        const bool ignore_viewport_pos,
>> -        const bool immediate_flip_support)
>> +        const bool cstate_en)
>>   {
>>       const display_pipe_source_params_st *src =
>> &e2e_pipe_param[pipe_idx].pipe.src;
>>       const display_pipe_dest_params_st *dst =
>> &e2e_pipe_param[pipe_idx].pipe.dest;
>> @@ -1060,9 +1056,6 @@ static void dml_rq_dlg_get_dlg_params(
>>         dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
>>       dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
> 
> hmmm... I'm not sure if I missed something, but you dropped the variable
> pstate_en from the parameter list, but you still have it here. Is this
> correct?

Yep, I missed that. But I remember have compiled the code and deploying
it. So, I went to check it and examine it I found out that the
dml314_rq_dlg_get_dlg_reg is not even used on the codebase. Which can
indicate one of two things:

1. Should exist a dml314_func struct on the dml/display_mode_lib.c with
this function.

2. The dml/dcn314/display_rq_dlg_calc_314 files should be deleted, as
none of its functions are used on the codebase.

I believe you might know which one is the correct option.

> 
>> -    dml_print("DML_DLG: %s: vm_en     = %d\n", __func__, vm_en);
>> -    dml_print("DML_DLG: %s: ignore_viewport_pos  = %d\n", __func__,
>> ignore_viewport_pos);
>> -    dml_print("DML_DLG: %s: immediate_flip_support  = %d\n",
>> __func__, immediate_flip_support);
> 
> Why are we dropping these logs? It is already hard to debug DML code,
> and reducing the amount of information that we can get does not sound
> good to me.

The parameters vm_en, ignore_viewport_pos, and immediate_flip_support
are hard-coded into code as `false, false, true` on all calls of the
function rq_dlg_get_dlg_reg (there are only two: on cn20/dcn20_fpu.c and
on dml/dml_wrapper.c). As these parameters are already known and don't
change, I don't believe that they add much value to the debug log as the
log will be always the same.

Moreover, I could argue that they are polluting the debug log, as none
of those parameters are being called anywhere else on the codebase. So,
you already know their value from the beginning, and it is the only time
they will ever appear on the log, as they are not considered parameters
anywhere else.

Best Regards,
- Maíra Canal

> 
> Thanks
> Siqueira
> 
>>         dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n",
>> __func__, dppclk_freq_in_mhz);
>>       dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n",
>> __func__, refclk_freq_in_mhz);
>> @@ -1073,7 +1066,6 @@ static void dml_rq_dlg_get_dlg_params(
>>       disp_dlg_regs->refcyc_per_htotal = (unsigned int)
>> (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
>>       disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) :
>> vblank_end;    // 15 bits
>>   -    //set_prefetch_mode(mode_lib, cstate_en, pstate_en,
>> ignore_viewport_pos, immediate_flip_support);
>>       min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib,
>> e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
>>         dlg_vblank_start = interlaced ? (vblank_start / 2) :
>> vblank_start;
>> @@ -1725,9 +1717,6 @@ void dml314_rq_dlg_get_dlg_reg(
>>               &rq_param.dlg,
>>               &dlg_sys_param,
>>               cstate_en,
>> -            pstate_en,
>> -            vm_en,
>> -            ignore_viewport_pos,
>> -            immediate_flip_support);
>> +            pstate_en);
>>       dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
>>   }
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
>> index 49cb85d1056c..d2c1ba8b7ebf 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
>> @@ -62,9 +62,6 @@ void dml314_rq_dlg_get_dlg_reg(struct
>> display_mode_lib             *mode_lib,
>>           const unsigned int            num_pipes,
>>           const unsigned int            pipe_idx,
>>           const bool                    cstate_en,
>> -        const bool                    pstate_en,
>> -        const bool                    vm_en,
>> -        const bool                    ignore_viewport_pos,
>> -        const bool                    immediate_flip_support);
>> +        const bool                    pstate_en);
>>     #endif
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
>> b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
>> index 2bdd6ed22611..8a4b60a278b5 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
>> @@ -55,10 +55,7 @@ struct dml_funcs {
>>               const unsigned int num_pipes,
>>               const unsigned int pipe_idx,
>>               const bool cstate_en,
>> -            const bool pstate_en,
>> -            const bool vm_en,
>> -            const bool ignore_viewport_pos,
>> -            const bool immediate_flip_support);
>> +            const bool pstate_en);
>>       void (*rq_dlg_get_rq_reg)(
>>           struct display_mode_lib *mode_lib,
>>           display_rq_regs_st *rq_regs,
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
>> index b4b51e51fc25..e39e2363ea0a 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
>> @@ -1647,8 +1647,7 @@ static void dml_calculate_dlg_params(
>>                   pipe_cnt,
>>                   pipe_idx,
>>                   cstate_en,
>> -                context->bw_ctx.bw.dcn.clk.p_state_change_support,
>> -                false, false, true);
>> +                context->bw_ctx.bw.dcn.clk.p_state_change_support);
>>            
>> context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
>>                   &context->res_ctx.pipe_ctx[i].rq_regs,
> 

[PATCH v2 4/4] drm/amd/display: Rewrite CalculateWriteBackDISPCLK function

[Maíra Canal]

Based on the dml30_CalculateWriteBackDISPCLK, it separates the
DISPCLK calculations on three variables, making no functional changes, in order
to make it more readable and better express that three values are being compared
on dml_max.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
Reviewed-by: André Almeida <andrealmeid@igalia.com>
---
 .../drm/amd/display/dc/dml/display_mode_vba.c | 29 ++++++++++++-------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 503e7d984ff0..df80c79d8fbc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -1115,20 +1115,27 @@ double CalculateWriteBackDISPCLK(
 		unsigned int HTotal,
 		unsigned int WritebackChromaLineBufferWidth)
 {
-	double CalculateWriteBackDISPCLK = 1.01 * PixelClock * dml_max(
-		dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
-		dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWidth / 4.0, 1)
+	double DISPCLK_H, DISPCLK_V, DISPCLK_HB, CalculateWriteBackDISPCLK;
+
+	DISPCLK_H = dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio;
+	DISPCLK_V = (WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWidth / 4.0, 1)
 			+ dml_ceil(WritebackDestinationWidth / 4.0, 1)) / (double) HTotal + dml_ceil(1.0 / WritebackVRatio, 1)
-			* (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / (double) HTotal,
-			dml_ceil(1.0 / WritebackVRatio, 1) * WritebackDestinationWidth / (double) HTotal));
+			* (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / (double) HTotal;
+	DISPCLK_HB = dml_ceil(1.0 / WritebackVRatio, 1) * WritebackDestinationWidth / (double) HTotal;
+
+	CalculateWriteBackDISPCLK = 1.01 * PixelClock * dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB);
+
 	if (WritebackPixelFormat != dm_444_32) {
-		CalculateWriteBackDISPCLK = dml_max(CalculateWriteBackDISPCLK, 1.01 * PixelClock * dml_max(
-			dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * WritebackHRatio),
-			dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) * dml_ceil(WritebackDestinationWidth / 2.0 / 2.0, 1)
-				+ dml_ceil(WritebackDestinationWidth / 2.0 / WritebackChromaLineBufferWidth, 1)) / HTotal
-				+ dml_ceil(1 / (2 * WritebackVRatio), 1) * (dml_ceil(WritebackChromaVTaps / 4.0, 1) + 4) / HTotal,
-				dml_ceil(1.0 / (2 * WritebackVRatio), 1) * WritebackDestinationWidth / 2.0 / HTotal)));
+		DISPCLK_H = dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * WritebackHRatio);
+		DISPCLK_V = (WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) *
+				dml_ceil(WritebackDestinationWidth / 4.0, 1) +
+				dml_ceil(WritebackDestinationWidth / 2.0 / WritebackChromaLineBufferWidth, 1)) / HTotal +
+			dml_ceil(1 / (2 * WritebackVRatio), 1) *(dml_ceil(WritebackChromaVTaps / 4.0, 1) + 4) / HTotal;
+		DISPCLK_HB = dml_ceil(1.0 / (2 * WritebackVRatio), 1) * WritebackDestinationWidth / 2.0 / HTotal;
+		CalculateWriteBackDISPCLK = dml_max(CalculateWriteBackDISPCLK,
+				1.01 * PixelClock * dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB));
 	}
+
 	return CalculateWriteBackDISPCLK;
 }
 
-- 
2.36.1

Re: [PATCH v2 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl

[André Almeida]

Thank you for the quick revision!

Series is Reviewed-by: André Almeida <andrealmeid@igalia.com>

Às 15:36 de 21/07/22, Maíra Canal escreveu:
> As the enum entries dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp
> are not used on the codebase, drop those entries from enum
> dm_swizzle_mode.
> 
> Signed-off-by: Maíra Canal <mairacanal@riseup.net>
> ---
> v1 -> v2:
> - Replace "enum" to "enum entries" (André Almeida).
> - Describe changes in imperative mood (André Almeida).
> ---
>  .../dc/dml/dcn20/display_mode_vba_20.c        | 26 +++++-------------
>  .../dc/dml/dcn20/display_mode_vba_20v2.c      | 26 +++++-------------
>  .../dc/dml/dcn21/display_mode_vba_21.c        | 27 +++++--------------
>  .../amd/display/dc/dml/display_mode_enums.h   |  2 --
>  .../display/dc/dml/dml_wrapper_translation.c  |  9 -------
>  5 files changed, 19 insertions(+), 71 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index d3b5b6fedf04..4e4cb0927057 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -938,7 +938,7 @@ static unsigned int CalculateVMAndRowBytes(
>  		*MetaRowByte = 0;
>  	}
>  
> -	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> +	if (SurfaceTiling == dm_sw_linear) {
>  		MacroTileSizeBytes = 256;
>  		MacroTileHeight = BlockHeight256Bytes;
>  	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
> @@ -3347,26 +3347,12 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>  										== dm_420_8
>  								|| mode_lib->vba.SourcePixelFormat[k]
>  										== dm_420_10))
> -				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
> -						|| mode_lib->vba.SurfaceTiling[k]
> -								== dm_sw_gfx7_2d_thin_l_vp)
> -						&& !((mode_lib->vba.SourcePixelFormat[k]
> -								== dm_444_64
> +				|| (mode_lib->vba.DCCEnable[k] == true
> +						&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>  								|| mode_lib->vba.SourcePixelFormat[k]
> -										== dm_444_32)
> -								&& mode_lib->vba.SourceScan[k]
> -										== dm_horz
> -								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> -										== true
> -								&& mode_lib->vba.DCCEnable[k]
> -										== false))
> -						|| (mode_lib->vba.DCCEnable[k] == true
> -								&& (mode_lib->vba.SurfaceTiling[k]
> -										== dm_sw_linear
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_8
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_10)))) {
> +										== dm_420_8
> +								|| mode_lib->vba.SourcePixelFormat[k]
> +										== dm_420_10))) {
>  			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> index 63bbdf8b8678..eaa0cdb599ba 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> @@ -998,7 +998,7 @@ static unsigned int CalculateVMAndRowBytes(
>  		*MetaRowByte = 0;
>  	}
>  
> -	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> +	if (SurfaceTiling == dm_sw_linear) {
>  		MacroTileSizeBytes = 256;
>  		MacroTileHeight = BlockHeight256Bytes;
>  	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
> @@ -3454,26 +3454,12 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
>  										== dm_420_8
>  								|| mode_lib->vba.SourcePixelFormat[k]
>  										== dm_420_10))
> -				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
> -						|| mode_lib->vba.SurfaceTiling[k]
> -								== dm_sw_gfx7_2d_thin_l_vp)
> -						&& !((mode_lib->vba.SourcePixelFormat[k]
> -								== dm_444_64
> +				|| (mode_lib->vba.DCCEnable[k] == true
> +						&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>  								|| mode_lib->vba.SourcePixelFormat[k]
> -										== dm_444_32)
> -								&& mode_lib->vba.SourceScan[k]
> -										== dm_horz
> -								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> -										== true
> -								&& mode_lib->vba.DCCEnable[k]
> -										== false))
> -						|| (mode_lib->vba.DCCEnable[k] == true
> -								&& (mode_lib->vba.SurfaceTiling[k]
> -										== dm_sw_linear
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_8
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_10)))) {
> +										== dm_420_8
> +								|| mode_lib->vba.SourcePixelFormat[k]
> +										== dm_420_10))) {
>  			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> index 8a7485e21d53..198d81861ac5 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> @@ -1342,7 +1342,7 @@ static unsigned int CalculateVMAndRowBytes(
>  		*MetaRowByte = 0;
>  	}
>  
> -	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> +	if (SurfaceTiling == dm_sw_linear) {
>  		MacroTileSizeBytes = 256;
>  		MacroTileHeight = BlockHeight256Bytes;
>  	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
> @@ -3579,26 +3579,13 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>  										== dm_420_8
>  								|| mode_lib->vba.SourcePixelFormat[k]
>  										== dm_420_10))
> -				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
> -						|| mode_lib->vba.SurfaceTiling[k]
> -								== dm_sw_gfx7_2d_thin_l_vp)
> -						&& !((mode_lib->vba.SourcePixelFormat[k]
> -								== dm_444_64
> +				|| (mode_lib->vba.DCCEnable[k] == true
> +						&& (mode_lib->vba.SurfaceTiling[k]
> +								== dm_sw_linear
>  								|| mode_lib->vba.SourcePixelFormat[k]
> -										== dm_444_32)
> -								&& mode_lib->vba.SourceScan[k]
> -										== dm_horz
> -								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> -										== true
> -								&& mode_lib->vba.DCCEnable[k]
> -										== false))
> -						|| (mode_lib->vba.DCCEnable[k] == true
> -								&& (mode_lib->vba.SurfaceTiling[k]
> -										== dm_sw_linear
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_8
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_10)))) {
> +										== dm_420_8
> +								|| mode_lib->vba.SourcePixelFormat[k]
> +										== dm_420_10))) {
>  			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> index f394b3f3922a..0e06727d40b3 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> @@ -89,8 +89,6 @@ enum dm_swizzle_mode {
>  	dm_sw_var_s_x = 29,
>  	dm_sw_var_d_x = 30,
>  	dm_sw_var_r_x = 31,
> -	dm_sw_gfx7_2d_thin_l_vp,
> -	dm_sw_gfx7_2d_thin_gl,
>  };
>  enum lb_depth {
>  	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
> index 4ec5310a2962..9edcb6fc83c1 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
> @@ -35,15 +35,6 @@ static void gfx10array_mode_to_dml_params(
>  	case DC_ARRAY_LINEAR_GENERAL:
>  		*sw_mode = dm_sw_linear;
>  		break;
> -	case DC_ARRAY_2D_TILED_THIN1:
> -// DC_LEGACY_TILING_ADDR_GEN_ZERO - undefined as per current code hence removed
> -#if 0
> -		if (compat_level == DC_LEGACY_TILING_ADDR_GEN_ZERO)
> -			*sw_mode = dm_sw_gfx7_2d_thin_l_vp;
> -		else
> -			*sw_mode = dm_sw_gfx7_2d_thin_gl;
> -#endif
> -		break;
>  	default:
>  		ASSERT(0); /* Not supported */
>  		break;