* [PATCH v2 0/1] drm/i915: Use the correct max source link rate for MST @ 2021-04-30 21:45 Nikola Cornij 2021-04-30 21:45 ` [PATCH v2 1/1] " Nikola Cornij 0 siblings, 1 reply; 5+ messages in thread From: Nikola Cornij @ 2021-04-30 21:45 UTC (permalink / raw) To: amd-gfx Cc: intel-gfx, dri-devel, Nikola Cornij, koba.ko, aurabindo.pillai, jani.nikula, mikita.lipski, ville.syrjala, bskeggs This is a follow-up change to fix incorrectly used max link rate source capability at MST init time. Change history: v1: - Initial v2: - Use local variabale for improved code readability - Fix the comment to point to the correct sub-directory Nikola Cornij (1): drm/i915: Use the correct max source link rate for MST drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/1] drm/i915: Use the correct max source link rate for MST 2021-04-30 21:45 [PATCH v2 0/1] drm/i915: Use the correct max source link rate for MST Nikola Cornij @ 2021-04-30 21:45 ` Nikola Cornij 2021-04-30 22:41 ` Lyude Paul 0 siblings, 1 reply; 5+ messages in thread From: Nikola Cornij @ 2021-04-30 21:45 UTC (permalink / raw) To: amd-gfx Cc: intel-gfx, dri-devel, Nikola Cornij, koba.ko, aurabindo.pillai, jani.nikula, mikita.lipski, ville.syrjala, bskeggs [why] Previously used value was not safe to provide the correct value, i.e. it could be 0 if not not configured, leading to no MST on this platform. [how] Do not use the value from BIOS, but from the structure populated at encoder initialization time. Fixes: 98025a62cb00 ("drm/dp_mst: Use Extended Base Receiver Capability DPCD space") Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Lyude Paul <lyude@redhat.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index bf7f8487945c..3642d7578658 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -942,7 +942,7 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) struct intel_dp *intel_dp = &dig_port->dp; enum port port = dig_port->base.port; int ret; - int bios_max_link_rate; + int max_source_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) return 0; @@ -957,11 +957,11 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) /* create encoders */ intel_dp_create_fake_mst_encoders(dig_port); - bios_max_link_rate = intel_bios_dp_max_link_rate(&dig_port->base); ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, &intel_dp->aux, 16, 3, (u8)dig_port->max_lanes, - (u8)(bios_max_link_rate / 27000), conn_base_id); + (u8)(max_source_rate / 27000), + conn_base_id); if (ret) return ret; -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/1] drm/i915: Use the correct max source link rate for MST 2021-04-30 21:45 ` [PATCH v2 1/1] " Nikola Cornij @ 2021-04-30 22:41 ` Lyude Paul 2021-04-30 22:55 ` Cornij, Nikola 0 siblings, 1 reply; 5+ messages in thread From: Lyude Paul @ 2021-04-30 22:41 UTC (permalink / raw) To: Nikola Cornij, amd-gfx Cc: intel-gfx, dri-devel, koba.ko, aurabindo.pillai, jani.nikula, mikita.lipski, ville.syrjala, bskeggs Alright - I had Ville double check this and give their A-B on IRC (I just need to fix the open coded link_rate_to_bw() here). Since this got broken on drm- misc-next I'm going to go ahead and push the fix there, since I'm not going to be around next Monday or Tuesday and I don't want to leave i915 broken in the interim. Sorry about the noise with this Jani! As well - I'll get to fixing the dpcd unit usage once I get back on Wednesday (unless Nikola's already gotten to it by then) so we use KHz instead. Although as ville has pointed out, I think we should teach the topology manager to allow passing for the current link rate/lane count during state computation in the long term. On Fri, 2021-04-30 at 17:45 -0400, Nikola Cornij wrote: > [why] > Previously used value was not safe to provide the correct value, i.e. it > could be 0 if not not configured, leading to no MST on this platform. > > [how] > Do not use the value from BIOS, but from the structure populated at > encoder initialization time. > > Fixes: 98025a62cb00 ("drm/dp_mst: Use Extended Base Receiver Capability DPCD > space") > Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> > Reviewed-by: Lyude Paul <lyude@redhat.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index bf7f8487945c..3642d7578658 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -942,7 +942,7 @@ intel_dp_mst_encoder_init(struct intel_digital_port > *dig_port, int conn_base_id) > struct intel_dp *intel_dp = &dig_port->dp; > enum port port = dig_port->base.port; > int ret; > - int bios_max_link_rate; > + int max_source_rate = intel_dp->source_rates[intel_dp- > >num_source_rates - 1]; > > if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) > return 0; > @@ -957,11 +957,11 @@ intel_dp_mst_encoder_init(struct intel_digital_port > *dig_port, int conn_base_id) > > /* create encoders */ > intel_dp_create_fake_mst_encoders(dig_port); > - bios_max_link_rate = intel_bios_dp_max_link_rate(&dig_port->base); > ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, > &intel_dp->aux, 16, 3, > (u8)dig_port->max_lanes, > - (u8)(bios_max_link_rate / 27000), > conn_base_id); > + (u8)(max_source_rate / 27000), > + conn_base_id); > if (ret) > return ret; > -- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite! _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v2 1/1] drm/i915: Use the correct max source link rate for MST 2021-04-30 22:41 ` Lyude Paul @ 2021-04-30 22:55 ` Cornij, Nikola 2021-05-03 8:44 ` Jani Nikula 0 siblings, 1 reply; 5+ messages in thread From: Cornij, Nikola @ 2021-04-30 22:55 UTC (permalink / raw) To: lyude, amd-gfx Cc: intel-gfx, dri-devel, koba.ko, Pillai, Aurabindo, jani.nikula, Lipski, Mikita, ville.syrjala, bskeggs [AMD Official Use Only - Internal Distribution Only] I'll fix the dpcd part to use kHz on Monday My apologies as well, not only for coming up with the wrong patch in first place, but also for missing to CC all the maintainers. -----Original Message----- From: Lyude Paul <lyude@redhat.com> Sent: Friday, April 30, 2021 6:41 PM To: Cornij, Nikola <Nikola.Cornij@amd.com>; amd-gfx@lists.freedesktop.org Cc: Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lipski, Mikita <Mikita.Lipski@amd.com>; ville.syrjala@linux.intel.com; koba.ko@canonical.com; intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; jani.nikula@linux.intel.com; bskeggs@redhat.com Subject: Re: [PATCH v2 1/1] drm/i915: Use the correct max source link rate for MST Alright - I had Ville double check this and give their A-B on IRC (I just need to fix the open coded link_rate_to_bw() here). Since this got broken on drm- misc-next I'm going to go ahead and push the fix there, since I'm not going to be around next Monday or Tuesday and I don't want to leave i915 broken in the interim. Sorry about the noise with this Jani! As well - I'll get to fixing the dpcd unit usage once I get back on Wednesday (unless Nikola's already gotten to it by then) so we use KHz instead. Although as ville has pointed out, I think we should teach the topology manager to allow passing for the current link rate/lane count during state computation in the long term. On Fri, 2021-04-30 at 17:45 -0400, Nikola Cornij wrote: > [why] > Previously used value was not safe to provide the correct value, i.e. > it could be 0 if not not configured, leading to no MST on this platform. > > [how] > Do not use the value from BIOS, but from the structure populated at > encoder initialization time. > > Fixes: 98025a62cb00 ("drm/dp_mst: Use Extended Base Receiver > Capability DPCD > space") > Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> > Reviewed-by: Lyude Paul <lyude@redhat.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index bf7f8487945c..3642d7578658 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -942,7 +942,7 @@ intel_dp_mst_encoder_init(struct > intel_digital_port *dig_port, int conn_base_id) > struct intel_dp *intel_dp = &dig_port->dp; > enum port port = dig_port->base.port; > int ret; > - int bios_max_link_rate; > + int max_source_rate = intel_dp->source_rates[intel_dp- > >num_source_rates - 1]; > > if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) > return 0; > @@ -957,11 +957,11 @@ intel_dp_mst_encoder_init(struct > intel_digital_port *dig_port, int conn_base_id) > > /* create encoders */ > intel_dp_create_fake_mst_encoders(dig_port); > - bios_max_link_rate = > intel_bios_dp_max_link_rate(&dig_port->base); > ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, > &i915->drm, > &intel_dp->aux, 16, 3, > (u8)dig_port->max_lanes, > - (u8)(bios_max_link_rate / > 27000), conn_base_id); > + (u8)(max_source_rate / > +27000), > + conn_base_id); > if (ret) > return ret; > -- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite! _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v2 1/1] drm/i915: Use the correct max source link rate for MST 2021-04-30 22:55 ` Cornij, Nikola @ 2021-05-03 8:44 ` Jani Nikula 0 siblings, 0 replies; 5+ messages in thread From: Jani Nikula @ 2021-05-03 8:44 UTC (permalink / raw) To: Cornij, Nikola, lyude, amd-gfx Cc: intel-gfx, dri-devel, koba.ko, Pillai, Aurabindo, bskeggs, Lipski, Mikita, ville.syrjala On Fri, 30 Apr 2021, "Cornij, Nikola" <Nikola.Cornij@amd.com> wrote: > I'll fix the dpcd part to use kHz on Monday I'd appreciate that, thanks. I think it is the better interface. > My apologies as well, not only for coming up with the wrong patch in > first place, but also for missing to CC all the maintainers. The drivers we have are monsters, and it can be tricky to get the details right. All the more important to get the Cc's right; then at least you can blame us afterwards. ;) Thanks for reacting quickly, though. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-05-03 8:44 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-04-30 21:45 [PATCH v2 0/1] drm/i915: Use the correct max source link rate for MST Nikola Cornij 2021-04-30 21:45 ` [PATCH v2 1/1] " Nikola Cornij 2021-04-30 22:41 ` Lyude Paul 2021-04-30 22:55 ` Cornij, Nikola 2021-05-03 8:44 ` Jani Nikula
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).