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* [PATCH] Revert "drm/amdgpu: support access regs outside of mmio bar"
@ 2020-06-30  8:55 Hawking Zhang
  2020-06-30  9:07 ` Christian König
  0 siblings, 1 reply; 2+ messages in thread
From: Hawking Zhang @ 2020-06-30  8:55 UTC (permalink / raw)
  To: amd-gfx; +Cc: Hawking Zhang

This reverts commit e318290d4845026623924a42435eafd101f669ac.
Fallback to a stable base until we have a correct new one

Signed-off-by:Hawking Zhang <Hawking.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 19 ++++++-------
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 +++++++++++++++++++-----------
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  |  4 +--
 3 files changed, 39 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 110234d..80f32b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1013,10 +1013,10 @@ int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
 
 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
 			       uint32_t *buf, size_t size, bool write);
-uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
-			    uint32_t acc_flags);
-void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 			uint32_t acc_flags);
+void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+		    uint32_t acc_flags);
 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 		    uint32_t acc_flags);
 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
@@ -1035,8 +1035,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
  */
 #define AMDGPU_REGS_NO_KIQ    (1<<1)
 
-#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
-#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
+#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
+#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
 
 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
@@ -1044,9 +1044,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
 
-#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
-#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
-#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
+#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
+#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
+#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
@@ -1084,7 +1084,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 		WREG32_PLL(reg, tmp_);				\
 	} while (0)
 
-
 #define WREG32_SMC_P(_Reg, _Val, _Mask)                         \
 	do {                                                    \
 		u32 tmp = RREG32_SMC(_Reg);                     \
@@ -1093,7 +1092,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 		WREG32_SMC(_Reg, tmp);                          \
 	} while (0)
 
-#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
+#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7a4e965..7a61085 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -301,10 +301,10 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
 }
 
 /*
- * device register access helper functions.
+ * MMIO register access helper functions.
  */
 /**
- * amdgpu_device_rreg - read a register
+ * amdgpu_mm_rreg - read a memory mapped IO register
  *
  * @adev: amdgpu_device pointer
  * @reg: dword aligned register offset
@@ -312,8 +312,8 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
  *
  * Returns the 32 bit value from the offset specified.
  */
-uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
-			    uint32_t acc_flags)
+uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
+			uint32_t acc_flags)
 {
 	uint32_t ret;
 
@@ -322,9 +322,15 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
 
 	if ((reg * 4) < adev->rmmio_size)
 		ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
-	else
-		ret = adev->pcie_rreg(adev, (reg * 4));
-	trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
+	else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
+		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
+		ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
+		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
+	}
+	trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 	return ret;
 }
 
@@ -370,19 +376,24 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
 		BUG();
 }
 
-void static inline amdgpu_device_wreg_no_kiq(struct amdgpu_device *adev, uint32_t reg,
-					     uint32_t v, uint32_t acc_flags)
+void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t acc_flags)
 {
-	trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
+	trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 
 	if ((reg * 4) < adev->rmmio_size)
 		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
-	else
-		adev->pcie_wreg(adev, (reg * 4), v);
+	else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
+		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
+		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
+		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
+	}
 }
 
 /**
- * amdgpu_device_wreg - write to a register
+ * amdgpu_mm_wreg - write to a memory mapped IO register
  *
  * @adev: amdgpu_device pointer
  * @reg: dword aligned register offset
@@ -391,13 +402,13 @@ void static inline amdgpu_device_wreg_no_kiq(struct amdgpu_device *adev, uint32_
  *
  * Writes the value specified to the offset specified.
  */
-void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
-			uint32_t acc_flags)
+void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+		    uint32_t acc_flags)
 {
 	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 		return amdgpu_kiq_wreg(adev, reg, v);
 
-	amdgpu_device_wreg_no_kiq(adev, reg, v, acc_flags);
+	amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);
 }
 
 /*
@@ -416,7 +427,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t
 			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
 	}
 
-	amdgpu_device_wreg_no_kiq(adev, reg, v, acc_flags);
+	amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 5da20fc..63e734a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -35,7 +35,7 @@
 #define AMDGPU_JOB_GET_TIMELINE_NAME(job) \
 	 job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished)
 
-TRACE_EVENT(amdgpu_device_rreg,
+TRACE_EVENT(amdgpu_mm_rreg,
 	    TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
 	    TP_ARGS(did, reg, value),
 	    TP_STRUCT__entry(
@@ -54,7 +54,7 @@ TRACE_EVENT(amdgpu_device_rreg,
 		      (unsigned long)__entry->value)
 );
 
-TRACE_EVENT(amdgpu_device_wreg,
+TRACE_EVENT(amdgpu_mm_wreg,
 	    TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
 	    TP_ARGS(did, reg, value),
 	    TP_STRUCT__entry(
-- 
2.7.4

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^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] Revert "drm/amdgpu: support access regs outside of mmio bar"
  2020-06-30  8:55 [PATCH] Revert "drm/amdgpu: support access regs outside of mmio bar" Hawking Zhang
@ 2020-06-30  9:07 ` Christian König
  0 siblings, 0 replies; 2+ messages in thread
From: Christian König @ 2020-06-30  9:07 UTC (permalink / raw)
  To: Hawking Zhang, amd-gfx

Am 30.06.20 um 10:55 schrieb Hawking Zhang:
> This reverts commit e318290d4845026623924a42435eafd101f669ac.
> Fallback to a stable base until we have a correct new one
>
> Signed-off-by:Hawking Zhang <Hawking.Zhang@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 19 ++++++-------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 +++++++++++++++++++-----------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  |  4 +--
>   3 files changed, 39 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 110234d..80f32b3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1013,10 +1013,10 @@ int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
>   
>   void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
>   			       uint32_t *buf, size_t size, bool write);
> -uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
> -			    uint32_t acc_flags);
> -void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
> +uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
>   			uint32_t acc_flags);
> +void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
> +		    uint32_t acc_flags);
>   void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
>   		    uint32_t acc_flags);
>   void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
> @@ -1035,8 +1035,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
>    */
>   #define AMDGPU_REGS_NO_KIQ    (1<<1)
>   
> -#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
> -#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
> +#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
> +#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
>   
>   #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
>   #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
> @@ -1044,9 +1044,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
>   #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
>   #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
>   
> -#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
> -#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
> -#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
> +#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
> +#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
> +#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
>   #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
>   #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
>   #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
> @@ -1084,7 +1084,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
>   		WREG32_PLL(reg, tmp_);				\
>   	} while (0)
>   
> -
>   #define WREG32_SMC_P(_Reg, _Val, _Mask)                         \
>   	do {                                                    \
>   		u32 tmp = RREG32_SMC(_Reg);                     \
> @@ -1093,7 +1092,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
>   		WREG32_SMC(_Reg, tmp);                          \
>   	} while (0)
>   
> -#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
> +#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
>   #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
>   #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7a4e965..7a61085 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -301,10 +301,10 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
>   }
>   
>   /*
> - * device register access helper functions.
> + * MMIO register access helper functions.
>    */
>   /**
> - * amdgpu_device_rreg - read a register
> + * amdgpu_mm_rreg - read a memory mapped IO register
>    *
>    * @adev: amdgpu_device pointer
>    * @reg: dword aligned register offset
> @@ -312,8 +312,8 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
>    *
>    * Returns the 32 bit value from the offset specified.
>    */
> -uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
> -			    uint32_t acc_flags)
> +uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> +			uint32_t acc_flags)
>   {
>   	uint32_t ret;
>   
> @@ -322,9 +322,15 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
>   
>   	if ((reg * 4) < adev->rmmio_size)
>   		ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
> -	else
> -		ret = adev->pcie_rreg(adev, (reg * 4));
> -	trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
> +	else {
> +		unsigned long flags;
> +
> +		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
> +		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
> +		ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
> +		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
> +	}
> +	trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
>   	return ret;
>   }
>   
> @@ -370,19 +376,24 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
>   		BUG();
>   }
>   
> -void static inline amdgpu_device_wreg_no_kiq(struct amdgpu_device *adev, uint32_t reg,
> -					     uint32_t v, uint32_t acc_flags)
> +void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t acc_flags)
>   {
> -	trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
> +	trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
>   
>   	if ((reg * 4) < adev->rmmio_size)
>   		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> -	else
> -		adev->pcie_wreg(adev, (reg * 4), v);
> +	else {
> +		unsigned long flags;
> +
> +		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
> +		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
> +		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
> +		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
> +	}
>   }
>   
>   /**
> - * amdgpu_device_wreg - write to a register
> + * amdgpu_mm_wreg - write to a memory mapped IO register
>    *
>    * @adev: amdgpu_device pointer
>    * @reg: dword aligned register offset
> @@ -391,13 +402,13 @@ void static inline amdgpu_device_wreg_no_kiq(struct amdgpu_device *adev, uint32_
>    *
>    * Writes the value specified to the offset specified.
>    */
> -void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
> -			uint32_t acc_flags)
> +void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
> +		    uint32_t acc_flags)
>   {
>   	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
>   		return amdgpu_kiq_wreg(adev, reg, v);
>   
> -	amdgpu_device_wreg_no_kiq(adev, reg, v, acc_flags);
> +	amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);
>   }
>   
>   /*
> @@ -416,7 +427,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t
>   			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
>   	}
>   
> -	amdgpu_device_wreg_no_kiq(adev, reg, v, acc_flags);
> +	amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);
>   }
>   
>   /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> index 5da20fc..63e734a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> @@ -35,7 +35,7 @@
>   #define AMDGPU_JOB_GET_TIMELINE_NAME(job) \
>   	 job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished)
>   
> -TRACE_EVENT(amdgpu_device_rreg,
> +TRACE_EVENT(amdgpu_mm_rreg,
>   	    TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
>   	    TP_ARGS(did, reg, value),
>   	    TP_STRUCT__entry(
> @@ -54,7 +54,7 @@ TRACE_EVENT(amdgpu_device_rreg,
>   		      (unsigned long)__entry->value)
>   );
>   
> -TRACE_EVENT(amdgpu_device_wreg,
> +TRACE_EVENT(amdgpu_mm_wreg,
>   	    TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
>   	    TP_ARGS(did, reg, value),
>   	    TP_STRUCT__entry(

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2020-06-30  8:55 [PATCH] Revert "drm/amdgpu: support access regs outside of mmio bar" Hawking Zhang
2020-06-30  9:07 ` Christian König

AMD-GFX Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/amd-gfx/0 amd-gfx/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 amd-gfx amd-gfx/ https://lore.kernel.org/amd-gfx \
		amd-gfx@lists.freedesktop.org
	public-inbox-index amd-gfx

Example config snippet for mirrors

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	nntp://nntp.lore.kernel.org/org.freedesktop.lists.amd-gfx


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git