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* [PATCH Review 1/1] drm/amdgpu: force enable gfx ras for vega20 ws
@ 2021-04-30  6:52 Stanley.Yang
  2021-04-30  8:08 ` Xu, Feifei
  2021-04-30 10:22 ` Zhang, Hawking
  0 siblings, 2 replies; 3+ messages in thread
From: Stanley.Yang @ 2021-04-30  6:52 UTC (permalink / raw)
  To: amd-gfx, Hawking.Zhang; +Cc: Stanley.Yang

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index daf63a4c1fff..dfeaa57dd7ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -34,6 +34,7 @@
 #include "amdgpu_xgmi.h"
 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
 #include <asm/mce.h>
+#include "atom.h"
 
 static const char *RAS_FS_NAME = "ras";
 
@@ -2070,6 +2071,25 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
 		adev->asic_type == CHIP_SIENNA_CICHLID;
 }
 
+/*
+ * this is workaround for vega20 workstation sku,
+ * force enable gfx ras, ignore vbios gfx ras flag
+ * due to GC EDC can not write
+ */
+static void amdgpu_ras_get_quirks(struct amdgpu_device *adev,
+		uint32_t *hw_supported)
+{
+	struct atom_context *ctx = adev->mode_info.atom_context;
+
+	if (!ctx)
+		return;
+
+	if (adev->asic_type == CHIP_VEGA20 &&
+			strnstr(ctx->vbios_version, "D16406",
+					sizeof(ctx->vbios_version)))
+			*hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX);
+}
+
 /*
  * check hardware's ras ability which will be saved in hw_supported.
  * if hardware does not support ras, we can skip some ras initializtion and
@@ -2112,6 +2132,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
 				1 << AMDGPU_RAS_BLOCK__MMHUB);
 	}
 
+	amdgpu_ras_get_quirks(adev, hw_supported);
+
 	/* hw_supported needs to be aligned with RAS block mask. */
 	*hw_supported &= AMDGPU_RAS_BLOCK_MASK;
 
-- 
2.17.1

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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* RE: [PATCH Review 1/1] drm/amdgpu: force enable gfx ras for vega20 ws
  2021-04-30  6:52 [PATCH Review 1/1] drm/amdgpu: force enable gfx ras for vega20 ws Stanley.Yang
@ 2021-04-30  8:08 ` Xu, Feifei
  2021-04-30 10:22 ` Zhang, Hawking
  1 sibling, 0 replies; 3+ messages in thread
From: Xu, Feifei @ 2021-04-30  8:08 UTC (permalink / raw)
  To: Yang, Stanley, amd-gfx, Zhang, Hawking; +Cc: Yang, Stanley

[AMD Official Use Only - Internal Distribution Only]

Maybe the title can be more specific like:
drm/amdgpu: force enable gfx ras in hw_support for vega20 ws

With above modified.

Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Stanley.Yang
Sent: Friday, April 30, 2021 2:52 PM
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking <Hawking.Zhang@amd.com>
Cc: Yang, Stanley <Stanley.Yang@amd.com>
Subject: [PATCH Review 1/1] drm/amdgpu: force enable gfx ras for vega20 ws

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index daf63a4c1fff..dfeaa57dd7ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -34,6 +34,7 @@
 #include "amdgpu_xgmi.h"
 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
 #include <asm/mce.h>
+#include "atom.h"

 static const char *RAS_FS_NAME = "ras";

@@ -2070,6 +2071,25 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
 adev->asic_type == CHIP_SIENNA_CICHLID;  }

+/*
+ * this is workaround for vega20 workstation sku,
+ * force enable gfx ras, ignore vbios gfx ras flag
+ * due to GC EDC can not write
+ */
+static void amdgpu_ras_get_quirks(struct amdgpu_device *adev,
+uint32_t *hw_supported)
+{
+struct atom_context *ctx = adev->mode_info.atom_context;
+
+if (!ctx)
+return;
+
+if (adev->asic_type == CHIP_VEGA20 &&
+strnstr(ctx->vbios_version, "D16406",
+sizeof(ctx->vbios_version)))
+*hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX); }
+
 /*
  * check hardware's ras ability which will be saved in hw_supported.
  * if hardware does not support ras, we can skip some ras initializtion and @@ -2112,6 +2132,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
 1 << AMDGPU_RAS_BLOCK__MMHUB);
 }

+amdgpu_ras_get_quirks(adev, hw_supported);
+
 /* hw_supported needs to be aligned with RAS block mask. */
 *hw_supported &= AMDGPU_RAS_BLOCK_MASK;

--
2.17.1

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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* RE: [PATCH Review 1/1] drm/amdgpu: force enable gfx ras for vega20 ws
  2021-04-30  6:52 [PATCH Review 1/1] drm/amdgpu: force enable gfx ras for vega20 ws Stanley.Yang
  2021-04-30  8:08 ` Xu, Feifei
@ 2021-04-30 10:22 ` Zhang, Hawking
  1 sibling, 0 replies; 3+ messages in thread
From: Zhang, Hawking @ 2021-04-30 10:22 UTC (permalink / raw)
  To: Yang, Stanley, amd-gfx; +Cc: Yang, Stanley

[AMD Public Use]

Please remove the redundant aisc type check: adev->asic_type == CHIP_VEGA20. The board ID should be good enough for this case.

Other than that, the patch is

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking

-----Original Message-----
From: Stanley.Yang <Stanley.Yang@amd.com> 
Sent: Friday, April 30, 2021 14:52
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking <Hawking.Zhang@amd.com>
Cc: Yang, Stanley <Stanley.Yang@amd.com>
Subject: [PATCH Review 1/1] drm/amdgpu: force enable gfx ras for vega20 ws

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index daf63a4c1fff..dfeaa57dd7ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -34,6 +34,7 @@
 #include "amdgpu_xgmi.h"
 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
 #include <asm/mce.h>
+#include "atom.h"
 
 static const char *RAS_FS_NAME = "ras";
 
@@ -2070,6 +2071,25 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
 		adev->asic_type == CHIP_SIENNA_CICHLID;  }
 
+/*
+ * this is workaround for vega20 workstation sku,
+ * force enable gfx ras, ignore vbios gfx ras flag
+ * due to GC EDC can not write
+ */
+static void amdgpu_ras_get_quirks(struct amdgpu_device *adev,
+		uint32_t *hw_supported)
+{
+	struct atom_context *ctx = adev->mode_info.atom_context;
+
+	if (!ctx)
+		return;
+
+	if (adev->asic_type == CHIP_VEGA20 &&
+			strnstr(ctx->vbios_version, "D16406",
+					sizeof(ctx->vbios_version)))
+			*hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX); }
+
 /*
  * check hardware's ras ability which will be saved in hw_supported.
  * if hardware does not support ras, we can skip some ras initializtion and @@ -2112,6 +2132,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
 				1 << AMDGPU_RAS_BLOCK__MMHUB);
 	}
 
+	amdgpu_ras_get_quirks(adev, hw_supported);
+
 	/* hw_supported needs to be aligned with RAS block mask. */
 	*hw_supported &= AMDGPU_RAS_BLOCK_MASK;
 
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-04-30 10:22 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2021-04-30  8:08 ` Xu, Feifei
2021-04-30 10:22 ` Zhang, Hawking

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