amd-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
* [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
@ 2020-09-17  9:42 Jingwen Chen
  2020-09-18  2:38 ` Deng, Emily
  0 siblings, 1 reply; 8+ messages in thread
From: Jingwen Chen @ 2020-09-17  9:42 UTC (permalink / raw)
  To: amd-gfx; +Cc: Jingwen Chen

smu_post_init needs to enable SMU feature, while this require
virtualization off. Skip it since this feature is not used in SRIOV.

v2: move the check to the early stage of smu_post_init.

v3: fix typo

Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index a027c7fdad56..05cb1fdd15ce 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2631,6 +2631,9 @@ static int navi10_post_smu_init(struct smu_context *smu)
 	uint64_t feature_mask = 0;
 	int ret = 0;
 
+	if (amdgpu_sriov_vf(adev))
+		return 0;
+
 	/* For Naiv1x, enable these features only after DAL initialization */
 	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 		feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
-- 
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* RE: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
  2020-09-17  9:42 [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV Jingwen Chen
@ 2020-09-18  2:38 ` Deng, Emily
  0 siblings, 0 replies; 8+ messages in thread
From: Deng, Emily @ 2020-09-18  2:38 UTC (permalink / raw)
  To: Chen, JingWen, amd-gfx; +Cc: Chen, JingWen

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Emily.Deng <Emily.Deng@amd.com>

>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
>Jingwen Chen
>Sent: Thursday, September 17, 2020 5:43 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Chen, JingWen <JingWen.Chen2@amd.com>
>Subject: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
>
>smu_post_init needs to enable SMU feature, while this require virtualization
>off. Skip it since this feature is not used in SRIOV.
>
>v2: move the check to the early stage of smu_post_init.
>
>v3: fix typo
>
>Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
>---
> drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>index a027c7fdad56..05cb1fdd15ce 100644
>--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>@@ -2631,6 +2631,9 @@ static int navi10_post_smu_init(struct smu_context
>*smu)
> uint64_t feature_mask = 0;
> int ret = 0;
>
>+if (amdgpu_sriov_vf(adev))
>+return 0;
>+
> /* For Naiv1x, enable these features only after DAL initialization */
> if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
>--
>2.25.1
>
>_______________________________________________
>amd-gfx mailing list
>amd-gfx@lists.freedesktop.org
>https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.fre
>edesktop.org%2Fmailman%2Flistinfo%2Famd-
>gfx&amp;data=02%7C01%7CEmily.Deng%40amd.com%7Ca1fbb64ca45945c3f3
>e008d85aee24df%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
>37359326168883628&amp;sdata=Ix4oI%2FxGMb3vUimmLO%2Bix%2Bgqp9OY
>O0WfTOlZvieZj3Y%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 8+ messages in thread
* RE: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
  2020-09-17  9:39 ` Chen, Guchun
@ 2020-09-17  9:44   ` Chen, JingWen
  0 siblings, 0 replies; 8+ messages in thread
From: Chen, JingWen @ 2020-09-17  9:44 UTC (permalink / raw)
  To: Chen, Guchun, amd-gfx

[AMD Public Use]

Typo fixed in v3

Best Regards,
JingWen Chen

> -----Original Message-----
> From: Chen, Guchun <Guchun.Chen@amd.com>
> Sent: Thursday, September 17, 2020 5:40 PM
> To: Chen, JingWen <JingWen.Chen2@amd.com>; amd-
> gfx@lists.freedesktop.org
> Cc: Chen, JingWen <JingWen.Chen2@amd.com>
> Subject: RE: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
> 
> [AMD Public Use]
> 
> You want to call it in SRIOV case or in bare-metal case?
> 
> Regards,
> Guchun
> 
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Jingwen Chen
> Sent: Thursday, September 17, 2020 5:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Chen, JingWen <JingWen.Chen2@amd.com>
> Subject: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
> 
> smu_post_init needs to enable SMU feature, while this require virtualization
> off. Skip it since this feature is not used in SRIOV.
> 
> v2: move the check to the early stage of smu_post_init.
> 
> Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index a027c7fdad56..a950f009c794 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -2631,6 +2631,9 @@ static int navi10_post_smu_init(struct smu_context
> *smu)
>  	uint64_t feature_mask = 0;
>  	int ret = 0;
> 
> +	if (!amdgpu_sriov_vf(adev))
> +		return 0;
> +
>  	/* For Naiv1x, enable these features only after DAL initialization */
>  	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
>  		feature_mask |=
> FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> --
> 2.25.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&amp;data=02%7C01%7Cguchun.chen%40amd.com%7C12ec63de0caa413
> 4415008d85aea7b6a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C
> 637359310721844702&amp;sdata=9JCzyhqPIKMZV%2BBEL83HZyfwCyZjTP5iP
> gs7Hn4Epx8%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 8+ messages in thread
* RE: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
  2020-09-17  9:16 Jingwen Chen
@ 2020-09-17  9:39 ` Chen, Guchun
  2020-09-17  9:44   ` Chen, JingWen
  0 siblings, 1 reply; 8+ messages in thread
From: Chen, Guchun @ 2020-09-17  9:39 UTC (permalink / raw)
  To: Chen, JingWen, amd-gfx; +Cc: Chen, JingWen

[AMD Public Use]

You want to call it in SRIOV case or in bare-metal case?

Regards,
Guchun

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Jingwen Chen
Sent: Thursday, September 17, 2020 5:17 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, JingWen <JingWen.Chen2@amd.com>
Subject: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV

smu_post_init needs to enable SMU feature, while this require virtualization off. Skip it since this feature is not used in SRIOV.

v2: move the check to the early stage of smu_post_init.

Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index a027c7fdad56..a950f009c794 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2631,6 +2631,9 @@ static int navi10_post_smu_init(struct smu_context *smu)
 	uint64_t feature_mask = 0;
 	int ret = 0;
 
+	if (!amdgpu_sriov_vf(adev))
+		return 0;
+
 	/* For Naiv1x, enable these features only after DAL initialization */
 	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 		feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
--
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cguchun.chen%40amd.com%7C12ec63de0caa4134415008d85aea7b6a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637359310721844702&amp;sdata=9JCzyhqPIKMZV%2BBEL83HZyfwCyZjTP5iPgs7Hn4Epx8%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* RE: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
  2020-09-17  8:21 ` Chen, Guchun
@ 2020-09-17  9:17   ` Chen, JingWen
  0 siblings, 0 replies; 8+ messages in thread
From: Chen, JingWen @ 2020-09-17  9:17 UTC (permalink / raw)
  To: Chen, Guchun, amd-gfx

[AMD Public Use]

Done in v2

Best Regards,
JingWen Chen

> -----Original Message-----
> From: Chen, Guchun <Guchun.Chen@amd.com>
> Sent: Thursday, September 17, 2020 4:21 PM
> To: Chen, JingWen <JingWen.Chen2@amd.com>; amd-
> gfx@lists.freedesktop.org
> Cc: Chen, JingWen <JingWen.Chen2@amd.com>
> Subject: RE: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
> 
> [AMD Public Use]
> 
> Why not moving the check in smu_post_init, and return 0 at the first early
> stage if it's SRIOV case?
> 
> Regards,
> Guchun
> 
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Jingwen Chen
> Sent: Thursday, September 17, 2020 4:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Chen, JingWen <JingWen.Chen2@amd.com>
> Subject: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
> 
> smu_post_init needs to enable SMU feature, while this require virtualization
> off. Skip it since this feature is not used in SRIOV.
> 
> Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
> ---
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 5c4b74f964fc..79163d0ff762 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -469,10 +469,12 @@ static int smu_late_init(void *handle)
>  	if (!smu->pm_enabled)
>  		return 0;
> 
> -	ret = smu_post_init(smu);
> -	if (ret) {
> -		dev_err(adev->dev, "Failed to post smu init!\n");
> -		return ret;
> +	if (!amdgpu_sriov_vf(adev)) {
> +		ret = smu_post_init(smu);
> +		if (ret) {
> +			dev_err(adev->dev, "Failed to post smu init!\n");
> +			return ret;
> +		}
>  	}
> 
>  	ret = smu_set_default_od_settings(smu);
> --
> 2.25.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&amp;data=02%7C01%7Cguchun.chen%40amd.com%7C7bc132d80cd34c4
> e7b8f08d85ae1fcc5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C
> 637359274256715319&amp;sdata=x%2Bc0jbDbTv8PR7qj4GCbYgxorKyFg2K%2
> BJYgcrs4iftE%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
@ 2020-09-17  9:16 Jingwen Chen
  2020-09-17  9:39 ` Chen, Guchun
  0 siblings, 1 reply; 8+ messages in thread
From: Jingwen Chen @ 2020-09-17  9:16 UTC (permalink / raw)
  To: amd-gfx; +Cc: Jingwen Chen

smu_post_init needs to enable SMU feature, while this require
virtualization off. Skip it since this feature is not used in SRIOV.

v2: move the check to the early stage of smu_post_init.

Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index a027c7fdad56..a950f009c794 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2631,6 +2631,9 @@ static int navi10_post_smu_init(struct smu_context *smu)
 	uint64_t feature_mask = 0;
 	int ret = 0;
 
+	if (!amdgpu_sriov_vf(adev))
+		return 0;
+
 	/* For Naiv1x, enable these features only after DAL initialization */
 	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 		feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
-- 
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* RE: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
  2020-09-17  8:10 Jingwen Chen
@ 2020-09-17  8:21 ` Chen, Guchun
  2020-09-17  9:17   ` Chen, JingWen
  0 siblings, 1 reply; 8+ messages in thread
From: Chen, Guchun @ 2020-09-17  8:21 UTC (permalink / raw)
  To: Chen, JingWen, amd-gfx; +Cc: Chen, JingWen

[AMD Public Use]

Why not moving the check in smu_post_init, and return 0 at the first early stage if it's SRIOV case?

Regards,
Guchun

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Jingwen Chen
Sent: Thursday, September 17, 2020 4:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, JingWen <JingWen.Chen2@amd.com>
Subject: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV

smu_post_init needs to enable SMU feature, while this require virtualization off. Skip it since this feature is not used in SRIOV.

Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 5c4b74f964fc..79163d0ff762 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -469,10 +469,12 @@ static int smu_late_init(void *handle)
 	if (!smu->pm_enabled)
 		return 0;
 
-	ret = smu_post_init(smu);
-	if (ret) {
-		dev_err(adev->dev, "Failed to post smu init!\n");
-		return ret;
+	if (!amdgpu_sriov_vf(adev)) {
+		ret = smu_post_init(smu);
+		if (ret) {
+			dev_err(adev->dev, "Failed to post smu init!\n");
+			return ret;
+		}
 	}
 
 	ret = smu_set_default_od_settings(smu);
--
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cguchun.chen%40amd.com%7C7bc132d80cd34c4e7b8f08d85ae1fcc5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637359274256715319&amp;sdata=x%2Bc0jbDbTv8PR7qj4GCbYgxorKyFg2K%2BJYgcrs4iftE%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV
@ 2020-09-17  8:10 Jingwen Chen
  2020-09-17  8:21 ` Chen, Guchun
  0 siblings, 1 reply; 8+ messages in thread
From: Jingwen Chen @ 2020-09-17  8:10 UTC (permalink / raw)
  To: amd-gfx; +Cc: Jingwen Chen

smu_post_init needs to enable SMU feature, while this require
virtualization off. Skip it since this feature is not used in SRIOV.

Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 5c4b74f964fc..79163d0ff762 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -469,10 +469,12 @@ static int smu_late_init(void *handle)
 	if (!smu->pm_enabled)
 		return 0;
 
-	ret = smu_post_init(smu);
-	if (ret) {
-		dev_err(adev->dev, "Failed to post smu init!\n");
-		return ret;
+	if (!amdgpu_sriov_vf(adev)) {
+		ret = smu_post_init(smu);
+		if (ret) {
+			dev_err(adev->dev, "Failed to post smu init!\n");
+			return ret;
+		}
 	}
 
 	ret = smu_set_default_od_settings(smu);
-- 
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-09-18  2:38 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-17  9:42 [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV Jingwen Chen
2020-09-18  2:38 ` Deng, Emily
  -- strict thread matches above, loose matches on Subject: below --
2020-09-17  9:16 Jingwen Chen
2020-09-17  9:39 ` Chen, Guchun
2020-09-17  9:44   ` Chen, JingWen
2020-09-17  8:10 Jingwen Chen
2020-09-17  8:21 ` Chen, Guchun
2020-09-17  9:17   ` Chen, JingWen

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).