* [PATCH v1 ] drm/amd/pm: Removed fixed clock in auto mode DPM
@ 2020-09-15 7:18 Sudheesh Mavila
2020-09-15 7:45 ` Christian König
0 siblings, 1 reply; 3+ messages in thread
From: Sudheesh Mavila @ 2020-09-15 7:18 UTC (permalink / raw)
To: sudheesh.mavila, evan.quan, alexander.deucher, christian.koenig,
airlied, daniel, nicholas.kazlauskas, zhengbin13, yanaijie,
tom.stdenis, amd-gfx, linux-kernel, dri-devel
SMU10_UMD_PSTATE_PEAK_FCLK value should not be used to set the DPM.
Change suggested by Evan.Quan@amd.com
Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index c9cfe90a2947..081cb9b1b7c8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -566,6 +566,8 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
struct smu10_hwmgr *data = hwmgr->backend;
uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
+ uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
+ uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
if (hwmgr->smu_version < 0x1E3700) {
pr_info("smu firmware version too old, can not set dpm level\n");
@@ -679,13 +681,13 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
hwmgr->display_config->num_display > 3 ?
- SMU10_UMD_PSTATE_PEAK_FCLK :
+ data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk :
min_mclk,
NULL);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinSocclkByFreq,
- SMU10_UMD_PSTATE_MIN_SOCCLK,
+ data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk,
NULL);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinVcn,
@@ -698,11 +700,11 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
NULL);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxFclkByFreq,
- SMU10_UMD_PSTATE_PEAK_FCLK,
+ data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk,
NULL);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxSocclkByFreq,
- SMU10_UMD_PSTATE_PEAK_SOCCLK,
+ data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk,
NULL);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxVcn,
--
2.17.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v1 ] drm/amd/pm: Removed fixed clock in auto mode DPM
2020-09-15 7:18 [PATCH v1 ] drm/amd/pm: Removed fixed clock in auto mode DPM Sudheesh Mavila
@ 2020-09-15 7:45 ` Christian König
2020-09-21 19:55 ` Alex Deucher
0 siblings, 1 reply; 3+ messages in thread
From: Christian König @ 2020-09-15 7:45 UTC (permalink / raw)
To: Sudheesh Mavila, evan.quan, alexander.deucher, airlied, daniel,
nicholas.kazlauskas, zhengbin13, yanaijie, tom.stdenis, amd-gfx,
linux-kernel, dri-devel
Am 15.09.20 um 09:18 schrieb Sudheesh Mavila:
> SMU10_UMD_PSTATE_PEAK_FCLK value should not be used to set the DPM.
>
> Change suggested by Evan.Quan@amd.com
Can't say much about the change itself, but the Commit message is
indented and the indentation in the code doesn't look consistent either.
Christian.
>
> Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index c9cfe90a2947..081cb9b1b7c8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -566,6 +566,8 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> struct smu10_hwmgr *data = hwmgr->backend;
> uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
> uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
> + uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
> + uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
>
> if (hwmgr->smu_version < 0x1E3700) {
> pr_info("smu firmware version too old, can not set dpm level\n");
> @@ -679,13 +681,13 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetHardMinFclkByFreq,
> hwmgr->display_config->num_display > 3 ?
> - SMU10_UMD_PSTATE_PEAK_FCLK :
> + data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk :
> min_mclk,
> NULL);
>
> smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetHardMinSocclkByFreq,
> - SMU10_UMD_PSTATE_MIN_SOCCLK,
> + data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk,
> NULL);
> smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetHardMinVcn,
> @@ -698,11 +700,11 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> NULL);
> smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetSoftMaxFclkByFreq,
> - SMU10_UMD_PSTATE_PEAK_FCLK,
> + data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk,
> NULL);
> smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetSoftMaxSocclkByFreq,
> - SMU10_UMD_PSTATE_PEAK_SOCCLK,
> + data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk,
> NULL);
> smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetSoftMaxVcn,
_______________________________________________
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1 ] drm/amd/pm: Removed fixed clock in auto mode DPM
2020-09-15 7:45 ` Christian König
@ 2020-09-21 19:55 ` Alex Deucher
0 siblings, 0 replies; 3+ messages in thread
From: Alex Deucher @ 2020-09-21 19:55 UTC (permalink / raw)
To: Christian König
Cc: Tom St Denis, Quan, Evan, Jason Yan, Dave Airlie, LKML,
amd-gfx list, zhengbin, Maling list - DRI developers,
Daniel Vetter, Deucher, Alexander, Sudheesh Mavila, Kazlauskas,
Nicholas
Applied with fixed up whitespace.
Thanks,
Alex
On Tue, Sep 15, 2020 at 3:45 AM Christian König
<christian.koenig@amd.com> wrote:
>
> Am 15.09.20 um 09:18 schrieb Sudheesh Mavila:
> > SMU10_UMD_PSTATE_PEAK_FCLK value should not be used to set the DPM.
> >
> > Change suggested by Evan.Quan@amd.com
>
> Can't say much about the change itself, but the Commit message is
> indented and the indentation in the code doesn't look consistent either.
>
> Christian.
>
> >
> > Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
> > ---
> > drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 ++++++----
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > index c9cfe90a2947..081cb9b1b7c8 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > @@ -566,6 +566,8 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> > struct smu10_hwmgr *data = hwmgr->backend;
> > uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
> > uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
> > + uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
> > + uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
> >
> > if (hwmgr->smu_version < 0x1E3700) {
> > pr_info("smu firmware version too old, can not set dpm level\n");
> > @@ -679,13 +681,13 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_SetHardMinFclkByFreq,
> > hwmgr->display_config->num_display > 3 ?
> > - SMU10_UMD_PSTATE_PEAK_FCLK :
> > + data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk :
> > min_mclk,
> > NULL);
> >
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_SetHardMinSocclkByFreq,
> > - SMU10_UMD_PSTATE_MIN_SOCCLK,
> > + data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk,
> > NULL);
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_SetHardMinVcn,
> > @@ -698,11 +700,11 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> > NULL);
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_SetSoftMaxFclkByFreq,
> > - SMU10_UMD_PSTATE_PEAK_FCLK,
> > + data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk,
> > NULL);
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_SetSoftMaxSocclkByFreq,
> > - SMU10_UMD_PSTATE_PEAK_SOCCLK,
> > + data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk,
> > NULL);
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_SetSoftMaxVcn,
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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2020-09-15 7:18 [PATCH v1 ] drm/amd/pm: Removed fixed clock in auto mode DPM Sudheesh Mavila
2020-09-15 7:45 ` Christian König
2020-09-21 19:55 ` Alex Deucher
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