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* [PATCH] drm/amd/display: fix 64 bit divide in freesync code
@ 2022-04-07 19:50 Alex Deucher
  2022-04-07 23:31 ` Nathan Chancellor
  0 siblings, 1 reply; 5+ messages in thread
From: Alex Deucher @ 2022-04-07 19:50 UTC (permalink / raw)
  To: amd-gfx
  Cc: Alex Deucher, Aric Cyr, Anthony Koo, kernel test robot, Angus Wang

Use do_div() rather than a a 64 bit divide.

Fixes: 3fe5739db48843 ("drm/amd/display: Add flip interval workaround")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Angus Wang <Angus.Wang@amd.com>
Cc: Anthony Koo <Anthony.Koo@amd.com>
Cc: Aric Cyr <Aric.Cyr@amd.com>
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 0130f1879116..70f06fa8cc2b 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1230,6 +1230,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 {
 	struct core_freesync *core_freesync = NULL;
 	unsigned int cur_timestamp_in_us;
+	unsigned long long tmp;
 
 	if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
 		return;
@@ -1239,7 +1240,9 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 	if (in_out_vrr->supported == false)
 		return;
 
-	cur_timestamp_in_us = dm_get_timestamp(core_freesync->dc->ctx)/10;
+	tmp = dm_get_timestamp(core_freesync->dc->ctx);
+	do_div(tmp, 10);
+	cur_timestamp_in_us = tmp;
 
 	in_out_vrr->flip_interval.vsyncs_between_flip++;
 	in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amd/display: fix 64 bit divide in freesync code
  2022-04-07 19:50 [PATCH] drm/amd/display: fix 64 bit divide in freesync code Alex Deucher
@ 2022-04-07 23:31 ` Nathan Chancellor
  2022-04-08 20:51   ` Alex Deucher
  0 siblings, 1 reply; 5+ messages in thread
From: Nathan Chancellor @ 2022-04-07 23:31 UTC (permalink / raw)
  To: Alex Deucher
  Cc: Aric Cyr, Anthony Koo, kernel test robot, amd-gfx, Angus Wang

On Thu, Apr 07, 2022 at 03:50:29PM -0400, Alex Deucher wrote:
> Use do_div() rather than a a 64 bit divide.
> 
> Fixes: 3fe5739db48843 ("drm/amd/display: Add flip interval workaround")
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> Cc: Angus Wang <Angus.Wang@amd.com>
> Cc: Anthony Koo <Anthony.Koo@amd.com>
> Cc: Aric Cyr <Aric.Cyr@amd.com>
> ---
>  drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> index 0130f1879116..70f06fa8cc2b 100644
> --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> @@ -1230,6 +1230,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
>  {
>  	struct core_freesync *core_freesync = NULL;
>  	unsigned int cur_timestamp_in_us;
> +	unsigned long long tmp;
>  
>  	if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
>  		return;
> @@ -1239,7 +1240,9 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
>  	if (in_out_vrr->supported == false)
>  		return;
>  
> -	cur_timestamp_in_us = dm_get_timestamp(core_freesync->dc->ctx)/10;
> +	tmp = dm_get_timestamp(core_freesync->dc->ctx);
> +	do_div(tmp, 10);
> +	cur_timestamp_in_us = tmp;

Any reason not to use

cur_timestamp_in_us = div_u64(dm_get_timestamp(core_freesync->dc->ctx), 10)

and save a variable?

>  	in_out_vrr->flip_interval.vsyncs_between_flip++;
>  	in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
> -- 
> 2.35.1
> 
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amd/display: fix 64 bit divide in freesync code
  2022-04-07 23:31 ` Nathan Chancellor
@ 2022-04-08 20:51   ` Alex Deucher
  0 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2022-04-08 20:51 UTC (permalink / raw)
  To: Nathan Chancellor
  Cc: Aric Cyr, kernel test robot, amd-gfx list, Angus Wang,
	Alex Deucher, Anthony Koo

On Thu, Apr 7, 2022 at 7:31 PM Nathan Chancellor <nathan@kernel.org> wrote:
>
> On Thu, Apr 07, 2022 at 03:50:29PM -0400, Alex Deucher wrote:
> > Use do_div() rather than a a 64 bit divide.
> >
> > Fixes: 3fe5739db48843 ("drm/amd/display: Add flip interval workaround")
> > Reported-by: kernel test robot <lkp@intel.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Angus Wang <Angus.Wang@amd.com>
> > Cc: Anthony Koo <Anthony.Koo@amd.com>
> > Cc: Aric Cyr <Aric.Cyr@amd.com>
> > ---
> >  drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 5 ++++-
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> > index 0130f1879116..70f06fa8cc2b 100644
> > --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> > +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> > @@ -1230,6 +1230,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
> >  {
> >       struct core_freesync *core_freesync = NULL;
> >       unsigned int cur_timestamp_in_us;
> > +     unsigned long long tmp;
> >
> >       if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
> >               return;
> > @@ -1239,7 +1240,9 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
> >       if (in_out_vrr->supported == false)
> >               return;
> >
> > -     cur_timestamp_in_us = dm_get_timestamp(core_freesync->dc->ctx)/10;
> > +     tmp = dm_get_timestamp(core_freesync->dc->ctx);
> > +     do_div(tmp, 10);
> > +     cur_timestamp_in_us = tmp;
>
> Any reason not to use
>
> cur_timestamp_in_us = div_u64(dm_get_timestamp(core_freesync->dc->ctx), 10)
>
> and save a variable?

I can do that.

Alex

>
> >       in_out_vrr->flip_interval.vsyncs_between_flip++;
> >       in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
> > --
> > 2.35.1
> >
> >

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amd/display: fix 64 bit divide in freesync code
  2022-04-08 21:04 Alex Deucher
@ 2022-04-08 21:07 ` Nathan Chancellor
  0 siblings, 0 replies; 5+ messages in thread
From: Nathan Chancellor @ 2022-04-08 21:07 UTC (permalink / raw)
  To: Alex Deucher
  Cc: Aric Cyr, Anthony Koo, kernel test robot, amd-gfx, Angus Wang

On Fri, Apr 08, 2022 at 05:04:55PM -0400, Alex Deucher wrote:
> Use div_u64() rather than a a 64 bit divide.
> 
> Fixes: 3fe5739db48843 ("drm/amd/display: Add flip interval workaround")
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> Cc: Angus Wang <Angus.Wang@amd.com>
> Cc: Anthony Koo <Anthony.Koo@amd.com>
> Cc: Aric Cyr <Aric.Cyr@amd.com>
> Cc: Nathan Chancellor <nathan@kernel.org>

This resolves the build failure for me.

Reviewed-by: Nathan Chancellor <nathan@kernel.org>

> ---
>  drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> index 0130f1879116..d2d76ce56f89 100644
> --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> @@ -1239,7 +1239,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
>  	if (in_out_vrr->supported == false)
>  		return;
>  
> -	cur_timestamp_in_us = dm_get_timestamp(core_freesync->dc->ctx)/10;
> +	cur_timestamp_in_us = div_u64(dm_get_timestamp(core_freesync->dc->ctx), 10);
>  
>  	in_out_vrr->flip_interval.vsyncs_between_flip++;
>  	in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
> -- 
> 2.35.1
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH] drm/amd/display: fix 64 bit divide in freesync code
@ 2022-04-08 21:04 Alex Deucher
  2022-04-08 21:07 ` Nathan Chancellor
  0 siblings, 1 reply; 5+ messages in thread
From: Alex Deucher @ 2022-04-08 21:04 UTC (permalink / raw)
  To: amd-gfx
  Cc: Aric Cyr, kernel test robot, Nathan Chancellor, Angus Wang,
	Alex Deucher, Anthony Koo

Use div_u64() rather than a a 64 bit divide.

Fixes: 3fe5739db48843 ("drm/amd/display: Add flip interval workaround")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Angus Wang <Angus.Wang@amd.com>
Cc: Anthony Koo <Anthony.Koo@amd.com>
Cc: Aric Cyr <Aric.Cyr@amd.com>
Cc: Nathan Chancellor <nathan@kernel.org>
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 0130f1879116..d2d76ce56f89 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1239,7 +1239,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 	if (in_out_vrr->supported == false)
 		return;
 
-	cur_timestamp_in_us = dm_get_timestamp(core_freesync->dc->ctx)/10;
+	cur_timestamp_in_us = div_u64(dm_get_timestamp(core_freesync->dc->ctx), 10);
 
 	in_out_vrr->flip_interval.vsyncs_between_flip++;
 	in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-04-08 21:07 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2022-04-07 19:50 [PATCH] drm/amd/display: fix 64 bit divide in freesync code Alex Deucher
2022-04-07 23:31 ` Nathan Chancellor
2022-04-08 20:51   ` Alex Deucher
2022-04-08 21:04 Alex Deucher
2022-04-08 21:07 ` Nathan Chancellor

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