* [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance
@ 2022-05-03 20:38 Alex Deucher
2022-05-03 20:38 ` [PATCH 2/2] drm/amdgpu: skip the new gc doorbell function for some asics Alex Deucher
2022-05-04 6:27 ` [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance Christian König
0 siblings, 2 replies; 5+ messages in thread
From: Alex Deucher @ 2022-05-03 20:38 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui, Xiaojian Du
From: Xiaojian Du <Xiaojian.Du@amd.com>
This patch will handle asics with 1 SDMA instance.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 307a1da13557..29acc5573f56 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -252,8 +252,9 @@ static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
*value = 0;
for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
en = &soc21_allowed_read_registers[i];
- if (reg_offset !=
- (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
+ if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
+ reg_offset !=
+ (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
continue;
*value = soc21_get_register_value(adev,
--
2.35.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/amdgpu: skip the new gc doorbell function for some asics
2022-05-03 20:38 [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance Alex Deucher
@ 2022-05-03 20:38 ` Alex Deucher
2022-05-04 6:27 ` [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance Christian König
1 sibling, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2022-05-03 20:38 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Huang Rui, Xiaojian Du
From: Xiaojian Du <Xiaojian.Du@amd.com>
This patch will skip the new gc doorbell function for some asics,
only enable new doorbell model on aisc where it is supported.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 97d37b2e58f2..85fddec0d4ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4592,7 +4592,8 @@ static int gfx_v11_0_hw_init(void *handle)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
gfx_v11_0_select_cp_fw_arch(adev);
- adev->nbio.funcs->gc_doorbell_init(adev);
+ if (adev->nbio.funcs->gc_doorbell_init)
+ adev->nbio.funcs->gc_doorbell_init(adev);
r = gfx_v11_0_rlc_resume(adev);
if (r)
--
2.35.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance
2022-05-03 20:38 [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance Alex Deucher
2022-05-03 20:38 ` [PATCH 2/2] drm/amdgpu: skip the new gc doorbell function for some asics Alex Deucher
@ 2022-05-04 6:27 ` Christian König
2022-05-05 2:52 ` Alex Deucher
1 sibling, 1 reply; 5+ messages in thread
From: Christian König @ 2022-05-04 6:27 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Huang Rui, Xiaojian Du
Am 03.05.22 um 22:38 schrieb Alex Deucher:
> From: Xiaojian Du <Xiaojian.Du@amd.com>
>
> This patch will handle asics with 1 SDMA instance.
>
> Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/soc21.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index 307a1da13557..29acc5573f56 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -252,8 +252,9 @@ static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
> *value = 0;
> for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
> en = &soc21_allowed_read_registers[i];
> - if (reg_offset !=
> - (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
> + if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
> + reg_offset !=
> + (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
Hui what? Why do we filter out register reads in the low level function?
> continue;
>
> *value = soc21_get_register_value(adev,
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance
2022-05-04 6:27 ` [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance Christian König
@ 2022-05-05 2:52 ` Alex Deucher
2022-05-05 6:23 ` Huang Rui
0 siblings, 1 reply; 5+ messages in thread
From: Alex Deucher @ 2022-05-05 2:52 UTC (permalink / raw)
To: Christian König; +Cc: Alex Deucher, Huang Rui, Xiaojian Du, amd-gfx list
On Wed, May 4, 2022 at 2:28 AM Christian König <christian.koenig@amd.com> wrote:
>
> Am 03.05.22 um 22:38 schrieb Alex Deucher:
> > From: Xiaojian Du <Xiaojian.Du@amd.com>
> >
> > This patch will handle asics with 1 SDMA instance.
> >
> > Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
> > Reviewed-by: Huang Rui <ray.huang@amd.com>
> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/soc21.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> > index 307a1da13557..29acc5573f56 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> > @@ -252,8 +252,9 @@ static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
> > *value = 0;
> > for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
> > en = &soc21_allowed_read_registers[i];
> > - if (reg_offset !=
> > - (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
> > + if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
> > + reg_offset !=
> > + (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
>
> Hui what? Why do we filter out register reads in the low level function?
It was copied from nv.c. The proper solution is to handle it like we
do in soc15.c:
if (adev->reg_offset[en->hwip][en->inst] &&
reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
+ en->reg_offset))
continue;
Alex
>
> > continue;
> >
> > *value = soc21_get_register_value(adev,
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance
2022-05-05 2:52 ` Alex Deucher
@ 2022-05-05 6:23 ` Huang Rui
0 siblings, 0 replies; 5+ messages in thread
From: Huang Rui @ 2022-05-05 6:23 UTC (permalink / raw)
To: Alex Deucher, Koenig, Christian
Cc: Deucher, Alexander, Du, Xiaojian, amd-gfx list
On Thu, May 05, 2022 at 10:52:31AM +0800, Alex Deucher wrote:
> On Wed, May 4, 2022 at 2:28 AM Christian König <christian.koenig@amd.com> wrote:
> >
> > Am 03.05.22 um 22:38 schrieb Alex Deucher:
> > > From: Xiaojian Du <Xiaojian.Du@amd.com>
> > >
> > > This patch will handle asics with 1 SDMA instance.
> > >
> > > Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
> > > Reviewed-by: Huang Rui <ray.huang@amd.com>
> > > Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/soc21.c | 5 +++--
> > > 1 file changed, 3 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> > > index 307a1da13557..29acc5573f56 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> > > @@ -252,8 +252,9 @@ static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
> > > *value = 0;
> > > for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
> > > en = &soc21_allowed_read_registers[i];
> > > - if (reg_offset !=
> > > - (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
> > > + if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
> > > + reg_offset !=
> > > + (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
> >
> > Hui what? Why do we filter out register reads in the low level function?
>
> It was copied from nv.c. The proper solution is to handle it like we
> do in soc15.c:
> if (adev->reg_offset[en->hwip][en->inst] &&
> reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
> + en->reg_offset))
> continue;
>
The SDMA1_BASE are not contained in GC V11.0.1 APUs, so cannot refer this
pointer. Above check is better than before, thanks!
Thanks,
Ray
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-05-05 6:24 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2022-05-03 20:38 [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance Alex Deucher
2022-05-03 20:38 ` [PATCH 2/2] drm/amdgpu: skip the new gc doorbell function for some asics Alex Deucher
2022-05-04 6:27 ` [PATCH 1/2] drm/amdgpu: handle asics with 1 SDMA instance Christian König
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