* [bug report] drm/amd/display: DML changes for DCN32/321
@ 2022-07-26 15:25 Dan Carpenter
0 siblings, 0 replies; only message in thread
From: Dan Carpenter @ 2022-07-26 15:25 UTC (permalink / raw)
To: aurabindo.pillai; +Cc: amd-gfx
Hello Aurabindo Pillai,
The patch dda4fb85e433: "drm/amd/display: DML changes for DCN32/321"
from Feb 21, 2022, leads to the following Smatch static checker
warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:1631 dml32_TruncToValidBPP() error: uninitialized symbol 'NonDSCBPP3'.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:1644 dml32_TruncToValidBPP() error: uninitialized symbol 'NonDSCBPP3'.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:1651 dml32_TruncToValidBPP() warn: ignoring unreachable code.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:713 dml32_CalculateSwathWidth() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c
1540 double dml32_TruncToValidBPP(
1541 double LinkBitRate,
1542 unsigned int Lanes,
1543 unsigned int HTotal,
1544 unsigned int HActive,
1545 double PixelClock,
1546 double DesiredBPP,
1547 bool DSCEnable,
1548 enum output_encoder_class Output,
1549 enum output_format_class Format,
1550 unsigned int DSCInputBitPerComponent,
1551 unsigned int DSCSlices,
1552 unsigned int AudioRate,
1553 unsigned int AudioLayout,
1554 enum odm_combine_mode ODMModeNoDSC,
1555 enum odm_combine_mode ODMModeDSC,
1556 /* Output */
1557 unsigned int *RequiredSlots)
1558 {
1559 double MaxLinkBPP;
1560 unsigned int MinDSCBPP;
1561 double MaxDSCBPP;
1562 unsigned int NonDSCBPP0;
1563 unsigned int NonDSCBPP1;
1564 unsigned int NonDSCBPP2;
1565 unsigned int NonDSCBPP3;
1566
1567 if (Format == dm_420) {
1568 NonDSCBPP0 = 12;
1569 NonDSCBPP1 = 15;
1570 NonDSCBPP2 = 18;
1571 MinDSCBPP = 6;
1572 MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;
1573 } else if (Format == dm_444) {
1574 NonDSCBPP0 = 18;
1575 NonDSCBPP1 = 24;
1576 NonDSCBPP2 = 30;
1577 NonDSCBPP3 = 36;
NonDSCBPP3 is initialized here but not on other paths.
1578 MinDSCBPP = 8;
1579 MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
1580 } else {
1581 if (Output == dm_hdmi) {
1582 NonDSCBPP0 = 24;
1583 NonDSCBPP1 = 24;
1584 NonDSCBPP2 = 24;
1585 } else {
1586 NonDSCBPP0 = 16;
1587 NonDSCBPP1 = 20;
1588 NonDSCBPP2 = 24;
1589 }
1590 if (Format == dm_n422) {
1591 MinDSCBPP = 7;
1592 MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0 / 16.0;
1593 } else {
1594 MinDSCBPP = 8;
1595 MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16.0;
1596 }
1597 }
1598 if (Output == dm_dp2p0) {
1599 MaxLinkBPP = LinkBitRate * Lanes / PixelClock * 128 / 132 * 383 / 384 * 65536 / 65540;
1600 } else if (DSCEnable && Output == dm_dp) {
1601 MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock * (1 - 2.4 / 100);
1602 } else {
1603 MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock;
1604 }
1605
1606 if (DSCEnable) {
1607 if (ODMModeDSC == dm_odm_combine_mode_4to1)
1608 MaxLinkBPP = dml_min(MaxLinkBPP, 16);
1609 else if (ODMModeDSC == dm_odm_combine_mode_2to1)
1610 MaxLinkBPP = dml_min(MaxLinkBPP, 32);
1611 else if (ODMModeDSC == dm_odm_split_mode_1to2)
1612 MaxLinkBPP = 2 * MaxLinkBPP;
1613 } else {
1614 if (ODMModeNoDSC == dm_odm_combine_mode_4to1)
1615 MaxLinkBPP = dml_min(MaxLinkBPP, 16);
1616 else if (ODMModeNoDSC == dm_odm_combine_mode_2to1)
1617 MaxLinkBPP = dml_min(MaxLinkBPP, 32);
1618 else if (ODMModeNoDSC == dm_odm_split_mode_1to2)
1619 MaxLinkBPP = 2 * MaxLinkBPP;
1620 }
1621
1622 if (DesiredBPP == 0) {
1623 if (DSCEnable) {
1624 if (MaxLinkBPP < MinDSCBPP)
1625 return BPP_INVALID;
1626 else if (MaxLinkBPP >= MaxDSCBPP)
1627 return MaxDSCBPP;
1628 else
1629 return dml_floor(16.0 * MaxLinkBPP, 1.0) / 16.0;
1630 } else {
--> 1631 if (MaxLinkBPP >= NonDSCBPP3)
1632 return NonDSCBPP3;
1633 else if (MaxLinkBPP >= NonDSCBPP2)
1634 return NonDSCBPP2;
1635 else if (MaxLinkBPP >= NonDSCBPP1)
1636 return NonDSCBPP1;
1637 else if (MaxLinkBPP >= NonDSCBPP0)
1638 return 16.0;
1639 else
1640 return BPP_INVALID;
1641 }
1642 } else {
1643 if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 ||
1644 DesiredBPP == NonDSCBPP0 || DesiredBPP == NonDSCBPP3)) ||
1645 (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP)))
1646 return BPP_INVALID;
1647 else
1648 return DesiredBPP;
1649 }
1650
1651 *RequiredSlots = dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1);
1652
1653 return BPP_INVALID;
1654 } // TruncToValidBPP
regards,
dan carpenter
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