* [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter
@ 2020-11-11 22:27 James Zhu
2020-11-11 22:27 ` [PATCH 2/5] drm/amdgpu/vcn: update header to support dec vcn software ring James Zhu
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: James Zhu @ 2020-11-11 22:27 UTC (permalink / raw)
To: amd-gfx
This allows us to enable dec software ring feature on VCN.
The default is 0 for all asics, and it is only valid for
asics with vcn3.0 and above.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 20400ec..cc47da6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -209,6 +209,7 @@ extern int amdgpu_si_support;
extern int amdgpu_cik_support;
#endif
extern int amdgpu_num_kcq;
+extern int amdgpu_dec_sw_ring_enabled;
#define AMDGPU_VM_MAX_NUM_CTX 4096
#define AMDGPU_SG_THRESHOLD (256*1024*1024)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 999f84d..570088f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
int amdgpu_tmz;
int amdgpu_reset_method = -1; /* auto */
int amdgpu_num_kcq = -1;
+int amdgpu_dec_sw_ring_enabled;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -806,6 +807,13 @@ module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
+/**
+ * DOC: dec_sw_ring_enabled (uint)
+ * Override vcn decode software ring features enabled.
+ */
+MODULE_PARM_DESC(dec_sw_ring_enabled, "vcn dec sw ring support (1 = enable, 0 = disable (default))");
+module_param_named(dec_sw_ring_enabled, amdgpu_dec_sw_ring_enabled, int, 0444);
+
static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/5] drm/amdgpu/vcn: update header to support dec vcn software ring
2020-11-11 22:27 [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter James Zhu
@ 2020-11-11 22:27 ` James Zhu
2020-11-11 22:27 ` [PATCH 3/5] drm/amdgpu/vcn: add test for " James Zhu
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: James Zhu @ 2020-11-11 22:27 UTC (permalink / raw)
To: amd-gfx
Add macro, structure and function prototype to
support dec vcn software ring.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 1769115..13aa417 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -44,6 +44,17 @@
#define VCN_DEC_CMD_PACKET_START 0x0000000a
#define VCN_DEC_CMD_PACKET_END 0x0000000b
+#define VCN_DEC_SW_CMD_NO_OP 0x00000000
+#define VCN_DEC_SW_CMD_END 0x00000001
+#define VCN_DEC_SW_CMD_IB 0x00000002
+#define VCN_DEC_SW_CMD_FENCE 0x00000003
+#define VCN_DEC_SW_CMD_TRAP 0x00000004
+#define VCN_DEC_SW_CMD_IB_AUTO 0x00000005
+#define VCN_DEC_SW_CMD_SEMAPHORE 0x00000006
+#define VCN_DEC_SW_CMD_PREEMPT_FENCE 0x00000009
+#define VCN_DEC_SW_CMD_REG_WRITE 0x0000000b
+#define VCN_DEC_SW_CMD_REG_WAIT 0x0000000c
+
#define VCN_ENC_CMD_NO_OP 0x00000000
#define VCN_ENC_CMD_END 0x00000001
#define VCN_ENC_CMD_IB 0x00000002
@@ -145,6 +156,10 @@
} while (0)
#define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8)
+#define AMDGPU_VCN_SW_RING_FLAG (1 << 9)
+
+#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
+#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
enum fw_queue_mode {
FW_QUEUE_RING_RESET = 1,
@@ -236,12 +251,25 @@ struct amdgpu_fw_shared_multi_queue {
uint8_t padding[4];
};
+struct amdgpu_fw_shared_sw_ring {
+ uint8_t is_enabled;
+ uint8_t padding[3];
+};
+
struct amdgpu_fw_shared {
uint32_t present_flag_0;
uint8_t pad[53];
struct amdgpu_fw_shared_multi_queue multi_queue;
+ struct amdgpu_fw_shared_sw_ring sw_ring;
} __attribute__((__packed__));
+struct amdgpu_vcn_decode_buffer {
+ uint32_t valid_buf_flag;
+ uint32_t msg_buffer_address_hi;
+ uint32_t msg_buffer_address_lo;
+ uint32_t pad[30];
+};
+
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
@@ -251,6 +279,8 @@ void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
+int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/5] drm/amdgpu/vcn: add test for dec vcn software ring
2020-11-11 22:27 [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter James Zhu
2020-11-11 22:27 ` [PATCH 2/5] drm/amdgpu/vcn: update header to support dec vcn software ring James Zhu
@ 2020-11-11 22:27 ` James Zhu
2020-11-12 1:00 ` [PATCH v2 " James Zhu
2020-11-16 11:42 ` [PATCH " Christian König
2020-11-11 22:27 ` [PATCH 4/5] drm/amdgpu/vcn3.0: add dec software ring vm functions to support James Zhu
` (3 subsequent siblings)
5 siblings, 2 replies; 12+ messages in thread
From: James Zhu @ 2020-11-11 22:27 UTC (permalink / raw)
To: amd-gfx
Add vcn software ring decode ring test and decode ib test.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 138 ++++++++++++++++++++++++++++++--
1 file changed, 132 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7e19a66..e3d54fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -456,6 +456,37 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
return r;
}
+int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t rptr;
+ unsigned int i;
+ int r;
+
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ r = amdgpu_ring_alloc(ring, 16);
+ if (r)
+ return r;
+
+ rptr = amdgpu_ring_get_rptr(ring);
+
+ amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
+ amdgpu_ring_commit(ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (amdgpu_ring_get_rptr(ring) != rptr)
+ break;
+ udelay(1);
+ }
+
+ if (i >= adev->usec_timeout)
+ r = -ETIMEDOUT;
+
+ return r;
+}
+
static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
struct amdgpu_bo *bo,
struct dma_fence **fence)
@@ -510,7 +541,10 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
}
static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct dma_fence **fence)
+ struct dma_fence **fence,
+ int (*send_msg)(struct amdgpu_ring *,
+ struct amdgpu_bo *,
+ struct dma_fence **))
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_bo *bo = NULL;
@@ -540,13 +574,17 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
for (i = 14; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
- return amdgpu_vcn_dec_send_msg(ring, bo, fence);
+ return send_msg(ring, bo, fence);
}
static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct dma_fence **fence)
+ struct dma_fence **fence,
+ int (*send_msg)(struct amdgpu_ring *,
+ struct amdgpu_bo *,
+ struct dma_fence **))
{
struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_send_msg *dec;
struct amdgpu_bo *bo = NULL;
uint32_t *msg;
int r, i;
@@ -566,19 +604,107 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
for (i = 6; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
- return amdgpu_vcn_dec_send_msg(ring, bo, fence);
+ return send_msg(ring, bo, fence);
}
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
+ struct amdgpu_device *adev = ring->adev;
struct dma_fence *fence;
long r;
- r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
+ r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL,
+ amdgpu_vcn_dec_send_msg);
+ if (r)
+ goto error;
+
+ r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence,
+ amdgpu_vcn_dec_send_msg);
+ if (r)
+ goto error;
+
+ r = dma_fence_wait_timeout(fence, false, timeout);
+ if (r == 0)
+ r = -ETIMEDOUT;
+ else if (r > 0)
+ r = 0;
+
+ dma_fence_put(fence);
+error:
+ return r;
+}
+
+static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
+ struct amdgpu_bo *bo,
+ struct dma_fence **fence)
+{
+ struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
+ const unsigned int ib_size_dw = 64;
+ struct amdgpu_device *adev = ring->adev;
+ struct dma_fence *f = NULL;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
+ AMDGPU_IB_POOL_DIRECT, &job);
+ if (r)
+ goto err;
+
+ ib = &job->ibs[0];
+ addr = amdgpu_bo_gpu_offset(bo);
+ ib->length_dw = 0;
+
+ ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
+ ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
+ decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
+ ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
+ memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
+
+ decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
+ decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
+ decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
+
+ for (i = ib->length_dw; i < ib_size_dw; ++i)
+ ib->ptr[i] = 0x0;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r)
+ goto err_free;
+
+ amdgpu_bo_fence(bo, f, false);
+ amdgpu_bo_unreserve(bo);
+ amdgpu_bo_unref(&bo);
+
+ if (fence)
+ *fence = dma_fence_get(f);
+ dma_fence_put(f);
+
+ return 0;
+
+err_free:
+ amdgpu_job_free(job);
+
+err:
+ amdgpu_bo_unreserve(bo);
+ amdgpu_bo_unref(&bo);
+ return r;
+}
+
+int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+ struct amdgpu_device *adev = ring->adev;
+ struct dma_fence *fence = NULL;
+ long r;
+
+ r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL,
+ amdgpu_vcn_dec_sw_send_msg);
if (r)
goto error;
- r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
+ r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence,
+ amdgpu_vcn_dec_sw_send_msg);
if (r)
goto error;
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/5] drm/amdgpu/vcn3.0: add dec software ring vm functions to support
2020-11-11 22:27 [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter James Zhu
2020-11-11 22:27 ` [PATCH 2/5] drm/amdgpu/vcn: update header to support dec vcn software ring James Zhu
2020-11-11 22:27 ` [PATCH 3/5] drm/amdgpu/vcn: add test for " James Zhu
@ 2020-11-11 22:27 ` James Zhu
2020-11-11 22:27 ` [PATCH 5/5] drm/amdgpu/vcn3.0: add software ring share memory support James Zhu
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: James Zhu @ 2020-11-11 22:27 UTC (permalink / raw)
To: amd-gfx
Add dec software ring vm functions to support.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 100 +++++++++++++++++++++++++++++++++-
1 file changed, 98 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index c5e0a53..9d3c902 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1673,6 +1673,98 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
}
}
+void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+ u64 seq, uint32_t flags)
+{
+ WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+ amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
+ amdgpu_ring_write(ring, addr);
+ amdgpu_ring_write(ring, upper_32_bits(addr));
+ amdgpu_ring_write(ring, seq);
+ amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
+}
+
+void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
+{
+ amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
+}
+
+void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ struct amdgpu_ib *ib,
+ uint32_t flags)
+{
+ uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
+
+ amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
+ amdgpu_ring_write(ring, vmid);
+ amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+ amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+ amdgpu_ring_write(ring, ib->length_dw);
+}
+
+void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+ uint32_t val, uint32_t mask)
+{
+ amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
+ amdgpu_ring_write(ring, reg << 2);
+ amdgpu_ring_write(ring, mask);
+ amdgpu_ring_write(ring, val);
+}
+
+void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
+ uint32_t vmid, uint64_t pd_addr)
+{
+ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+ uint32_t data0, data1, mask;
+
+ pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for register write */
+ data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
+ data1 = lower_32_bits(pd_addr);
+ mask = 0xffffffff;
+ vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
+}
+
+void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
+{
+ amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
+ amdgpu_ring_write(ring, reg << 2);
+ amdgpu_ring_write(ring, val);
+}
+
+static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
+ .type = AMDGPU_RING_TYPE_VCN_DEC,
+ .align_mask = 0x3f,
+ .nop = VCN_DEC_SW_CMD_NO_OP,
+ .vmhub = AMDGPU_MMHUB_0,
+ .get_rptr = vcn_v3_0_dec_ring_get_rptr,
+ .get_wptr = vcn_v3_0_dec_ring_get_wptr,
+ .set_wptr = vcn_v3_0_dec_ring_set_wptr,
+ .emit_frame_size =
+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
+ 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */
+ 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */
+ 1, /* vcn_v3_0_dec_sw_ring_insert_end */
+ .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */
+ .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib,
+ .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence,
+ .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush,
+ .test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
+ .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib,
+ .insert_nop = amdgpu_ring_insert_nop,
+ .insert_end = vcn_v3_0_dec_sw_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_vcn_ring_begin_use,
+ .end_use = amdgpu_vcn_ring_end_use,
+ .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg,
+ .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait,
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+};
+
static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_VCN_DEC,
.align_mask = 0xf,
@@ -1810,9 +1902,13 @@ static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
if (adev->vcn.harvest_config & (1 << i))
continue;
- adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
+ if (!amdgpu_dec_sw_ring_enabled)
+ adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
+ else
+ adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
adev->vcn.inst[i].ring_dec.me = i;
- DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
+ DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i,
+ !!amdgpu_dec_sw_ring_enabled?"(Software Ring)":"");
}
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/5] drm/amdgpu/vcn3.0: add software ring share memory support
2020-11-11 22:27 [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter James Zhu
` (2 preceding siblings ...)
2020-11-11 22:27 ` [PATCH 4/5] drm/amdgpu/vcn3.0: add dec software ring vm functions to support James Zhu
@ 2020-11-11 22:27 ` James Zhu
2020-11-12 14:23 ` [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter Alex Deucher
2020-11-16 11:38 ` Christian König
5 siblings, 0 replies; 12+ messages in thread
From: James Zhu @ 2020-11-11 22:27 UTC (permalink / raw)
To: amd-gfx
Support software ring share memory with vcn firmware.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 35 +++++++++++++++++++++++++++++++----
1 file changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 9d3c902..18a56c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -169,6 +169,7 @@ static int vcn_v3_0_sw_init(void *handle)
}
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ volatile struct amdgpu_fw_shared *fw_shared;
if (adev->vcn.harvest_config & (1 << i))
continue;
@@ -233,6 +234,10 @@ static int vcn_v3_0_sw_init(void *handle)
if (r)
return r;
}
+
+ fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
+ fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG);
+ fw_shared->sw_ring.is_enabled = cpu_to_le32(!!amdgpu_dec_sw_ring_enabled);
}
if (amdgpu_sriov_vf(adev)) {
@@ -256,7 +261,17 @@ static int vcn_v3_0_sw_init(void *handle)
static int vcn_v3_0_sw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- int r;
+ int i, r;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ volatile struct amdgpu_fw_shared *fw_shared;
+
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+ fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
+ fw_shared->present_flag_0 = 0;
+ fw_shared->sw_ring.is_enabled = false;
+ }
if (amdgpu_sriov_vf(adev))
amdgpu_virt_free_mm_table(adev);
@@ -466,6 +481,15 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+
+ /* non-cache window */
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
+ lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
+ upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
+ WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,
+ AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
}
static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
@@ -548,13 +572,16 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
/* non-cache window */
WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
- VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
+ VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
- VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
+ VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
- VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
+ VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),
+ AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
}
static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 3/5] drm/amdgpu/vcn: add test for dec vcn software ring
2020-11-11 22:27 ` [PATCH 3/5] drm/amdgpu/vcn: add test for " James Zhu
@ 2020-11-12 1:00 ` James Zhu
2020-11-16 11:42 ` [PATCH " Christian König
1 sibling, 0 replies; 12+ messages in thread
From: James Zhu @ 2020-11-12 1:00 UTC (permalink / raw)
To: amd-gfx
Add vcn software ring decode ring test and decode ib test.
v2: clear compilation warning.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 135 ++++++++++++++++++++++++++++++--
1 file changed, 129 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7e19a66..cbd8b5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -456,6 +456,37 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
return r;
}
+int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t rptr;
+ unsigned int i;
+ int r;
+
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ r = amdgpu_ring_alloc(ring, 16);
+ if (r)
+ return r;
+
+ rptr = amdgpu_ring_get_rptr(ring);
+
+ amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
+ amdgpu_ring_commit(ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (amdgpu_ring_get_rptr(ring) != rptr)
+ break;
+ udelay(1);
+ }
+
+ if (i >= adev->usec_timeout)
+ r = -ETIMEDOUT;
+
+ return r;
+}
+
static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
struct amdgpu_bo *bo,
struct dma_fence **fence)
@@ -510,7 +541,10 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
}
static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct dma_fence **fence)
+ struct dma_fence **fence,
+ int (*send_msg)(struct amdgpu_ring *,
+ struct amdgpu_bo *,
+ struct dma_fence **))
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_bo *bo = NULL;
@@ -540,11 +574,14 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
for (i = 14; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
- return amdgpu_vcn_dec_send_msg(ring, bo, fence);
+ return send_msg(ring, bo, fence);
}
static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct dma_fence **fence)
+ struct dma_fence **fence,
+ int (*send_msg)(struct amdgpu_ring *,
+ struct amdgpu_bo *,
+ struct dma_fence **))
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_bo *bo = NULL;
@@ -566,7 +603,7 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
for (i = 6; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
- return amdgpu_vcn_dec_send_msg(ring, bo, fence);
+ return send_msg(ring, bo, fence);
}
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
@@ -574,11 +611,97 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
struct dma_fence *fence;
long r;
- r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
+ r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL,
+ amdgpu_vcn_dec_send_msg);
+ if (r)
+ goto error;
+
+ r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence,
+ amdgpu_vcn_dec_send_msg);
+ if (r)
+ goto error;
+
+ r = dma_fence_wait_timeout(fence, false, timeout);
+ if (r == 0)
+ r = -ETIMEDOUT;
+ else if (r > 0)
+ r = 0;
+
+ dma_fence_put(fence);
+error:
+ return r;
+}
+
+static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
+ struct amdgpu_bo *bo,
+ struct dma_fence **fence)
+{
+ struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
+ const unsigned int ib_size_dw = 64;
+ struct amdgpu_device *adev = ring->adev;
+ struct dma_fence *f = NULL;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
+ AMDGPU_IB_POOL_DIRECT, &job);
+ if (r)
+ goto err;
+
+ ib = &job->ibs[0];
+ addr = amdgpu_bo_gpu_offset(bo);
+ ib->length_dw = 0;
+
+ ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
+ ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
+ decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
+ ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
+ memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
+
+ decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
+ decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
+ decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
+
+ for (i = ib->length_dw; i < ib_size_dw; ++i)
+ ib->ptr[i] = 0x0;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r)
+ goto err_free;
+
+ amdgpu_bo_fence(bo, f, false);
+ amdgpu_bo_unreserve(bo);
+ amdgpu_bo_unref(&bo);
+
+ if (fence)
+ *fence = dma_fence_get(f);
+ dma_fence_put(f);
+
+ return 0;
+
+err_free:
+ amdgpu_job_free(job);
+
+err:
+ amdgpu_bo_unreserve(bo);
+ amdgpu_bo_unref(&bo);
+ return r;
+}
+
+int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+ struct dma_fence *fence = NULL;
+ long r;
+
+ r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL,
+ amdgpu_vcn_dec_sw_send_msg);
if (r)
goto error;
- r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
+ r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence,
+ amdgpu_vcn_dec_sw_send_msg);
if (r)
goto error;
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter
2020-11-11 22:27 [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter James Zhu
` (3 preceding siblings ...)
2020-11-11 22:27 ` [PATCH 5/5] drm/amdgpu/vcn3.0: add software ring share memory support James Zhu
@ 2020-11-12 14:23 ` Alex Deucher
2020-11-12 15:23 ` James Zhu
2020-11-16 11:38 ` Christian König
5 siblings, 1 reply; 12+ messages in thread
From: Alex Deucher @ 2020-11-12 14:23 UTC (permalink / raw)
To: James Zhu; +Cc: amd-gfx list
On Wed, Nov 11, 2020 at 5:28 PM James Zhu <James.Zhu@amd.com> wrote:
>
> This allows us to enable dec software ring feature on VCN.
> The default is 0 for all asics, and it is only valid for
> asics with vcn3.0 and above.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> Reviewed-by: Leo Liu <leo.liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 20400ec..cc47da6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -209,6 +209,7 @@ extern int amdgpu_si_support;
> extern int amdgpu_cik_support;
> #endif
> extern int amdgpu_num_kcq;
> +extern int amdgpu_dec_sw_ring_enabled;
>
> #define AMDGPU_VM_MAX_NUM_CTX 4096
> #define AMDGPU_SG_THRESHOLD (256*1024*1024)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 999f84d..570088f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
> int amdgpu_tmz;
> int amdgpu_reset_method = -1; /* auto */
> int amdgpu_num_kcq = -1;
> +int amdgpu_dec_sw_ring_enabled;
>
> struct amdgpu_mgpu_info mgpu_info = {
> .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
> @@ -806,6 +807,13 @@ module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
> MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
> module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
>
> +/**
> + * DOC: dec_sw_ring_enabled (uint)
> + * Override vcn decode software ring features enabled.
> + */
> +MODULE_PARM_DESC(dec_sw_ring_enabled, "vcn dec sw ring support (1 = enable, 0 = disable (default))");
> +module_param_named(dec_sw_ring_enabled, amdgpu_dec_sw_ring_enabled, int, 0444);
How about just vcn_sw_ring as the parameter name?
> +
> static const struct pci_device_id pciidlist[] = {
> #ifdef CONFIG_DRM_AMDGPU_SI
> {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter
2020-11-12 14:23 ` [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter Alex Deucher
@ 2020-11-12 15:23 ` James Zhu
2020-11-12 18:57 ` Alex Deucher
0 siblings, 1 reply; 12+ messages in thread
From: James Zhu @ 2020-11-12 15:23 UTC (permalink / raw)
To: Alex Deucher, James Zhu; +Cc: amd-gfx list
On 2020-11-12 9:23 a.m., Alex Deucher wrote:
> On Wed, Nov 11, 2020 at 5:28 PM James Zhu <James.Zhu@amd.com> wrote:
>> This allows us to enable dec software ring feature on VCN.
>> The default is 0 for all asics, and it is only valid for
>> asics with vcn3.0 and above.
>>
>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>> Reviewed-by: Leo Liu <leo.liu@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++
>> 2 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 20400ec..cc47da6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -209,6 +209,7 @@ extern int amdgpu_si_support;
>> extern int amdgpu_cik_support;
>> #endif
>> extern int amdgpu_num_kcq;
>> +extern int amdgpu_dec_sw_ring_enabled;
>>
>> #define AMDGPU_VM_MAX_NUM_CTX 4096
>> #define AMDGPU_SG_THRESHOLD (256*1024*1024)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index 999f84d..570088f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
>> int amdgpu_tmz;
>> int amdgpu_reset_method = -1; /* auto */
>> int amdgpu_num_kcq = -1;
>> +int amdgpu_dec_sw_ring_enabled;
>>
>> struct amdgpu_mgpu_info mgpu_info = {
>> .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
>> @@ -806,6 +807,13 @@ module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
>> MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
>> module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
>>
>> +/**
>> + * DOC: dec_sw_ring_enabled (uint)
>> + * Override vcn decode software ring features enabled.
>> + */
>> +MODULE_PARM_DESC(dec_sw_ring_enabled, "vcn dec sw ring support (1 = enable, 0 = disable (default))");
>> +module_param_named(dec_sw_ring_enabled, amdgpu_dec_sw_ring_enabled, int, 0444);
> How about just vcn_sw_ring as the parameter name?
[JZ] It is for decode ring only. if just use vcn_sw_ring. I am not sure
if it will confuse people.
>
>> +
>> static const struct pci_device_id pciidlist[] = {
>> #ifdef CONFIG_DRM_AMDGPU_SI
>> {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CJames.Zhu%40amd.com%7C6a8168ed39b74d9a0a8f08d88716a006%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637407878530324835%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=egZMRoAdhY%2FRQAVENCT5CEVivi%2Fdzsn%2BUxPrnHJRKzU%3D&reserved=0
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter
2020-11-12 15:23 ` James Zhu
@ 2020-11-12 18:57 ` Alex Deucher
2020-11-12 19:14 ` James Zhu
0 siblings, 1 reply; 12+ messages in thread
From: Alex Deucher @ 2020-11-12 18:57 UTC (permalink / raw)
To: James Zhu; +Cc: James Zhu, amd-gfx list
On Thu, Nov 12, 2020 at 10:23 AM James Zhu <jamesz@amd.com> wrote:
>
>
> On 2020-11-12 9:23 a.m., Alex Deucher wrote:
> > On Wed, Nov 11, 2020 at 5:28 PM James Zhu <James.Zhu@amd.com> wrote:
> >> This allows us to enable dec software ring feature on VCN.
> >> The default is 0 for all asics, and it is only valid for
> >> asics with vcn3.0 and above.
> >>
> >> Signed-off-by: James Zhu <James.Zhu@amd.com>
> >> Reviewed-by: Leo Liu <leo.liu@amd.com>
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++
> >> 2 files changed, 9 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> index 20400ec..cc47da6 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> @@ -209,6 +209,7 @@ extern int amdgpu_si_support;
> >> extern int amdgpu_cik_support;
> >> #endif
> >> extern int amdgpu_num_kcq;
> >> +extern int amdgpu_dec_sw_ring_enabled;
> >>
> >> #define AMDGPU_VM_MAX_NUM_CTX 4096
> >> #define AMDGPU_SG_THRESHOLD (256*1024*1024)
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> index 999f84d..570088f 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> @@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
> >> int amdgpu_tmz;
> >> int amdgpu_reset_method = -1; /* auto */
> >> int amdgpu_num_kcq = -1;
> >> +int amdgpu_dec_sw_ring_enabled;
> >>
> >> struct amdgpu_mgpu_info mgpu_info = {
> >> .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
> >> @@ -806,6 +807,13 @@ module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
> >> MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
> >> module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
> >>
> >> +/**
> >> + * DOC: dec_sw_ring_enabled (uint)
> >> + * Override vcn decode software ring features enabled.
> >> + */
> >> +MODULE_PARM_DESC(dec_sw_ring_enabled, "vcn dec sw ring support (1 = enable, 0 = disable (default))");
> >> +module_param_named(dec_sw_ring_enabled, amdgpu_dec_sw_ring_enabled, int, 0444);
> > How about just vcn_sw_ring as the parameter name?
> [JZ] It is for decode ring only. if just use vcn_sw_ring. I am not sure
> if it will confuse people.
Are we intending to have a separate enable option for enc? If so, is
there value in that vs just having one knob for both?
Alex
> >
> >> +
> >> static const struct pci_device_id pciidlist[] = {
> >> #ifdef CONFIG_DRM_AMDGPU_SI
> >> {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
> >> --
> >> 2.7.4
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CJames.Zhu%40amd.com%7C6a8168ed39b74d9a0a8f08d88716a006%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637407878530324835%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=egZMRoAdhY%2FRQAVENCT5CEVivi%2Fdzsn%2BUxPrnHJRKzU%3D&reserved=0
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter
2020-11-12 18:57 ` Alex Deucher
@ 2020-11-12 19:14 ` James Zhu
0 siblings, 0 replies; 12+ messages in thread
From: James Zhu @ 2020-11-12 19:14 UTC (permalink / raw)
To: Alex Deucher; +Cc: James Zhu, amd-gfx list
On 2020-11-12 1:57 p.m., Alex Deucher wrote:
> On Thu, Nov 12, 2020 at 10:23 AM James Zhu <jamesz@amd.com> wrote:
>>
>> On 2020-11-12 9:23 a.m., Alex Deucher wrote:
>>> On Wed, Nov 11, 2020 at 5:28 PM James Zhu <James.Zhu@amd.com> wrote:
>>>> This allows us to enable dec software ring feature on VCN.
>>>> The default is 0 for all asics, and it is only valid for
>>>> asics with vcn3.0 and above.
>>>>
>>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>>> Reviewed-by: Leo Liu <leo.liu@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++
>>>> 2 files changed, 9 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> index 20400ec..cc47da6 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> @@ -209,6 +209,7 @@ extern int amdgpu_si_support;
>>>> extern int amdgpu_cik_support;
>>>> #endif
>>>> extern int amdgpu_num_kcq;
>>>> +extern int amdgpu_dec_sw_ring_enabled;
>>>>
>>>> #define AMDGPU_VM_MAX_NUM_CTX 4096
>>>> #define AMDGPU_SG_THRESHOLD (256*1024*1024)
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> index 999f84d..570088f 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> @@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
>>>> int amdgpu_tmz;
>>>> int amdgpu_reset_method = -1; /* auto */
>>>> int amdgpu_num_kcq = -1;
>>>> +int amdgpu_dec_sw_ring_enabled;
>>>>
>>>> struct amdgpu_mgpu_info mgpu_info = {
>>>> .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
>>>> @@ -806,6 +807,13 @@ module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
>>>> MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
>>>> module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
>>>>
>>>> +/**
>>>> + * DOC: dec_sw_ring_enabled (uint)
>>>> + * Override vcn decode software ring features enabled.
>>>> + */
>>>> +MODULE_PARM_DESC(dec_sw_ring_enabled, "vcn dec sw ring support (1 = enable, 0 = disable (default))");
>>>> +module_param_named(dec_sw_ring_enabled, amdgpu_dec_sw_ring_enabled, int, 0444);
>>> How about just vcn_sw_ring as the parameter name?
>> [JZ] It is for decode ring only. if just use vcn_sw_ring. I am not sure
>> if it will confuse people.
> Are we intending to have a separate enable option for enc? If so, is
> there value in that vs just having one knob for both?
[JZ] VCN ENC is using software ring from the beginning. So only
vcn3 dec supports both hardware ring and software ring.
>
> Alex
>
>
>>>> +
>>>> static const struct pci_device_id pciidlist[] = {
>>>> #ifdef CONFIG_DRM_AMDGPU_SI
>>>> {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
>>>> --
>>>> 2.7.4
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CJames.Zhu%40amd.com%7Cd5c7a6f7a7c64c60436b08d8873cc5ad%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637408042373143039%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=%2F7n0SEiVnX2z6AfuwQaUEqlFmLLrQKs7wBHJgagW0OU%3D&reserved=0
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter
2020-11-11 22:27 [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter James Zhu
` (4 preceding siblings ...)
2020-11-12 14:23 ` [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter Alex Deucher
@ 2020-11-16 11:38 ` Christian König
5 siblings, 0 replies; 12+ messages in thread
From: Christian König @ 2020-11-16 11:38 UTC (permalink / raw)
To: James Zhu, amd-gfx
Am 11.11.20 um 23:27 schrieb James Zhu:
> This allows us to enable dec software ring feature on VCN.
> The default is 0 for all asics, and it is only valid for
> asics with vcn3.0 and above.
Is that only supposed to be used for testing or do you really want to
upstream this?
A module parameter is always something the end user should be able to
change to get a certain result.
But if this is only used by a developer for testing then a define
somewhere in the code would be the more appropriate approach.
Christian.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> Reviewed-by: Leo Liu <leo.liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 20400ec..cc47da6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -209,6 +209,7 @@ extern int amdgpu_si_support;
> extern int amdgpu_cik_support;
> #endif
> extern int amdgpu_num_kcq;
> +extern int amdgpu_dec_sw_ring_enabled;
>
> #define AMDGPU_VM_MAX_NUM_CTX 4096
> #define AMDGPU_SG_THRESHOLD (256*1024*1024)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 999f84d..570088f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
> int amdgpu_tmz;
> int amdgpu_reset_method = -1; /* auto */
> int amdgpu_num_kcq = -1;
> +int amdgpu_dec_sw_ring_enabled;
>
> struct amdgpu_mgpu_info mgpu_info = {
> .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
> @@ -806,6 +807,13 @@ module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
> MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
> module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
>
> +/**
> + * DOC: dec_sw_ring_enabled (uint)
> + * Override vcn decode software ring features enabled.
> + */
> +MODULE_PARM_DESC(dec_sw_ring_enabled, "vcn dec sw ring support (1 = enable, 0 = disable (default))");
> +module_param_named(dec_sw_ring_enabled, amdgpu_dec_sw_ring_enabled, int, 0444);
> +
> static const struct pci_device_id pciidlist[] = {
> #ifdef CONFIG_DRM_AMDGPU_SI
> {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/5] drm/amdgpu/vcn: add test for dec vcn software ring
2020-11-11 22:27 ` [PATCH 3/5] drm/amdgpu/vcn: add test for " James Zhu
2020-11-12 1:00 ` [PATCH v2 " James Zhu
@ 2020-11-16 11:42 ` Christian König
1 sibling, 0 replies; 12+ messages in thread
From: Christian König @ 2020-11-16 11:42 UTC (permalink / raw)
To: James Zhu, amd-gfx
Am 11.11.20 um 23:27 schrieb James Zhu:
> Add vcn software ring decode ring test and decode ib test.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> Reviewed-by: Leo Liu <leo.liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 138 ++++++++++++++++++++++++++++++--
> 1 file changed, 132 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 7e19a66..e3d54fa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -456,6 +456,37 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
> return r;
> }
>
> +int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
> +{
> + struct amdgpu_device *adev = ring->adev;
> + uint32_t rptr;
> + unsigned int i;
> + int r;
> +
> + if (amdgpu_sriov_vf(adev))
> + return 0;
> +
> + r = amdgpu_ring_alloc(ring, 16);
> + if (r)
> + return r;
> +
> + rptr = amdgpu_ring_get_rptr(ring);
> +
> + amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
> + amdgpu_ring_commit(ring);
> +
> + for (i = 0; i < adev->usec_timeout; i++) {
> + if (amdgpu_ring_get_rptr(ring) != rptr)
> + break;
> + udelay(1);
> + }
> +
> + if (i >= adev->usec_timeout)
> + r = -ETIMEDOUT;
> +
> + return r;
> +}
> +
> static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
> struct amdgpu_bo *bo,
> struct dma_fence **fence)
> @@ -510,7 +541,10 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
> }
>
> static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
> - struct dma_fence **fence)
> + struct dma_fence **fence,
> + int (*send_msg)(struct amdgpu_ring *,
> + struct amdgpu_bo *,
> + struct dma_fence **))
> {
> struct amdgpu_device *adev = ring->adev;
> struct amdgpu_bo *bo = NULL;
> @@ -540,13 +574,17 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
> for (i = 14; i < 1024; ++i)
> msg[i] = cpu_to_le32(0x0);
>
> - return amdgpu_vcn_dec_send_msg(ring, bo, fence);
> + return send_msg(ring, bo, fence);
> }
>
> static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
> - struct dma_fence **fence)
> + struct dma_fence **fence,
> + int (*send_msg)(struct amdgpu_ring *,
> + struct amdgpu_bo *,
> + struct dma_fence **))
> {
> struct amdgpu_device *adev = ring->adev;
> + struct amdgpu_send_msg *dec;
> struct amdgpu_bo *bo = NULL;
> uint32_t *msg;
> int r, i;
> @@ -566,19 +604,107 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
> for (i = 6; i < 1024; ++i)
> msg[i] = cpu_to_le32(0x0);
>
> - return amdgpu_vcn_dec_send_msg(ring, bo, fence);
> + return send_msg(ring, bo, fence);
You can avoid the send_msg parameter altogether by just doing this in
the caller of the function.
Christian.
> }
>
> int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> + struct amdgpu_device *adev = ring->adev;
> struct dma_fence *fence;
> long r;
>
> - r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
> + r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL,
> + amdgpu_vcn_dec_send_msg);
> + if (r)
> + goto error;
> +
> + r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence,
> + amdgpu_vcn_dec_send_msg);
> + if (r)
> + goto error;
> +
> + r = dma_fence_wait_timeout(fence, false, timeout);
> + if (r == 0)
> + r = -ETIMEDOUT;
> + else if (r > 0)
> + r = 0;
> +
> + dma_fence_put(fence);
> +error:
> + return r;
> +}
> +
> +static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
> + struct amdgpu_bo *bo,
> + struct dma_fence **fence)
> +{
> + struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
> + const unsigned int ib_size_dw = 64;
> + struct amdgpu_device *adev = ring->adev;
> + struct dma_fence *f = NULL;
> + struct amdgpu_job *job;
> + struct amdgpu_ib *ib;
> + uint64_t addr;
> + int i, r;
> +
> + r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
> + AMDGPU_IB_POOL_DIRECT, &job);
> + if (r)
> + goto err;
> +
> + ib = &job->ibs[0];
> + addr = amdgpu_bo_gpu_offset(bo);
> + ib->length_dw = 0;
> +
> + ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
> + ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
> + decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
> + ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
> + memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
> +
> + decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
> + decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
> + decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
> +
> + for (i = ib->length_dw; i < ib_size_dw; ++i)
> + ib->ptr[i] = 0x0;
> +
> + r = amdgpu_job_submit_direct(job, ring, &f);
> + if (r)
> + goto err_free;
> +
> + amdgpu_bo_fence(bo, f, false);
> + amdgpu_bo_unreserve(bo);
> + amdgpu_bo_unref(&bo);
> +
> + if (fence)
> + *fence = dma_fence_get(f);
> + dma_fence_put(f);
> +
> + return 0;
> +
> +err_free:
> + amdgpu_job_free(job);
> +
> +err:
> + amdgpu_bo_unreserve(bo);
> + amdgpu_bo_unref(&bo);
> + return r;
> +}
> +
> +int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> +{
> + struct amdgpu_device *adev = ring->adev;
> + struct dma_fence *fence = NULL;
> + long r;
> +
> + r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL,
> + amdgpu_vcn_dec_sw_send_msg);
> if (r)
> goto error;
>
> - r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
> + r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence,
> + amdgpu_vcn_dec_sw_send_msg);
> if (r)
> goto error;
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-11-13 15:42 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-11 22:27 [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter James Zhu
2020-11-11 22:27 ` [PATCH 2/5] drm/amdgpu/vcn: update header to support dec vcn software ring James Zhu
2020-11-11 22:27 ` [PATCH 3/5] drm/amdgpu/vcn: add test for " James Zhu
2020-11-12 1:00 ` [PATCH v2 " James Zhu
2020-11-16 11:42 ` [PATCH " Christian König
2020-11-11 22:27 ` [PATCH 4/5] drm/amdgpu/vcn3.0: add dec software ring vm functions to support James Zhu
2020-11-11 22:27 ` [PATCH 5/5] drm/amdgpu/vcn3.0: add software ring share memory support James Zhu
2020-11-12 14:23 ` [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter Alex Deucher
2020-11-12 15:23 ` James Zhu
2020-11-12 18:57 ` Alex Deucher
2020-11-12 19:14 ` James Zhu
2020-11-16 11:38 ` Christian König
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