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From: Sebastian von Ohr <vonohr@smaract.com>
To: Radhey Shyam Pandey <radheys@xilinx.com>,
	Vinod Koul <vkoul@kernel.org>,
	Appana Durga Kedareswara Rao <appanad@xilinx.com>,
	Michal Simek <michals@xilinx.com>
Cc: "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>
Subject: RE: [PATCH] dmaengine: xilinx_dma: Add missing check for empty list
Date: Wed, 8 Apr 2020 07:12:03 +0000	[thread overview]
Message-ID: <c0883a291b5940b6b1ecb14b072ffc15@smaract.com> (raw)
In-Reply-To: <BYAPR02MB5638F1A9A1B68C0FA534E07DC7C30@BYAPR02MB5638.namprd02.prod.outlook.com>

> -----Original Message-----
> From: Radhey Shyam Pandey [mailto:radheys@xilinx.com]
> Sent: Tuesday, April 7, 2020 6:04 PM
> To: Sebastian von Ohr <vonohr@smaract.com>; Vinod Koul
> <vkoul@kernel.org>; Appana Durga Kedareswara Rao
> <appanad@xilinx.com>; Michal Simek <michals@xilinx.com>
> Cc: dmaengine@vger.kernel.org
> Subject: RE: [PATCH] dmaengine: xilinx_dma: Add missing check for empty
> list
> 
> Thanks for reminding me. Somehow I missed it. You mentioned in one
> of earlier thread that this bug is introduced it using dma_sync_wait to
> wait for DMA completion. So to reproduce the issue in xilinx axidma
> test client I have to replace issue_pending with sync_wait API?

Yes, dma_sync_wait triggered the bug for me almost every transfer. In the 
xilinx axidmatest this is probably best achieved by adding dma_sync_wait 
before the wait_for_completion_timeout. I encountered the bug with your 
xilinx-v2019.2.01 tag. On this tag it actually crashes the kernel with an 
invalid memory access (because the residue is written to desc). With the 
current driver version it probably seems to work fine. You might have to 
add some debug print to verify that the active_list can indeed be empty in 
xilinx_dma_tx_status.

  reply	other threads:[~2020-04-08  7:12 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-03 13:05 [PATCH] dmaengine: xilinx_dma: Add missing check for empty list Sebastian von Ohr
2020-03-06 13:34 ` Vinod Koul
2020-03-06 13:57   ` Radhey Shyam Pandey
2020-03-11  9:16     ` Vinod Koul
2020-04-07  7:52     ` Sebastian von Ohr
2020-04-07 16:03       ` Radhey Shyam Pandey
2020-04-08  7:12         ` Sebastian von Ohr [this message]
2020-04-08 14:06           ` Radhey Shyam Pandey
2020-04-08 15:19             ` Sebastian von Ohr
2020-04-09  7:40               ` Radhey Shyam Pandey
2020-04-15 16:12 ` Vinod Koul

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