From: "Jiaxun Yang" <jiaxun.yang@flygoat.com> To: "Huacai Chen" <chenhuacai@loongson.cn>, "Arnd Bergmann" <arnd@arndb.de>, "Andy Lutomirski" <luto@kernel.org>, "Thomas Gleixner" <tglx@linutronix.de>, "Peter Zijlstra" <peterz@infradead.org>, "Andrew Morton" <akpm@linux-foundation.org>, "David Airlie" <airlied@linux.ie>, "Jonathan Corbet" <corbet@lwn.net>, "Linus Torvalds" <torvalds@linux-foundation.org> Cc: linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, "Xuefeng Li" <lixuefeng@loongson.cn>, "Yanteng Si" <siyanteng@loongson.cn>, "Huacai Chen" <chenhuacai@gmail.com>, "Guo Ren" <guoren@kernel.org>, "Xuerui Wang" <kernel@xen0n.name>, "Stephen Rothwell" <sfr@canb.auug.org.au>, "Daniel Vetter" <daniel@ffwll.ch>, dri-devel@lists.freedesktop.org, "WANG Xuerui" <git@xen0n.name> Subject: Re: [PATCH V12 06/24] LoongArch: Add writecombine support for drm Date: Wed, 01 Jun 2022 13:20:28 +0100 [thread overview] Message-ID: <c2c7d0cd-c708-4efe-9fff-7d84fc274735@www.fastmail.com> (raw) In-Reply-To: <20220601100005.2989022-7-chenhuacai@loongson.cn> 在2022年6月1日六月 上午10:59,Huacai Chen写道: > LoongArch maintains cache coherency in hardware, but its WUC attribute > (Weak-ordered UnCached, which is similar to WC) is out of the scope of > cache coherency machanism. This means WUC can only used for write-only > memory regions. > > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: dri-devel@lists.freedesktop.org > Reviewed-by: WANG Xuerui <git@xen0n.name> > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Can still remember painful experiences on poke with WC on LS3B1500 + Polaris. Glad to see that WC is flawless this time. Thanks. > --- > drivers/gpu/drm/drm_vm.c | 2 +- > drivers/gpu/drm/ttm/ttm_module.c | 2 +- > include/drm/drm_cache.h | 8 ++++++++ > 3 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c > index e957d4851dc0..f024dc93939e 100644 > --- a/drivers/gpu/drm/drm_vm.c > +++ b/drivers/gpu/drm/drm_vm.c > @@ -69,7 +69,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map, > pgprot_t tmp = vm_get_page_prot(vma->vm_flags); > > #if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) > || \ > - defined(__mips__) > + defined(__mips__) || defined(__loongarch__) > if (map->type == _DRM_REGISTERS && !(map->flags & > _DRM_WRITE_COMBINING)) > tmp = pgprot_noncached(tmp); > else > diff --git a/drivers/gpu/drm/ttm/ttm_module.c > b/drivers/gpu/drm/ttm/ttm_module.c > index a3ad7c9736ec..b3fffe7b5062 100644 > --- a/drivers/gpu/drm/ttm/ttm_module.c > +++ b/drivers/gpu/drm/ttm/ttm_module.c > @@ -74,7 +74,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching > caching, pgprot_t tmp) > #endif /* CONFIG_UML */ > #endif /* __i386__ || __x86_64__ */ > #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \ > - defined(__powerpc__) || defined(__mips__) > + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) > if (caching == ttm_write_combined) > tmp = pgprot_writecombine(tmp); > else > diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h > index 22deb216b59c..08e0e3ffad13 100644 > --- a/include/drm/drm_cache.h > +++ b/include/drm/drm_cache.h > @@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void) > * optimization entirely for ARM and arm64. > */ > return false; > +#elif defined(CONFIG_LOONGARCH) > + /* > + * LoongArch maintains cache coherency in hardware, but its WUC > attribute > + * (Weak-ordered UnCached, which is similar to WC) is out of the > scope of > + * cache coherency machanism. This means WUC can only used for > write-only > + * memory regions. > + */ > + return false; > #else > return true; > #endif > -- > 2.27.0 -- - Jiaxun
WARNING: multiple messages have this Message-ID (diff)
From: "Jiaxun Yang" <jiaxun.yang@flygoat.com> To: "Huacai Chen" <chenhuacai@loongson.cn>, "Arnd Bergmann" <arnd@arndb.de>, "Andy Lutomirski" <luto@kernel.org>, "Thomas Gleixner" <tglx@linutronix.de>, "Peter Zijlstra" <peterz@infradead.org>, "Andrew Morton" <akpm@linux-foundation.org>, "David Airlie" <airlied@linux.ie>, "Jonathan Corbet" <corbet@lwn.net>, "Linus Torvalds" <torvalds@linux-foundation.org> Cc: linux-arch@vger.kernel.org, Stephen Rothwell <sfr@canb.auug.org.au>, Yanteng Si <siyanteng@loongson.cn>, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Guo Ren <guoren@kernel.org>, WANG Xuerui <git@xen0n.name>, Xuerui Wang <kernel@xen0n.name>, Xuefeng Li <lixuefeng@loongson.cn> Subject: Re: [PATCH V12 06/24] LoongArch: Add writecombine support for drm Date: Wed, 01 Jun 2022 13:20:28 +0100 [thread overview] Message-ID: <c2c7d0cd-c708-4efe-9fff-7d84fc274735@www.fastmail.com> (raw) In-Reply-To: <20220601100005.2989022-7-chenhuacai@loongson.cn> 在2022年6月1日六月 上午10:59,Huacai Chen写道: > LoongArch maintains cache coherency in hardware, but its WUC attribute > (Weak-ordered UnCached, which is similar to WC) is out of the scope of > cache coherency machanism. This means WUC can only used for write-only > memory regions. > > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: dri-devel@lists.freedesktop.org > Reviewed-by: WANG Xuerui <git@xen0n.name> > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Can still remember painful experiences on poke with WC on LS3B1500 + Polaris. Glad to see that WC is flawless this time. Thanks. > --- > drivers/gpu/drm/drm_vm.c | 2 +- > drivers/gpu/drm/ttm/ttm_module.c | 2 +- > include/drm/drm_cache.h | 8 ++++++++ > 3 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c > index e957d4851dc0..f024dc93939e 100644 > --- a/drivers/gpu/drm/drm_vm.c > +++ b/drivers/gpu/drm/drm_vm.c > @@ -69,7 +69,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map, > pgprot_t tmp = vm_get_page_prot(vma->vm_flags); > > #if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) > || \ > - defined(__mips__) > + defined(__mips__) || defined(__loongarch__) > if (map->type == _DRM_REGISTERS && !(map->flags & > _DRM_WRITE_COMBINING)) > tmp = pgprot_noncached(tmp); > else > diff --git a/drivers/gpu/drm/ttm/ttm_module.c > b/drivers/gpu/drm/ttm/ttm_module.c > index a3ad7c9736ec..b3fffe7b5062 100644 > --- a/drivers/gpu/drm/ttm/ttm_module.c > +++ b/drivers/gpu/drm/ttm/ttm_module.c > @@ -74,7 +74,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching > caching, pgprot_t tmp) > #endif /* CONFIG_UML */ > #endif /* __i386__ || __x86_64__ */ > #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \ > - defined(__powerpc__) || defined(__mips__) > + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) > if (caching == ttm_write_combined) > tmp = pgprot_writecombine(tmp); > else > diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h > index 22deb216b59c..08e0e3ffad13 100644 > --- a/include/drm/drm_cache.h > +++ b/include/drm/drm_cache.h > @@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void) > * optimization entirely for ARM and arm64. > */ > return false; > +#elif defined(CONFIG_LOONGARCH) > + /* > + * LoongArch maintains cache coherency in hardware, but its WUC > attribute > + * (Weak-ordered UnCached, which is similar to WC) is out of the > scope of > + * cache coherency machanism. This means WUC can only used for > write-only > + * memory regions. > + */ > + return false; > #else > return true; > #endif > -- > 2.27.0 -- - Jiaxun
next prev parent reply other threads:[~2022-06-01 12:21 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-01 9:59 [PATCH V12 00/24] arch: Add basic LoongArch support Huacai Chen 2022-06-01 9:59 ` [PATCH V12 01/24] irqchip: Adjust Kconfig for Loongson Huacai Chen 2022-06-01 10:36 ` WANG Xuerui 2022-06-01 9:59 ` [PATCH V12 02/24] irqchip/loongson-liointc: Fix build error for LoongArch Huacai Chen 2022-06-01 10:37 ` WANG Xuerui 2022-06-01 12:09 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 03/24] Documentation: LoongArch: Add basic documentations Huacai Chen 2022-06-01 12:16 ` Jiaxun Yang 2022-06-02 9:13 ` Bagas Sanjaya 2022-06-02 9:26 ` Huacai Chen 2022-06-01 9:59 ` [PATCH V12 04/24] Documentation/zh_CN: Add basic LoongArch documentations Huacai Chen 2022-06-01 12:17 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 05/24] LoongArch: Add ELF-related definitions Huacai Chen 2022-06-01 12:18 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 06/24] LoongArch: Add writecombine support for drm Huacai Chen 2022-06-01 9:59 ` Huacai Chen 2022-06-01 12:20 ` Jiaxun Yang [this message] 2022-06-01 12:20 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 07/24] LoongArch: Add build infrastructure Huacai Chen 2022-06-01 12:23 ` Jiaxun Yang 2022-06-01 15:47 ` Randy Dunlap 2022-06-01 16:02 ` Arnd Bergmann 2022-06-01 9:59 ` [PATCH V12 08/24] LoongArch: Add CPU definition headers Huacai Chen 2022-06-01 12:25 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 09/24] LoongArch: Add atomic/locking headers Huacai Chen 2022-06-01 12:27 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 10/24] LoongArch: Add other common headers Huacai Chen 2022-06-01 12:27 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 11/24] LoongArch: Add boot and setup routines Huacai Chen 2022-06-01 12:29 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 12/24] LoongArch: Add exception/interrupt handling Huacai Chen 2022-06-01 12:29 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 13/24] LoongArch: Add process management Huacai Chen 2022-06-01 9:59 ` [PATCH V12 14/24] LoongArch: Add memory management Huacai Chen 2022-06-01 9:59 ` [PATCH V12 15/24] LoongArch: Add system call support Huacai Chen 2022-06-01 12:30 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 16/24] LoongArch: Add signal handling support Huacai Chen 2022-06-01 9:59 ` [PATCH V12 17/24] LoongArch: Add ELF and module support Huacai Chen 2022-06-01 12:30 ` Jiaxun Yang 2022-06-01 9:59 ` [PATCH V12 18/24] LoongArch: Add misc common routines Huacai Chen 2022-06-01 12:31 ` Jiaxun Yang 2022-06-01 10:00 ` [PATCH V12 19/24] LoongArch: Add some library functions Huacai Chen 2022-06-01 12:33 ` Jiaxun Yang 2022-06-01 10:00 ` [PATCH V12 20/24] LoongArch: Add VDSO and VSYSCALL support Huacai Chen 2022-06-01 10:00 ` [PATCH V12 21/24] LoongArch: Add multi-processor (SMP) support Huacai Chen 2022-06-01 12:34 ` Jiaxun Yang 2022-06-01 10:00 ` [PATCH V12 22/24] LoongArch: Add Non-Uniform Memory Access (NUMA) support Huacai Chen 2022-06-01 11:27 ` WANG Xuerui 2022-06-01 10:00 ` [PATCH V12 23/24] LoongArch: Add Loongson-3 default config file Huacai Chen 2022-06-01 10:00 ` [PATCH V12 24/24] MAINTAINERS: Add maintainer information for LoongArch Huacai Chen 2022-06-01 12:35 ` Jiaxun Yang 2022-06-01 14:56 ` Guo Ren 2022-06-01 11:30 ` [PATCH V12 00/24] arch: Add basic LoongArch support WANG Xuerui 2022-06-01 12:44 ` Jiaxun Yang 2022-06-01 15:02 ` Guo Ren
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