From: Matthias Brugger <matthias.bgg@gmail.com>
To: Hanks Chen <hanks.chen@mediatek.com>,
Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Sean Wang <sean.wang@kernel.org>
Cc: mtk01761 <wendell.lin@mediatek.com>,
Andy Teng <andy.teng@mediatek.com>,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
wsd_upstream@mediatek.com, CC Hwang <cc.hwang@mediatek.com>,
Loda Chou <loda.chou@mediatek.com>
Subject: Re: [PATCH v7 6/7] clk: mediatek: add UART0 clock support
Date: Fri, 10 Jul 2020 15:41:01 +0200 [thread overview]
Message-ID: <c40d2739-92a1-3309-764a-ed3ac8ee7bc6@gmail.com> (raw)
In-Reply-To: <1593694630-26604-8-git-send-email-hanks.chen@mediatek.com>
On 02/07/2020 14:57, Hanks Chen wrote:
> Add MT6779 UART0 clock support.
>
> Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/clk/mediatek/clk-mt6779.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> index 9766ccc..6e0d3a1 100644
> --- a/drivers/clk/mediatek/clk-mt6779.c
> +++ b/drivers/clk/mediatek/clk-mt6779.c
> @@ -919,6 +919,8 @@
> "pwm_sel", 19),
> GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> "pwm_sel", 21),
> + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> + "uart_sel", 22),
> GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> "uart_sel", 23),
> GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
>
WARNING: multiple messages have this Message-ID (diff)
From: Matthias Brugger <matthias.bgg@gmail.com>
To: Hanks Chen <hanks.chen@mediatek.com>,
Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Sean Wang <sean.wang@kernel.org>
Cc: devicetree@vger.kernel.org, CC Hwang <cc.hwang@mediatek.com>,
wsd_upstream@mediatek.com, Andy Teng <andy.teng@mediatek.com>,
Loda Chou <loda.chou@mediatek.com>,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-mediatek@lists.infradead.org,
mtk01761 <wendell.lin@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 6/7] clk: mediatek: add UART0 clock support
Date: Fri, 10 Jul 2020 15:41:01 +0200 [thread overview]
Message-ID: <c40d2739-92a1-3309-764a-ed3ac8ee7bc6@gmail.com> (raw)
In-Reply-To: <1593694630-26604-8-git-send-email-hanks.chen@mediatek.com>
On 02/07/2020 14:57, Hanks Chen wrote:
> Add MT6779 UART0 clock support.
>
> Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/clk/mediatek/clk-mt6779.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> index 9766ccc..6e0d3a1 100644
> --- a/drivers/clk/mediatek/clk-mt6779.c
> +++ b/drivers/clk/mediatek/clk-mt6779.c
> @@ -919,6 +919,8 @@
> "pwm_sel", 19),
> GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> "pwm_sel", 21),
> + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> + "uart_sel", 22),
> GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> "uart_sel", 23),
> GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Matthias Brugger <matthias.bgg@gmail.com>
To: Hanks Chen <hanks.chen@mediatek.com>,
Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Sean Wang <sean.wang@kernel.org>
Cc: devicetree@vger.kernel.org, CC Hwang <cc.hwang@mediatek.com>,
wsd_upstream@mediatek.com, Andy Teng <andy.teng@mediatek.com>,
Loda Chou <loda.chou@mediatek.com>,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-mediatek@lists.infradead.org,
mtk01761 <wendell.lin@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 6/7] clk: mediatek: add UART0 clock support
Date: Fri, 10 Jul 2020 15:41:01 +0200 [thread overview]
Message-ID: <c40d2739-92a1-3309-764a-ed3ac8ee7bc6@gmail.com> (raw)
In-Reply-To: <1593694630-26604-8-git-send-email-hanks.chen@mediatek.com>
On 02/07/2020 14:57, Hanks Chen wrote:
> Add MT6779 UART0 clock support.
>
> Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/clk/mediatek/clk-mt6779.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> index 9766ccc..6e0d3a1 100644
> --- a/drivers/clk/mediatek/clk-mt6779.c
> +++ b/drivers/clk/mediatek/clk-mt6779.c
> @@ -919,6 +919,8 @@
> "pwm_sel", 19),
> GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> "pwm_sel", 21),
> + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> + "uart_sel", 22),
> GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> "uart_sel", 23),
> GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-10 13:41 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 12:57 [PATCH v7] Add basic SoC Support for Mediatek MT6779 SoC Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` [PATCH v7 0/7] " Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-07 11:25 ` Hanks Chen
2020-07-07 11:25 ` Hanks Chen
2020-07-07 11:25 ` Hanks Chen
2020-07-02 12:57 ` [PATCH v7 1/7] pinctrl: mediatek: update pinmux definitions for mt6779 Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` [PATCH v7 2/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 20:58 ` Rob Herring
2020-07-02 20:58 ` Rob Herring
2020-07-02 20:58 ` Rob Herring
2020-07-07 11:05 ` Hanks Chen
2020-07-07 11:05 ` Hanks Chen
2020-07-07 11:05 ` Hanks Chen
2020-07-02 12:57 ` [PATCH v7 3/7] pinctrl: mediatek: avoid virtual gpio trying to set reg Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` [PATCH v7 4/7] pinctrl: mediatek: add pinctrl support for MT6779 SoC Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` [PATCH v7 5/7] pinctrl: mediatek: add mt6779 eint support Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` [PATCH v7 6/7] clk: mediatek: add UART0 clock support Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-10 13:41 ` Matthias Brugger [this message]
2020-07-10 13:41 ` Matthias Brugger
2020-07-10 13:41 ` Matthias Brugger
2020-07-02 12:57 ` [PATCH v7 7/7] arm64: dts: add dts nodes for MT6779 Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-02 12:57 ` Hanks Chen
2020-07-10 13:47 ` Matthias Brugger
2020-07-10 13:47 ` Matthias Brugger
2020-07-10 13:47 ` Matthias Brugger
2020-07-13 11:11 ` Hanks Chen
2020-07-13 11:11 ` Hanks Chen
2020-07-13 11:11 ` Hanks Chen
2020-07-07 11:41 ` [PATCH v7] Add basic SoC Support for Mediatek MT6779 SoC Linus Walleij
2020-07-07 11:41 ` Linus Walleij
2020-07-07 11:41 ` Linus Walleij
2020-07-07 11:51 ` Hanks Chen
2020-07-07 11:51 ` Hanks Chen
2020-07-07 11:51 ` Hanks Chen
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