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From: <Tudor.Ambarus@microchip.com>
To: <p.yadav@ti.com>, <chentsung@chromium.org>
Cc: <michael@walle.cc>, <miquel.raynal@bootlin.com>, <richard@nod.at>,
	<vigneshr@ti.com>, <linux-kernel@vger.kernel.org>,
	<linux-mtd@lists.infradead.org>
Subject: Re: [RESEND PATCH] mtd: spi-nor: core: Check written SR value in spi_nor_write_16bit_sr_and_check()
Date: Wed, 27 Apr 2022 07:14:09 +0000	[thread overview]
Message-ID: <c6b2956d-85f6-19c3-4282-23a72a1b5849@microchip.com> (raw)
In-Reply-To: <0e02112a-317c-e95b-e0d3-7ed2c74c3509@microchip.com>

On 4/27/22 10:11, Tudor Ambarus wrote:
> On 1/31/22 19:19, Pratyush Yadav wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 26/01/22 03:32PM, Chen-Tsung Hsieh wrote:
>>> Read back Status Register 1 to ensure that the written byte match the
>>> received value and return -EIO if read back test failed.
>>>
>>> Without this patch, spi_nor_write_16bit_sr_and_check() only check the
>>> second half of the 16bit. It causes errors like spi_nor_sr_unlock()
>>> return success incorrectly when spi_nor_write_16bit_sr_and_check()
>>> doesn't write SR successfully.
>>>

cc to stable please

>>> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()")
>>> Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
>>
>> I don't know much about this bit of code but this patch looks fine to me
>> from the surface. Would be nice to hear from Tudor about this too since
>> he added the function.
> 
> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>>
>> Acked-by: Pratyush Yadav <p.yadav@ti.com>


WARNING: multiple messages have this Message-ID (diff)
From: <Tudor.Ambarus@microchip.com>
To: <p.yadav@ti.com>, <chentsung@chromium.org>
Cc: <michael@walle.cc>, <miquel.raynal@bootlin.com>, <richard@nod.at>,
	<vigneshr@ti.com>, <linux-kernel@vger.kernel.org>,
	<linux-mtd@lists.infradead.org>
Subject: Re: [RESEND PATCH] mtd: spi-nor: core: Check written SR value in spi_nor_write_16bit_sr_and_check()
Date: Wed, 27 Apr 2022 07:14:09 +0000	[thread overview]
Message-ID: <c6b2956d-85f6-19c3-4282-23a72a1b5849@microchip.com> (raw)
In-Reply-To: <0e02112a-317c-e95b-e0d3-7ed2c74c3509@microchip.com>

On 4/27/22 10:11, Tudor Ambarus wrote:
> On 1/31/22 19:19, Pratyush Yadav wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 26/01/22 03:32PM, Chen-Tsung Hsieh wrote:
>>> Read back Status Register 1 to ensure that the written byte match the
>>> received value and return -EIO if read back test failed.
>>>
>>> Without this patch, spi_nor_write_16bit_sr_and_check() only check the
>>> second half of the 16bit. It causes errors like spi_nor_sr_unlock()
>>> return success incorrectly when spi_nor_write_16bit_sr_and_check()
>>> doesn't write SR successfully.
>>>

cc to stable please

>>> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()")
>>> Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
>>
>> I don't know much about this bit of code but this patch looks fine to me
>> from the surface. Would be nice to hear from Tudor about this too since
>> he added the function.
> 
> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>>
>> Acked-by: Pratyush Yadav <p.yadav@ti.com>

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  reply	other threads:[~2022-04-27  7:14 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-26  7:32 [RESEND PATCH] mtd: spi-nor: core: Check written SR value in spi_nor_write_16bit_sr_and_check() Chen-Tsung Hsieh
2022-01-26  7:32 ` Chen-Tsung Hsieh
2022-01-26 22:38 ` Michael Walle
2022-01-26 22:38   ` Michael Walle
2022-01-27  3:31   ` Chen-Tsung Hsieh
2022-01-27  3:31     ` Chen-Tsung Hsieh
2022-01-27  9:18     ` Michael Walle
2022-01-27  9:18       ` Michael Walle
2022-01-27 18:27       ` Chen-Tsung Hsieh
2022-01-27 18:27         ` Chen-Tsung Hsieh
2022-01-31 17:19 ` Pratyush Yadav
2022-01-31 17:19   ` Pratyush Yadav
2022-04-27  7:11   ` Tudor.Ambarus
2022-04-27  7:11     ` Tudor.Ambarus
2022-04-27  7:14     ` Tudor.Ambarus [this message]
2022-04-27  7:14       ` Tudor.Ambarus
2022-04-27  8:59       ` Pratyush Yadav
2022-04-27  8:59         ` Pratyush Yadav
2022-04-27 10:51         ` Tudor.Ambarus
2022-04-27 10:51           ` Tudor.Ambarus
2022-04-27  9:31 ` Pratyush Yadav
2022-04-27  9:31   ` Pratyush Yadav

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