From: BALATON Zoltan <balaton@eik.bme.hu>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: clg@kaod.org, Daniel Henrique Barboza <danielhb413@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v4 11/21] ppc440_sdram: Get rid of the init RAM hack
Date: Wed, 14 Sep 2022 13:34:24 +0200 (CEST) [thread overview]
Message-ID: <cd7fae004b752f235bcecaae6892793f86cd7d21.1663154398.git.balaton@eik.bme.hu> (raw)
In-Reply-To: <cover.1663154398.git.balaton@eik.bme.hu>
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board via DCR access instead. Firmware does this
so it may not be needed when booting firmware only with -kernel but we
enable it unconditionally to preserve previous behaviour.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440.h | 3 +--
hw/ppc/ppc440_uc.c | 8 ++------
hw/ppc/sam460ex.c | 8 +++++++-
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index e6c905b7d6..01d76b8000 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -17,8 +17,7 @@ void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks,
- int do_init);
+ Ppc4xxSdramBank *ram_banks);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index aa09534abb..9d011ae0cb 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -727,12 +727,11 @@ static void sdram_reset(void *opaque)
ppc440_sdram_t *sdram = opaque;
sdram->addr = 0;
- sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN;
+ sdram->mcopt2 = 0;
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks,
- int do_init)
+ Ppc4xxSdramBank *ram_banks)
{
ppc440_sdram_t *sdram;
int i;
@@ -749,9 +748,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
- if (do_init) {
- sdram_map_bcr(sdram);
- }
ppc_dcr_register(env, SDRAM_R0BAS,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index f4c2a693fb..dac329d482 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -345,7 +345,13 @@ static void sam460ex_init(MachineState *machine)
ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, 1, ram_banks, 1);
+ ppc440_sdram_init(env, 1, ram_banks);
+ /* Enable SDRAM memory regions as we may boot without firmware */
+ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) ||
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000)) {
+ error_report("Couldn't enable memory regions");
+ exit(1);
+ }
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
--
2.30.4
next prev parent reply other threads:[~2022-09-14 12:06 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 11:34 [PATCH v4 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 01/21] ppc440_bamboo: Remove unnecessary memsets BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 02/21] ppc4xx: Introduce Ppc4xxSdramBank struct BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 03/21] ppc4xx_sdram: Get rid of the init RAM hack BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 04/21] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 05/21] ppc440_bamboo: Add missing 4 MiB valid memory size BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 06/21] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() BALATON Zoltan
2022-09-17 21:54 ` Philippe Mathieu-Daudé via
2022-09-14 11:34 ` [PATCH v4 07/21] ppc4xx_sdram: QOM'ify BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 08/21] ppc4xx_sdram: Drop extra zeros for readability BALATON Zoltan
2022-09-17 22:12 ` Philippe Mathieu-Daudé via
2022-09-14 11:34 ` [PATCH v4 09/21] ppc440_sdram: Split off map/unmap of sdram banks for later reuse BALATON Zoltan
2022-09-17 22:14 ` Philippe Mathieu-Daudé via
2022-09-14 11:34 ` [PATCH v4 10/21] ppc440_sdram: Implement enable bit in the DDR2 SDRAM BALATON Zoltan
2022-09-14 11:34 ` BALATON Zoltan [this message]
2022-09-14 11:34 ` [PATCH v4 12/21] ppc440_sdram: Rename local variable for readability BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 13/21] ppc4xx_sdram: Rename functions to prevent name clashes BALATON Zoltan
2022-09-17 22:15 ` Philippe Mathieu-Daudé via
2022-09-14 11:34 ` [PATCH v4 14/21] ppc440_sdram: Move RAM size check to ppc440_sdram_init BALATON Zoltan
2022-09-17 22:16 ` Philippe Mathieu-Daudé via
2022-09-18 9:59 ` BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 15/21] ppc440_sdram: QOM'ify BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 17/21] ppc4xx_sdram: Use hwaddr for memory bank size BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 18/21] ppc4xx_sdram: Rename local state variable for brevity BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 19/21] ppc4xx_sdram: Generalise bank setup BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 20/21] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks() BALATON Zoltan
2022-09-17 22:18 ` Philippe Mathieu-Daudé via
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cd7fae004b752f235bcecaae6892793f86cd7d21.1663154398.git.balaton@eik.bme.hu \
--to=balaton@eik.bme.hu \
--cc=clg@kaod.org \
--cc=danielhb413@gmail.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.