CIP-dev Archive on lore.kernel.org
 help / color / Atom feed
From: "Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file
Date: Mon, 12 Oct 2020 15:19:21 +0100
Message-ID: <20201012141933.9652-39-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20201012141933.9652-1-prabhakar.mahadev-lad.rj@bp.renesas.com>


[-- Attachment #1: Type: text/plain, Size: 8269 bytes --]

commit 78a0d7f2f5a31357bce68012d886507b4cf33598 upstream.

Move shareable code to common file pcie-rcar.c and the #defines to
pcie-rcar.h so that the common code can be reused with endpoint driver.
There are no functional changes with this patch for the host controller
driver.

Link: https://lore.kernel.org/r/1588854799-13710-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[PL: Dropped changes to pcie-rcar-host.c as it doesnt apply cleanly and
manually applying the changes would result in huge change]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/pcie-rcar.c | 117 ++++++++++++++++++++++++++
 drivers/pci/controller/pcie-rcar.h | 131 +++++++++++++++++++++++++++++
 2 files changed, 248 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-rcar.c
 create mode 100644 drivers/pci/controller/pcie-rcar.h

diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
new file mode 100644
index 000000000000..cf8840d180c3
--- /dev/null
+++ b/drivers/pci/controller/pcie-rcar.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe driver for Renesas R-Car SoCs
+ *  Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
+ *
+ * Author: Phil Edworthy <phil.edworthy@renesas.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/pci.h>
+
+#include "pcie-rcar.h"
+
+void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg)
+{
+	writel(val, pcie->base + reg);
+}
+
+u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg)
+{
+	return readl(pcie->base + reg);
+}
+
+void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
+{
+	unsigned int shift = BITS_PER_BYTE * (where & 3);
+	u32 val = rcar_pci_read_reg(pcie, where & ~3);
+
+	val &= ~(mask << shift);
+	val |= data << shift;
+	rcar_pci_write_reg(pcie, val, where & ~3);
+}
+
+int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
+{
+	unsigned int timeout = 10;
+
+	while (timeout--) {
+		if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
+			return 0;
+
+		msleep(5);
+	}
+
+	return -ETIMEDOUT;
+}
+
+int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
+{
+	unsigned int timeout = 10000;
+
+	while (timeout--) {
+		if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
+			return 0;
+
+		udelay(5);
+		cpu_relax();
+	}
+
+	return -ETIMEDOUT;
+}
+
+void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
+			    struct resource_entry *window)
+{
+	/* Setup PCIe address space mappings for each resource */
+	struct resource *res = window->res;
+	resource_size_t res_start;
+	resource_size_t size;
+	u32 mask;
+
+	rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
+
+	/*
+	 * The PAMR mask is calculated in units of 128Bytes, which
+	 * keeps things pretty simple.
+	 */
+	size = resource_size(res);
+	mask = (roundup_pow_of_two(size) / SZ_128) - 1;
+	rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
+
+	if (res->flags & IORESOURCE_IO)
+		res_start = pci_pio_to_address(res->start) - window->offset;
+	else
+		res_start = res->start - window->offset;
+
+	rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
+	rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
+			   PCIEPALR(win));
+
+	/* First resource is for IO */
+	mask = PAR_ENABLE;
+	if (res->flags & IORESOURCE_IO)
+		mask |= IO_SPACE;
+
+	rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
+}
+
+void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
+			   u64 pci_addr, u64 flags, int idx, bool host)
+{
+	/*
+	 * Set up 64-bit inbound regions as the range parser doesn't
+	 * distinguish between 32 and 64-bit types.
+	 */
+	if (host)
+		rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
+				   PCIEPRAR(idx));
+	rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
+	rcar_pci_write_reg(pcie, flags, PCIELAMR(idx));
+
+	if (host)
+		rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
+				   PCIEPRAR(idx + 1));
+	rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx + 1));
+	rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
+}
diff --git a/drivers/pci/controller/pcie-rcar.h b/drivers/pci/controller/pcie-rcar.h
new file mode 100644
index 000000000000..97640e16af58
--- /dev/null
+++ b/drivers/pci/controller/pcie-rcar.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PCIe driver for Renesas R-Car SoCs
+ *  Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
+ *
+ * Author: Phil Edworthy <phil.edworthy@renesas.com>
+ */
+
+#ifndef _PCIE_RCAR_H
+#define _PCIE_RCAR_H
+
+#define PCIECAR			0x000010
+#define PCIECCTLR		0x000018
+#define  CONFIG_SEND_ENABLE	BIT(31)
+#define  TYPE0			(0 << 8)
+#define  TYPE1			BIT(8)
+#define PCIECDR			0x000020
+#define PCIEMSR			0x000028
+#define PCIEINTXR		0x000400
+#define PCIEPHYSR		0x0007f0
+#define  PHYRDY			BIT(0)
+#define PCIEMSITXR		0x000840
+
+/* Transfer control */
+#define PCIETCTLR		0x02000
+#define  DL_DOWN		BIT(3)
+#define  CFINIT			BIT(0)
+#define PCIETSTR		0x02004
+#define  DATA_LINK_ACTIVE	BIT(0)
+#define PCIEERRFR		0x02020
+#define  UNSUPPORTED_REQUEST	BIT(4)
+#define PCIEMSIFR		0x02044
+#define PCIEMSIALR		0x02048
+#define  MSIFE			BIT(0)
+#define PCIEMSIAUR		0x0204c
+#define PCIEMSIIER		0x02050
+
+/* root port address */
+#define PCIEPRAR(x)		(0x02080 + ((x) * 0x4))
+
+/* local address reg & mask */
+#define PCIELAR(x)		(0x02200 + ((x) * 0x20))
+#define PCIELAMR(x)		(0x02208 + ((x) * 0x20))
+#define  LAM_PREFETCH		BIT(3)
+#define  LAM_64BIT		BIT(2)
+#define  LAR_ENABLE		BIT(1)
+
+/* PCIe address reg & mask */
+#define PCIEPALR(x)		(0x03400 + ((x) * 0x20))
+#define PCIEPAUR(x)		(0x03404 + ((x) * 0x20))
+#define PCIEPAMR(x)		(0x03408 + ((x) * 0x20))
+#define PCIEPTCTLR(x)		(0x0340c + ((x) * 0x20))
+#define  PAR_ENABLE		BIT(31)
+#define  IO_SPACE		BIT(8)
+
+/* Configuration */
+#define PCICONF(x)		(0x010000 + ((x) * 0x4))
+#define PMCAP(x)		(0x010040 + ((x) * 0x4))
+#define EXPCAP(x)		(0x010070 + ((x) * 0x4))
+#define VCCAP(x)		(0x010100 + ((x) * 0x4))
+
+/* link layer */
+#define IDSETR1			0x011004
+#define TLCTLR			0x011048
+#define MACSR			0x011054
+#define  SPCHGFIN		BIT(4)
+#define  SPCHGFAIL		BIT(6)
+#define  SPCHGSUC		BIT(7)
+#define  LINK_SPEED		(0xf << 16)
+#define  LINK_SPEED_2_5GTS	(1 << 16)
+#define  LINK_SPEED_5_0GTS	(2 << 16)
+#define MACCTLR			0x011058
+#define  MACCTLR_NFTS_MASK	GENMASK(23, 16)	/* The name is from SH7786 */
+#define  SPEED_CHANGE		BIT(24)
+#define  SCRAMBLE_DISABLE	BIT(27)
+#define  LTSMDIS		BIT(31)
+#define  MACCTLR_INIT_VAL	(LTSMDIS | MACCTLR_NFTS_MASK)
+#define PMSR			0x01105c
+#define MACS2R			0x011078
+#define MACCGSPSETR		0x011084
+#define  SPCNGRSN		BIT(31)
+
+/* R-Car H1 PHY */
+#define H1_PCIEPHYADRR		0x04000c
+#define  WRITE_CMD		BIT(16)
+#define  PHY_ACK		BIT(24)
+#define  RATE_POS		12
+#define  LANE_POS		8
+#define  ADR_POS		0
+#define H1_PCIEPHYDOUTR		0x040014
+
+/* R-Car Gen2 PHY */
+#define GEN2_PCIEPHYADDR	0x780
+#define GEN2_PCIEPHYDATA	0x784
+#define GEN2_PCIEPHYCTRL	0x78c
+
+#define INT_PCI_MSI_NR		32
+
+#define RCONF(x)		(PCICONF(0) + (x))
+#define RPMCAP(x)		(PMCAP(0) + (x))
+#define REXPCAP(x)		(EXPCAP(0) + (x))
+#define RVCCAP(x)		(VCCAP(0) + (x))
+
+#define PCIE_CONF_BUS(b)	(((b) & 0xff) << 24)
+#define PCIE_CONF_DEV(d)	(((d) & 0x1f) << 19)
+#define PCIE_CONF_FUNC(f)	(((f) & 0x7) << 16)
+
+#define RCAR_PCI_MAX_RESOURCES	4
+#define MAX_NR_INBOUND_MAPS	6
+
+struct rcar_pcie {
+	struct device		*dev;
+	void __iomem		*base;
+};
+
+enum {
+	RCAR_PCI_ACCESS_READ,
+	RCAR_PCI_ACCESS_WRITE,
+};
+
+void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg);
+u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg);
+void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data);
+int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie);
+int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie);
+void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
+			    struct resource_entry *window);
+void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
+			   u64 pci_addr, u64 flags, int idx, bool host);
+
+#endif
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#5558): https://lists.cip-project.org/g/cip-dev/message/5558
Mute This Topic: https://lists.cip-project.org/mt/77461717/4520388
Group Owner: cip-dev+owner@lists.cip-project.org
Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/8129055/727948398/xyzzy [cip-dev@archiver.kernel.org]
-=-=-=-=-=-=-=-=-=-=-=-


  parent reply index

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 01/50] PCI: endpoint: Add new pci_epc_ops to get EPC features Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 02/50] PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 03/50] PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 04/50] PCI: pci-dra7xx: " Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 05/50] PCI: rockchip: " Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 06/50] PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 07/50] PCI: endpoint: Add helper to get first unreserved BAR Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 08/50] PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 09/50] PCI: pci-epf-test: Remove setting epf_bar flags in function driver Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 10/50] PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 11/50] PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 12/50] PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 13/50] PCI: rockchip: Remove pci_epf_linkup() from Rockchip " Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 14/50] PCI: designware-plat: Remove setting epc->features in Designware plat " Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 15/50] PCI: endpoint: Remove features member in struct pci_epc Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 16/50] PCI: endpoint: Fix a potential NULL pointer dereference Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 17/50] PCI: endpoint: Add support to specify alignment for buffers allocated to BARs Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 18/50] PCI: endpoint: Set endpoint controller pointer to NULL Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 19/50] PCI: endpoint: Allocate enough space for fixed size BAR Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 20/50] PCI: endpoint: Skip odd BAR when skipping 64bit BAR Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 21/50] PCI: endpoint: Clear BAR before freeing its space Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 22/50] PCI: endpoint: Cast the page number to phys_addr_t Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 23/50] PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex Lad Prabhakar
2020-10-20 20:43   ` Pavel Machek
2020-10-20 21:56     ` Lad Prabhakar
2020-10-21 18:34       ` Pavel Machek
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 25/50] PCI: endpoint: Protect concurrent access to pci_epf_ops " Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 26/50] PCI: endpoint: Assign function number for each PF in EPC core Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 27/50] PCI: endpoint: Add core init notifying feature Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 28/50] PCI: endpoint: Add notification for core init completion Lad Prabhakar
2020-10-21 19:00   ` Pavel Machek
2020-10-21 20:16     ` Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 29/50] PCI: pci-epf-test: Add support to defer core initialization Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 30/50] PCI: endpoint: Fix clearing start entry in configfs Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 31/50] PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 32/50] PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 33/50] PCI: endpoint: Pass page size as argument to pci_epc_mem_init() Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 34/50] PCI: endpoint: Add support to handle multiple base for mapping outbound memory Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 35/50] PCI: endpoint: functions/pci-epf-test: Print throughput information Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 36/50] PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 37/50] arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST Lad Prabhakar
2020-10-12 14:19 ` Lad Prabhakar [this message]
2020-10-21 19:06   ` [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file Pavel Machek
2020-10-21 20:28     ` Lad Prabhakar
2020-10-22 19:42       ` Pavel Machek
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 39/50] PCI: rcar: Fix calculating mask for PCIEPAMR register Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 40/50] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support Lad Prabhakar
2020-10-14  9:22   ` Pavel Machek
2020-10-15 16:31     ` Lad Prabhakar
2020-10-15 18:01       ` Pavel Machek
2020-10-22 18:23         ` Pavel Machek
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 42/50] arm64: defconfig: Enable R-Car PCIe endpoint driver Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 43/50] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1 Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 44/50] arm64: dts: renesas: r8a774c0: Add PCIe EP node Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 45/50] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 46/50] arm64: dts: renesas: r8a774b1: " Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 47/50] misc: pci_endpoint_test: Add Device ID for RZ/G2E PCIe controller Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 48/50] misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 49/50] tools: PCI: Exit with error code when test fails Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 50/50] tools: PCI: Fix fd leakage Lad Prabhakar
2020-10-14  9:39 ` [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Pavel Machek
2020-10-15 16:18   ` Lad Prabhakar
2020-10-20  7:16   ` Lad Prabhakar
2020-10-20 10:34     ` Pavel Machek
2020-10-20 12:01     ` Pavel Machek
2020-10-20 13:01       ` Lad Prabhakar
2020-10-20 20:48         ` Pavel Machek
2020-10-20 21:58           ` Lad Prabhakar
2020-10-14 10:07 ` [cip-dev] " Pavel Machek
2020-10-15 16:27   ` Lad Prabhakar

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201012141933.9652-39-prabhakar.mahadev-lad.rj@bp.renesas.com \
    --to=prabhakar.mahadev-lad.rj@bp.renesas.com \
    --cc=biju.das.jz@bp.renesas.com \
    --cc=cip-dev@lists.cip-project.org \
    --cc=nobuhiro1.iwamatsu@toshiba.co.jp \
    --cc=pavel@denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

CIP-dev Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/cip-dev/0 cip-dev/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 cip-dev cip-dev/ https://lore.kernel.org/cip-dev \
		cip-dev@lists.cip-project.org
	public-inbox-index cip-dev

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.cip-project.lists.cip-dev


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git