* [cip-dev] [PATCH 4.4.y-cip 01/11] base: soc: Early register bus when needed
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 02/11] dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema Lad Prabhakar
` (10 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1551 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 1da1b3628df34a2a5e38b70c8551770aadce969d upstream.
If soc_device_register() is called before soc_bus_register(), it crashes
with a NULL pointer dereference.
soc_bus_register() is already a core_initcall(), but drivers/base/ is
entered later than e.g. drivers/pinctrl/ and drivers/soc/. Hence there
are several subsystems that may need to know SoC revision information,
while it's not so easy to initialize the SoC bus even earlier using an
initcall.
To fix this, let soc_device_register() register the bus early if that
hasn't happened yet.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/base/soc.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/base/soc.c b/drivers/base/soc.c
index 84242e6b2897..c9fd0ee2ba50 100644
--- a/drivers/base/soc.c
+++ b/drivers/base/soc.c
@@ -114,6 +114,12 @@ struct soc_device *soc_device_register(struct soc_device_attribute *soc_dev_attr
struct soc_device *soc_dev;
int ret;
+ if (!soc_bus_type.p) {
+ ret = bus_register(&soc_bus_type);
+ if (ret)
+ goto out1;
+ }
+
soc_dev = kzalloc(sizeof(*soc_dev), GFP_KERNEL);
if (!soc_dev) {
ret = -ENOMEM;
@@ -159,6 +165,9 @@ EXPORT_SYMBOL_GPL(soc_device_unregister);
static int __init soc_bus_register(void)
{
+ if (soc_bus_type.p)
+ return 0;
+
return bus_register(&soc_bus_type);
}
core_initcall(soc_bus_register);
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 02/11] dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 01/11] base: soc: Early register bus when needed Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 03/11] soc: renesas: Identify SoC and register with the SoC bus Lad Prabhakar
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 2223 bytes --]
From: Simon Horman <horms+renesas@verge.net.au>
commit 09f156d97e530c2ac631620f7b29508ff5cc4e6f upstream.
Convert Renesas Product Register bindings documentation to json-schema.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20190908120528.9392-1-horms+renesas@verge.net.au
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Initially in upstream commit 5384f45cd9714287f198771bfb057eda799af9a8
("ARM: shmobile: Document DT bindings for Product Register" added DT
documentation later this was moved into separate file (renesas,prr.txt) in
commit 74791d15fd7c405511e3cc097c2f043171ecbdb0 ("dt-bindings: arm:
renesas: Move 'renesas,prr' binding to its own doc") and finally this was
converted into json-schema so using the same commit to backport]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/arm/renesas,prr.yaml | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.yaml
diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
new file mode 100644
index 000000000000..1f80767da38b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/renesas,prr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Product Register
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+ Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
+ Register that allows to retrieve SoC product and revision information.
+ If present, a device node for this register should be added.
+
+properties:
+ compatible:
+ enum:
+ - renesas,prr
+ - renesas,bsid
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0xff000044 4>;
+ };
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 03/11] soc: renesas: Identify SoC and register with the SoC bus
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 01/11] base: soc: Early register bus when needed Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 02/11] dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 04/11] ARM: dts: r8a7743: Add device node for PRR Lad Prabhakar
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 5671 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 8d6799a9ba23acd675f3243580ee6f1756fb4381 upstream.
Identify the SoC type and revision, and register this information with
the SoC bus, so it is available under /sys/devices/soc0/, and can be
checked where needed using soc_device_match().
Identification is done using the Product Register or Common Chip Code
Register, as declared in DT (PRR only for now), or using a hardcoded
fallback if missing.
Example:
Detected Renesas R-Car Gen2 r8a7791 ES1.0
...
# cat /sys/devices/soc0/{machine,family,soc_id,revision}
Koelsch
R-Car Gen2
r8a7791
ES1.0
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[PL: Dropped references to other platforms apart from RZ/G1{ME},
dropped SOC_BUS config option from arm64, enabled SOC_BUS config
option for ARCH_R8A7743 and ARCH_R8A7745]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 2 +
drivers/soc/renesas/Makefile | 2 +
drivers/soc/renesas/renesas-soc.c | 123 ++++++++++++++++++++++++++++++
3 files changed, 127 insertions(+)
create mode 100644 drivers/soc/renesas/renesas-soc.c
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index a51df53f0914..3f1e27b76d59 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -72,6 +72,7 @@ config ARCH_R8A7742
config ARCH_R8A7743
bool "RZ/G1M (R8A77430)"
select ARCH_RCAR_GEN2
+ select SOC_BUS
config ARCH_R8A7744
bool "RZ/G1N (R8A77440)"
@@ -81,6 +82,7 @@ config ARCH_R8A7744
config ARCH_R8A7745
bool "RZ/G1E (R8A77450)"
select ARCH_RCAR_GEN2
+ select SOC_BUS
config ARCH_R8A77470
bool "RZ/G1C (R8A77470)"
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 87517569af13..77e8f953f4c8 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -1 +1,3 @@
obj-$(CONFIG_ARCH_RCAR_GEN2) += rcar-rst.o
+
+obj-$(CONFIG_SOC_BUS) += renesas-soc.o
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
new file mode 100644
index 000000000000..e36b51a52dfc
--- /dev/null
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -0,0 +1,123 @@
+/*
+ * Renesas SoC Identification
+ *
+ * Copyright (C) 2014-2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sys_soc.h>
+
+struct renesas_family {
+ const char name[16];
+ u32 reg; /* CCCR or PRR, if not in DT */
+};
+
+static const struct renesas_family fam_rzg __initconst __maybe_unused = {
+ .name = "RZ/G",
+ .reg = 0xff000044, /* PRR (Product Register) */
+};
+
+struct renesas_soc {
+ const struct renesas_family *family;
+ u8 id;
+};
+
+static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x47,
+};
+
+static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x4c,
+};
+
+static const struct of_device_id renesas_socs[] __initconst = {
+#ifdef CONFIG_ARCH_R8A7743
+ { .compatible = "renesas,r8a7743", .data = &soc_rz_g1m },
+#endif
+#ifdef CONFIG_ARCH_R8A7745
+ { .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
+#endif
+ { /* sentinel */ }
+};
+
+static int __init renesas_soc_init(void)
+{
+ struct soc_device_attribute *soc_dev_attr;
+ const struct renesas_family *family;
+ const struct of_device_id *match;
+ const struct renesas_soc *soc;
+ void __iomem *chipid = NULL;
+ struct soc_device *soc_dev;
+ struct device_node *np;
+ unsigned int product;
+
+ match = of_match_node(renesas_socs, of_root);
+ if (!match)
+ return -ENODEV;
+
+ soc = match->data;
+ family = soc->family;
+
+ /* Try PRR first, then hardcoded fallback */
+ np = of_find_compatible_node(NULL, NULL, "renesas,prr");
+ if (np) {
+ chipid = of_iomap(np, 0);
+ of_node_put(np);
+ } else if (soc->id) {
+ chipid = ioremap(family->reg, 4);
+ }
+ if (chipid) {
+ product = readl(chipid);
+ iounmap(chipid);
+ if (soc->id && ((product >> 8) & 0xff) != soc->id) {
+ pr_warn("SoC mismatch (product = 0x%x)\n", product);
+ return -ENODEV;
+ }
+ }
+
+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ return -ENOMEM;
+
+ np = of_find_node_by_path("/");
+ of_property_read_string(np, "model", &soc_dev_attr->machine);
+ of_node_put(np);
+
+ soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL);
+ soc_dev_attr->soc_id = kstrdup_const(strchr(match->compatible, ',') + 1,
+ GFP_KERNEL);
+ if (chipid)
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u",
+ ((product >> 4) & 0x0f) + 1,
+ product & 0xf);
+
+ pr_info("Detected Renesas %s %s %s\n", soc_dev_attr->family,
+ soc_dev_attr->soc_id, soc_dev_attr->revision ?: "");
+
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR(soc_dev)) {
+ kfree(soc_dev_attr->revision);
+ kfree_const(soc_dev_attr->soc_id);
+ kfree_const(soc_dev_attr->family);
+ kfree(soc_dev_attr);
+ return PTR_ERR(soc_dev);
+ }
+
+ return 0;
+}
+core_initcall(renesas_soc_init);
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 04/11] ARM: dts: r8a7743: Add device node for PRR
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
` (2 preceding siblings ...)
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 03/11] soc: renesas: Identify SoC and register with the SoC bus Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 05/11] ARM: dts: r8a7745: " Lad Prabhakar
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 956 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 11d4407e939e74e89a29df88b1557b59ece9e9f9 upstream.
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[PL: sorted the node]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7743.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index aff5ebbdb4bd..73b8f7f341f4 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1781,6 +1781,11 @@
status = "disabled";
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7743",
"renesas,cmt-48-gen2";
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 05/11] ARM: dts: r8a7745: Add device node for PRR
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
` (3 preceding siblings ...)
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 04/11] ARM: dts: r8a7743: Add device node for PRR Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 06/11] soc: renesas: Identify RZ/G1N Lad Prabhakar
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 953 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 8916c7b58319fa27eae25c0c9b9a4cd68b9b30bd upstream.
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[PL: sorted the node as per address]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 5f603d9eafea..58bf2e52523e 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -1356,6 +1356,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7745",
"renesas,cmt-48-gen2";
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 06/11] soc: renesas: Identify RZ/G1N
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
` (4 preceding siblings ...)
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 05/11] ARM: dts: r8a7745: " Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR Lad Prabhakar
` (5 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1829 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit cd59de80dd34dd2d1a3ca97d7a6e712c048b135a upstream.
Add support for identifying the RZ/G1N (r8a7744) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[PL: Enabled SOC_BUS config for RZ/G1N]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/soc/renesas/renesas-soc.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 3f1e27b76d59..8b84eb630dee 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -78,6 +78,7 @@ config ARCH_R8A7744
bool "RZ/G1N (R8A77440)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
+ select SOC_BUS
config ARCH_R8A7745
bool "RZ/G1E (R8A77450)"
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index e36b51a52dfc..2cf62855cc45 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -40,6 +40,11 @@ static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
.id = 0x47,
};
+static const struct renesas_soc soc_rz_g1n __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x4b,
+};
+
static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
.family = &fam_rzg,
.id = 0x4c,
@@ -49,6 +54,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A7743
{ .compatible = "renesas,r8a7743", .data = &soc_rz_g1m },
#endif
+#ifdef CONFIG_ARCH_R8A7744
+ { .compatible = "renesas,r8a7744", .data = &soc_rz_g1n },
+#endif
#ifdef CONFIG_ARCH_R8A7745
{ .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
#endif
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
` (5 preceding siblings ...)
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 06/11] soc: renesas: Identify RZ/G1N Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-12-01 0:51 ` Nobuhiro Iwamatsu
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 08/11] soc: renesas: Identify RZ/G1H Lad Prabhakar
` (4 subsequent siblings)
11 siblings, 1 reply; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 835 bytes --]
Add a device node for the Product Register, which provides SoC product
and revision information.
Changes are already present in upstream but the PRR node is part of
initial SoC DTSI and cannot be individually backported hence this
new commit.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7744.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 079f46f17049..312c9aae8a10 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1526,6 +1526,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7744",
"renesas,cmt-48-gen2";
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 420 bytes --]
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [cip-dev] [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR Lad Prabhakar
@ 2020-12-01 0:51 ` Nobuhiro Iwamatsu
2020-12-01 7:50 ` Lad Prabhakar
0 siblings, 1 reply; 15+ messages in thread
From: Nobuhiro Iwamatsu @ 2020-12-01 0:51 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, cip-dev, pavel; +Cc: biju.das.jz
[-- Attachment #1: Type: text/plain, Size: 1703 bytes --]
Hi,
> -----Original Message-----
> From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
> Sent: Monday, November 30, 2020 11:19 PM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR
>
> Add a device node for the Product Register, which provides SoC product
> and revision information.
>
> Changes are already present in upstream but the PRR node is part of
> initial SoC DTSI and cannot be individually backported hence this
> new commit.
I thought it would be good to include the relevant commit ID.
For example, this should be included as 6929dfc5918049272e07653b1760b0b305f098e6,
but has been removed by 605e89568fafe57c1791219b411ab0771981beea.
If you accept this suggestion, please add the same comment to other similar patches.
Best regards,
Nobuhiro
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> arch/arm/boot/dts/r8a7744.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
> index 079f46f17049..312c9aae8a10 100644
> --- a/arch/arm/boot/dts/r8a7744.dtsi
> +++ b/arch/arm/boot/dts/r8a7744.dtsi
> @@ -1526,6 +1526,11 @@
> };
> };
>
> + prr: chipid@ff000044 {
> + compatible = "renesas,prr";
> + reg = <0 0xff000044 0 4>;
> + };
> +
> cmt0: timer@ffca0000 {
> compatible = "renesas,cmt-48-r8a7744",
> "renesas,cmt-48-gen2";
> --
> 2.17.1
[-- Attachment #2: Type: text/plain, Size: 420 bytes --]
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [cip-dev] [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR
2020-12-01 0:51 ` Nobuhiro Iwamatsu
@ 2020-12-01 7:50 ` Lad Prabhakar
0 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-12-01 7:50 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, cip-dev, pavel; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 2311 bytes --]
Hi Nobuhiro,
Thank you for the review.
> -----Original Message-----
> From: nobuhiro1.iwamatsu@toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
> Sent: 01 December 2020 00:52
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org;
> pavel@denx.de
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: RE: [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR
>
> Hi,
>
> > -----Original Message-----
> > From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
> > Sent: Monday, November 30, 2020 11:19 PM
> > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> > <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
> > Cc: Biju Das <biju.das.jz@bp.renesas.com>
> > Subject: [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR
> >
> > Add a device node for the Product Register, which provides SoC product
> > and revision information.
> >
> > Changes are already present in upstream but the PRR node is part of
> > initial SoC DTSI and cannot be individually backported hence this
> > new commit.
>
> I thought it would be good to include the relevant commit ID.
> For example, this should be included as 6929dfc5918049272e07653b1760b0b305f098e6,
> but has been removed by 605e89568fafe57c1791219b411ab0771981beea.
>
> If you accept this suggestion, please add the same comment to other similar patches.
>
Agreed I will update the commit message and repost.
Cheers,
Prabhakar
> Best regards,
> Nobuhiro
>
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > arch/arm/boot/dts/r8a7744.dtsi | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
> > index 079f46f17049..312c9aae8a10 100644
> > --- a/arch/arm/boot/dts/r8a7744.dtsi
> > +++ b/arch/arm/boot/dts/r8a7744.dtsi
> > @@ -1526,6 +1526,11 @@
> > };
> > };
> >
> > + prr: chipid@ff000044 {
> > + compatible = "renesas,prr";
> > + reg = <0 0xff000044 0 4>;
> > + };
> > +
> > cmt0: timer@ffca0000 {
> > compatible = "renesas,cmt-48-r8a7744",
> > "renesas,cmt-48-gen2";
> > --
> > 2.17.1
[-- Attachment #2: Type: text/plain, Size: 420 bytes --]
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [cip-dev] [PATCH 4.4.y-cip 08/11] soc: renesas: Identify RZ/G1H
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
` (6 preceding siblings ...)
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 09/11] ARM: dts: r8a7742: Add device node for PRR Lad Prabhakar
` (3 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1786 bytes --]
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 8848e1b14231a40ed66229fb3ee98519b32f2ae7 upstream.
Add support for identifying the RZ/G1H (r8a7742) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[PL: manually applied the changes, enabled SOC_BUS config for RZ/G1N]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/soc/renesas/renesas-soc.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 8b84eb630dee..6812b3e19ba3 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -68,6 +68,7 @@ config ARCH_R8A7742
bool "RZ/G1H (R8A77420)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
+ select SOC_BUS
config ARCH_R8A7743
bool "RZ/G1M (R8A77430)"
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 2cf62855cc45..eaa540bfc9bd 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -35,6 +35,11 @@ struct renesas_soc {
u8 id;
};
+static const struct renesas_soc soc_rz_g1h __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x45,
+};
+
static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
.family = &fam_rzg,
.id = 0x47,
@@ -51,6 +56,9 @@ static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
};
static const struct of_device_id renesas_socs[] __initconst = {
+#ifdef CONFIG_ARCH_R8A7742
+ { .compatible = "renesas,r8a7742", .data = &soc_rz_g1h },
+#endif
#ifdef CONFIG_ARCH_R8A7743
{ .compatible = "renesas,r8a7743", .data = &soc_rz_g1m },
#endif
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 420 bytes --]
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 09/11] ARM: dts: r8a7742: Add device node for PRR
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
` (7 preceding siblings ...)
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 08/11] soc: renesas: Identify RZ/G1H Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 10/11] soc: renesas: Identify RZ/G1C Lad Prabhakar
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 852 bytes --]
Add a device node for the Product Register, which provides SoC product
and revision information.
Changes are already present in upstream but the PRR node is part of
initial SoC DTSI and cannot be individually backported hence this
new commit.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 0da46a2edddd..2ad6f965ccbd 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -1927,6 +1927,11 @@
renesas,#wpf = <4>;
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7742",
"renesas,cmt-48-gen2";
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 420 bytes --]
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 10/11] soc: renesas: Identify RZ/G1C
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
` (8 preceding siblings ...)
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 09/11] ARM: dts: r8a7742: Add device node for PRR Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 11/11] ARM: dts: r8a77470: Add device node for PRR Lad Prabhakar
2020-12-01 0:59 ` [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Nobuhiro Iwamatsu
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1962 bytes --]
From: Biju Das <biju.das@bp.renesas.com>
commit 1daf13ba10378cad9ea4f5f26b83dd36c36dcdc0 upstream.
Add support for identifying the RZ/G1C (r8a77470) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[PL: manually applied the changes, replaced fam_rzg1 to fam_rzg,
enabled SOC_BUS config for RZ/G1C]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/soc/renesas/renesas-soc.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 6812b3e19ba3..017d03d3e4e5 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -89,6 +89,7 @@ config ARCH_R8A7745
config ARCH_R8A77470
bool "RZ/G1C (R8A77470)"
select ARCH_RCAR_GEN2
+ select SOC_BUS
config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index eaa540bfc9bd..a267c7637003 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -55,6 +55,11 @@ static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
.id = 0x4c,
};
+static const struct renesas_soc soc_rz_g1c __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x53,
+};
+
static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A7742
{ .compatible = "renesas,r8a7742", .data = &soc_rz_g1h },
@@ -67,6 +72,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#endif
#ifdef CONFIG_ARCH_R8A7745
{ .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
+#endif
+#ifdef CONFIG_ARCH_R8A77470
+ { .compatible = "renesas,r8a77470", .data = &soc_rz_g1c },
#endif
{ /* sentinel */ }
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [cip-dev] [PATCH 4.4.y-cip 11/11] ARM: dts: r8a77470: Add device node for PRR
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
` (9 preceding siblings ...)
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 10/11] soc: renesas: Identify RZ/G1C Lad Prabhakar
@ 2020-11-30 14:19 ` Lad Prabhakar
2020-12-01 0:59 ` [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Nobuhiro Iwamatsu
11 siblings, 0 replies; 15+ messages in thread
From: Lad Prabhakar @ 2020-11-30 14:19 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 867 bytes --]
Add a device node for the Product Register, which provides SoC product
and revision information.
Changes are already present in upstream but the PRR node is part of
initial SoC DTSI and cannot be individually backported hence this
new commit.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a77470.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 1057bff76cc8..3bf1a458593b 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -715,6 +715,11 @@
power-domains = <&cpg_clocks>;
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a77470",
"renesas,cmt-48-gen2";
--
2.17.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support
2020-11-30 14:19 [cip-dev] [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support Lad Prabhakar
` (10 preceding siblings ...)
2020-11-30 14:19 ` [cip-dev] [PATCH 4.4.y-cip 11/11] ARM: dts: r8a77470: Add device node for PRR Lad Prabhakar
@ 2020-12-01 0:59 ` Nobuhiro Iwamatsu
11 siblings, 0 replies; 15+ messages in thread
From: Nobuhiro Iwamatsu @ 2020-12-01 0:59 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, cip-dev, pavel; +Cc: biju.das.jz
[-- Attachment #1: Type: text/plain, Size: 2198 bytes --]
Hi,
> -----Original Message-----
> From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
> Sent: Monday, November 30, 2020 11:19 PM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support
>
> Hi All,
>
> This patch series adds SoC detection support for Renesas RZ/G1x SoC's.
>
> All the patches apart from {7, 9, 11}/11 have been cherry picked from
> Linux v5.10-rc6
>
> Cheers,
> Prabhakar
>
> Biju Das (1):
> soc: renesas: Identify RZ/G1C
>
> Geert Uytterhoeven (6):
> base: soc: Early register bus when needed
> soc: renesas: Identify SoC and register with the SoC bus
> ARM: dts: r8a7743: Add device node for PRR
> ARM: dts: r8a7745: Add device node for PRR
> soc: renesas: Identify RZ/G1N
> soc: renesas: Identify RZ/G1H
>
> Lad Prabhakar (3):
> ARM: dts: r8a7744: Add device node for PRR
> ARM: dts: r8a7742: Add device node for PRR
> ARM: dts: r8a77470: Add device node for PRR
>
> Simon Horman (1):
> dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema
>
> .../devicetree/bindings/arm/renesas,prr.yaml | 37 +++++
> arch/arm/boot/dts/r8a7742.dtsi | 5 +
> arch/arm/boot/dts/r8a7743.dtsi | 5 +
> arch/arm/boot/dts/r8a7744.dtsi | 5 +
> arch/arm/boot/dts/r8a7745.dtsi | 5 +
> arch/arm/boot/dts/r8a77470.dtsi | 5 +
> arch/arm/mach-shmobile/Kconfig | 5 +
> drivers/base/soc.c | 9 ++
> drivers/soc/renesas/Makefile | 2 +
> drivers/soc/renesas/renesas-soc.c | 147 ++++++++++++++++++
> 10 files changed, 225 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.yaml
> create mode 100644 drivers/soc/renesas/renesas-soc.c
>
I reviewed this patch series, there is not issue.
I can apply and push if there is no objection.
Best regards,
Nobuhiro
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^ permalink raw reply [flat|nested] 15+ messages in thread