From: "Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [cip-dev] [PATCH 4.19.y-cip 4/8] pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0
Date: Tue, 5 Jan 2021 15:10:53 +0000 [thread overview]
Message-ID: <20210105151057.12752-5-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20210105151057.12752-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
[-- Attachment #1: Type: text/plain, Size: 3317 bytes --]
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 03522a59a9e7e5f464735e907891cd235aa68b1d upstream.
This driver supports both RZ/G2E and R-Car E3 SoCs.
Optimize pinctrl image size for RZ/G2E, when support for R-Car E3
(R8A77990) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 2dfb8d9cfda1..18049e1c49a6 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1590,6 +1590,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -1782,6 +1783,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
@@ -3758,7 +3760,9 @@ static const unsigned int vin5_clk_b_mux[] = {
static const struct {
struct sh_pfc_pin_group common[247];
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
struct sh_pfc_pin_group automotive[21];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
@@ -4009,6 +4013,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clk_a),
SH_PFC_PIN_GROUP(vin5_clk_b),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4032,6 +4037,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
};
static const char * const audio_clk_groups[] = {
@@ -4085,6 +4091,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4117,6 +4124,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
static const char * const du_groups[] = {
"du_rgb666",
@@ -4457,7 +4465,9 @@ static const char * const vin5_groups[] = {
static const struct {
struct sh_pfc_function common[47];
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
struct sh_pfc_function automotive[4];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -4508,12 +4518,14 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
2.17.1
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next prev parent reply other threads:[~2021-01-05 15:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-05 15:10 [cip-dev] [PATCH 4.19.y-cip 0/8] Optimize pinctrl and add QSPI[01] pins for RZ/G2{H,M,N,E} Lad Prabhakar
2021-01-05 15:10 ` [cip-dev] [PATCH 4.19.y-cip 1/8] pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1 Lad Prabhakar
2021-01-05 15:10 ` [cip-dev] [PATCH 4.19.y-cip 2/8] pinctrl: renesas: r8a77951: Optimize pinctrl image size for R8A774E1 Lad Prabhakar
2021-01-05 15:10 ` [cip-dev] [PATCH 4.19.y-cip 3/8] pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1 Lad Prabhakar
2021-01-05 15:10 ` Lad Prabhakar [this message]
2021-01-05 15:10 ` [cip-dev] [PATCH 4.19.y-cip 5/8] pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions Lad Prabhakar
2021-01-05 15:10 ` [cip-dev] [PATCH 4.19.y-cip 6/8] pinctrl: renesas: r8a77951: " Lad Prabhakar
2021-01-05 15:10 ` [cip-dev] [PATCH 4.19.y-cip 7/8] pinctrl: renesas: r8a7796: " Lad Prabhakar
2021-01-05 15:10 ` [cip-dev] [PATCH 4.19.y-cip 8/8] pinctrl: renesas: r8a77965: " Lad Prabhakar
2021-01-05 16:38 ` [cip-dev] [PATCH 4.19.y-cip 0/8] Optimize pinctrl and add QSPI[01] pins for RZ/G2{H,M,N,E} Pavel Machek
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