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From: Felix Moessbauer <felix.moessbauer@siemens.com>
To: cip-dev@lists.cip-project.org
Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com,
	quirin.gylstorff@siemens.com,
	Felix Moessbauer <felix.moessbauer@siemens.com>
Subject: [isar-cip-core][PATCH v4 2/8] fix efibootguard for riscv64
Date: Fri,  3 Mar 2023 12:48:14 +0000	[thread overview]
Message-ID: <20230303124820.2209954-3-felix.moessbauer@siemens.com> (raw)
In-Reply-To: <20230303124820.2209954-1-felix.moessbauer@siemens.com>

This commit backports an upstream patch for efibootguard that
fixes the riscv64 install location. As it is not yet in an
EBG release, we add it as a patch here. No internal logic of EBG is
changed, hence no dedicated release is needed.

Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
 recipes-bsp/efibootguard/efibootguard_0.13.bb |  3 ++
 ...01-add-machine-type-name-for-riscv64.patch | 39 +++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch

diff --git a/recipes-bsp/efibootguard/efibootguard_0.13.bb b/recipes-bsp/efibootguard/efibootguard_0.13.bb
index 3279854..dd76198 100644
--- a/recipes-bsp/efibootguard/efibootguard_0.13.bb
+++ b/recipes-bsp/efibootguard/efibootguard_0.13.bb
@@ -21,6 +21,9 @@ SRC_URI = " \
     file://debian \
     "
 SRC_URI[sha256sum] = "639a6d8f687cb099b2e9b01eb08ad1494267fe26b5d903b4d405d0737feb989b"
+# add riscv64 support
+SRC_URI += "file://0001-add-machine-type-name-for-riscv64.patch"
+CHANGELOG_V = "${PV}+cip"
 
 PROVIDES = "${PN}"
 PROVIDES += "${PN}-dev"
diff --git a/recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch b/recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch
new file mode 100644
index 0000000..adc7962
--- /dev/null
+++ b/recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch
@@ -0,0 +1,39 @@
+From 391dd5e04b17be6f5184afb2de4853795f1d5620 Mon Sep 17 00:00:00 2001
+From: Felix Moessbauer <felix.moessbauer@siemens.com>
+Date: Tue, 31 Jan 2023 09:27:31 +0100
+Subject: [PATCH 1/1] add machine type name for riscv64
+
+By adding the machine type name, the generated efi binary for
+riscv64 is suffixed with the corresponding efi machine name.
+
+Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+---
+ configure.ac | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/configure.ac b/configure.ac
+index d8f9d3a..90d70b0 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -87,6 +87,7 @@ SET_ARCH(X86_64, x86_64*)
+ SET_ARCH(IA64, ia64*)
+ SET_ARCH(AARCH64, aarch64*)
+ SET_ARCH(ARM, arm*)
++SET_ARCH(RISCV64, riscv64*)
+ 
+ ARCH=$(echo $host | sed "s/\(-\).*$//")
+ 
+@@ -103,6 +104,9 @@ AM_COND_IF(ARCH_AARCH64, [
+ AM_COND_IF(ARCH_ARM, [
+ 	   MACHINE_TYPE_NAME=arm])
+ 
++AM_COND_IF(ARCH_RISCV64, [
++	   MACHINE_TYPE_NAME=riscv64])
++
+ AC_SUBST([ARCH])
+ AC_SUBST([MACHINE_TYPE_NAME])
+ AM_CONDITIONAL([ARCH_IS_X86], [test "$ARCH" = "ia32" -o "$ARCH" = "x86_64"])
+-- 
+2.30.2
+
-- 
2.34.1



  parent reply	other threads:[~2023-03-03 13:12 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 1/8] make reason for disabling wdog on arm more precise Felix Moessbauer
2023-03-03 12:48 ` Felix Moessbauer [this message]
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 3/8] wic(ebg): add support for riscv64 Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 4/8] add opensbi with u-boot payload " Felix Moessbauer
2023-03-04  8:35   ` Jan Kiszka
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 5/8] enhance qemu-riscv64 machine to be testable Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 6/8] add linux 6.1 mainline kernel Felix Moessbauer
2023-03-04  8:12   ` Jan Kiszka
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 7/8] add swupdate support for qemu-riscv64 Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 8/8] start-qemu: add support for swupdate on RISC-V Felix Moessbauer
2023-03-06  6:10 ` [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Jan Kiszka

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