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* [cip-dev] [PATCH 4.4.y-cip] ARM: dts: am33xx: Added macros for numeric pinmux addresses
@ 2020-06-03 10:10 johnsonch.chen@moxa.com
  2020-06-03 15:24 ` Pavel Machek
  0 siblings, 1 reply; 3+ messages in thread
From: johnsonch.chen@moxa.com @ 2020-06-03 10:10 UTC (permalink / raw)
  To: cip-dev, nobuhiro1.iwamatsu, pavel

[-- Attachment #1: Type: text/plain, Size: 5901 bytes --]

From: Christina Quast <cquast@hanoverdisplays.com>

commit 7ebd1ea798a4932231b18499df136fb552f6f648 upstream.

The values are extraced from the "AM335x SitaraTM Processors Technical
Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the
file autogenerated by TI PinMux.

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Johnson Chen <johnsonch.chen@moxa.com>
---
 include/dt-bindings/pinctrl/am33xx.h | 130 ++++++++++++++++++++++++++++++++++-
 1 file changed, 129 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h
index 7d947a597220..17877e85980b 100644
--- a/include/dt-bindings/pinctrl/am33xx.h
+++ b/include/dt-bindings/pinctrl/am33xx.h
@@ -40,5 +40,133 @@
 #undef PIN_OFF_INPUT_PULLDOWN
 #undef PIN_OFF_WAKEUPENABLE
 
-#endif
+#define AM335X_PIN_OFFSET_MIN			0x0800U
+
+#define AM335X_PIN_GPMC_AD0			0x800
+#define AM335X_PIN_GPMC_AD1			0x804
+#define AM335X_PIN_GPMC_AD2			0x808
+#define AM335X_PIN_GPMC_AD3			0x80c
+#define AM335X_PIN_GPMC_AD4			0x810
+#define AM335X_PIN_GPMC_AD5			0x814
+#define AM335X_PIN_GPMC_AD6			0x818
+#define AM335X_PIN_GPMC_AD7			0x81c
+#define AM335X_PIN_GPMC_AD8			0x820
+#define AM335X_PIN_GPMC_AD9			0x824
+#define AM335X_PIN_GPMC_AD10			0x828
+#define AM335X_PIN_GPMC_AD11			0x82c
+#define AM335X_PIN_GPMC_AD12			0x830
+#define AM335X_PIN_GPMC_AD13			0x834
+#define AM335X_PIN_GPMC_AD14			0x838
+#define AM335X_PIN_GPMC_AD15			0x83c
+#define AM335X_PIN_GPMC_A0			0x840
+#define AM335X_PIN_GPMC_A1			0x844
+#define AM335X_PIN_GPMC_A2			0x848
+#define AM335X_PIN_GPMC_A3			0x84c
+#define AM335X_PIN_GPMC_A4			0x850
+#define AM335X_PIN_GPMC_A5			0x854
+#define AM335X_PIN_GPMC_A6			0x858
+#define AM335X_PIN_GPMC_A7			0x85c
+#define AM335X_PIN_GPMC_A8			0x860
+#define AM335X_PIN_GPMC_A9			0x864
+#define AM335X_PIN_GPMC_A10			0x868
+#define AM335X_PIN_GPMC_A11			0x86c
+#define AM335X_PIN_GPMC_WAIT0			0x870
+#define AM335X_PIN_GPMC_WPN			0x874
+#define AM335X_PIN_GPMC_BEN1			0x878
+#define AM335X_PIN_GPMC_CSN0			0x87c
+#define AM335X_PIN_GPMC_CSN1			0x880
+#define AM335X_PIN_GPMC_CSN2			0x884
+#define AM335X_PIN_GPMC_CSN3			0x888
+#define AM335X_PIN_GPMC_CLK			0x88c
+#define AM335X_PIN_GPMC_ADVN_ALE		0x890
+#define AM335X_PIN_GPMC_OEN_REN			0x894
+#define AM335X_PIN_GPMC_WEN			0x898
+#define AM335X_PIN_GPMC_BEN0_CLE		0x89c
+#define AM335X_PIN_LCD_DATA0			0x8a0
+#define AM335X_PIN_LCD_DATA1			0x8a4
+#define AM335X_PIN_LCD_DATA2			0x8a8
+#define AM335X_PIN_LCD_DATA3			0x8ac
+#define AM335X_PIN_LCD_DATA4			0x8b0
+#define AM335X_PIN_LCD_DATA5			0x8b4
+#define AM335X_PIN_LCD_DATA6			0x8b8
+#define AM335X_PIN_LCD_DATA7			0x8bc
+#define AM335X_PIN_LCD_DATA8			0x8c0
+#define AM335X_PIN_LCD_DATA9			0x8c4
+#define AM335X_PIN_LCD_DATA10			0x8c8
+#define AM335X_PIN_LCD_DATA11			0x8cc
+#define AM335X_PIN_LCD_DATA12			0x8d0
+#define AM335X_PIN_LCD_DATA13			0x8d4
+#define AM335X_PIN_LCD_DATA14			0x8d8
+#define AM335X_PIN_LCD_DATA15			0x8dc
+#define AM335X_PIN_LCD_VSYNC			0x8e0
+#define AM335X_PIN_LCD_HSYNC			0x8e4
+#define AM335X_PIN_LCD_PCLK			0x8e8
+#define AM335X_PIN_LCD_AC_BIAS_EN		0x8ec
+#define AM335X_PIN_MMC0_DAT3			0x8f0
+#define AM335X_PIN_MMC0_DAT2			0x8f4
+#define AM335X_PIN_MMC0_DAT1			0x8f8
+#define AM335X_PIN_MMC0_DAT0			0x8fc
+#define AM335X_PIN_MMC0_CLK			0x900
+#define AM335X_PIN_MMC0_CMD			0x904
+#define AM335X_PIN_MII1_COL			0x908
+#define AM335X_PIN_MII1_CRS			0x90c
+#define AM335X_PIN_MII1_RX_ER			0x910
+#define AM335X_PIN_MII1_TX_EN			0x914
+#define AM335X_PIN_MII1_RX_DV			0x918
+#define AM335X_PIN_MII1_TXD3			0x91c
+#define AM335X_PIN_MII1_TXD2			0x920
+#define AM335X_PIN_MII1_TXD1			0x924
+#define AM335X_PIN_MII1_TXD0			0x928
+#define AM335X_PIN_MII1_TX_CLK			0x92c
+#define AM335X_PIN_MII1_RX_CLK			0x930
+#define AM335X_PIN_MII1_RXD3			0x934
+#define AM335X_PIN_MII1_RXD2			0x938
+#define AM335X_PIN_MII1_RXD1			0x93c
+#define AM335X_PIN_MII1_RXD0			0x940
+#define AM335X_PIN_RMII1_REF_CLK		0x944
+#define AM335X_PIN_MDIO				0x948
+#define AM335X_PIN_MDC				0x94c
+#define AM335X_PIN_SPI0_SCLK			0x950
+#define AM335X_PIN_SPI0_D0			0x954
+#define AM335X_PIN_SPI0_D1			0x958
+#define AM335X_PIN_SPI0_CS0			0x95c
+#define AM335X_PIN_SPI0_CS1			0x960
+#define AM335X_PIN_ECAP0_IN_PWM0_OUT		0x964
+#define AM335X_PIN_UART0_CTSN			0x968
+#define AM335X_PIN_UART0_RTSN			0x96c
+#define AM335X_PIN_UART0_RXD			0x970
+#define AM335X_PIN_UART0_TXD			0x974
+#define AM335X_PIN_UART1_CTSN			0x978
+#define AM335X_PIN_UART1_RTSN			0x97c
+#define AM335X_PIN_UART1_RXD			0x980
+#define AM335X_PIN_UART1_TXD			0x984
+#define AM335X_PIN_I2C0_SDA			0x988
+#define AM335X_PIN_I2C0_SCL			0x98c
+#define AM335X_PIN_MCASP0_ACLKX			0x990
+#define AM335X_PIN_MCASP0_FSX			0x994
+#define AM335X_PIN_MCASP0_AXR0			0x998
+#define AM335X_PIN_MCASP0_AHCLKR		0x99c
+#define AM335X_PIN_MCASP0_ACLKR			0x9a0
+#define AM335X_PIN_MCASP0_FSR			0x9a4
+#define AM335X_PIN_MCASP0_AXR1			0x9a8
+#define AM335X_PIN_MCASP0_AHCLKX		0x9ac
+#define AM335X_PIN_XDMA_EVENT_INTR0		0x9b0
+#define AM335X_PIN_XDMA_EVENT_INTR1		0x9b4
+#define AM335X_PIN_WARMRSTN			0x9b8
+#define AM335X_PIN_NNMI				0x9c0
+#define AM335X_PIN_TMS				0x9d0
+#define AM335X_PIN_TDI				0x9d4
+#define AM335X_PIN_TDO				0x9d8
+#define AM335X_PIN_TCK				0x9dc
+#define AM335X_PIN_TRSTN			0x9e0
+#define AM335X_PIN_EMU0				0x9e4
+#define AM335X_PIN_EMU1				0x9e8
+#define AM335X_PIN_RTC_PWRONRSTN		0x9f8
+#define AM335X_PIN_PMIC_POWER_EN		0x9fc
+#define AM335X_PIN_EXT_WAKEUP			0xa00
+#define AM335X_PIN_USB0_DRVVBUS			0xa1c
+#define AM335X_PIN_USB1_DRVVBUS			0xa34
 
+#define AM335X_PIN_OFFSET_MAX			0x0a34U
+
+#endif
-- 
2.11.0


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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [cip-dev] [PATCH 4.4.y-cip] ARM: dts: am33xx: Added macros for numeric pinmux addresses
  2020-06-03 10:10 [cip-dev] [PATCH 4.4.y-cip] ARM: dts: am33xx: Added macros for numeric pinmux addresses johnsonch.chen@moxa.com
@ 2020-06-03 15:24 ` Pavel Machek
  2020-06-04  2:18   ` johnsonch.chen@moxa.com
  0 siblings, 1 reply; 3+ messages in thread
From: Pavel Machek @ 2020-06-03 15:24 UTC (permalink / raw)
  To: Johnson CH Chen (陳昭勳)
  Cc: cip-dev, nobuhiro1.iwamatsu, pavel


[-- Attachment #1.1: Type: text/plain, Size: 893 bytes --]

Hi!

> From: Christina Quast <cquast@hanoverdisplays.com>
> 
> commit 7ebd1ea798a4932231b18499df136fb552f6f648 upstream.
> 
> The values are extraced from the "AM335x SitaraTM Processors Technical
> Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the
> file autogenerated by TI PinMux.

I don't see anything wrong with the patch. OTOH I'd expect to see this
in a series with the code actually using these defines.

Is there a reason to merge it on its own?

Best regards,
								Pavel

> Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Johnson Chen <johnsonch.chen@moxa.com>


-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [cip-dev] [PATCH 4.4.y-cip] ARM: dts: am33xx: Added macros for numeric pinmux addresses
  2020-06-03 15:24 ` Pavel Machek
@ 2020-06-04  2:18   ` johnsonch.chen@moxa.com
  0 siblings, 0 replies; 3+ messages in thread
From: johnsonch.chen@moxa.com @ 2020-06-04  2:18 UTC (permalink / raw)
  To: Pavel Machek; +Cc: cip-dev, nobuhiro1.iwamatsu

[-- Attachment #1: Type: text/plain, Size: 1203 bytes --]

> Hi!
>
> > From: Christina Quast <cquast@hanoverdisplays.com>
> >
> > commit 7ebd1ea798a4932231b18499df136fb552f6f648 upstream.
> >
> > The values are extraced from the "AM335x SitaraTM Processors
> Technical
> > Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on
> the
> > file autogenerated by TI PinMux.
>
> I don't see anything wrong with the patch. OTOH I'd expect to see this in a series with the code actually using these defines.
>
> Is there a reason to merge it on its own?

It sounds better to send a series with using these defines one time than separating it with defines and using codes with two times.
I will send patch series later, thanks!

Best regards,
Johnson

>
> Best regards,
>                                                                 Pavel
>
> > Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > Signed-off-by: Johnson Chen <johnsonch.chen@moxa.com>
>
>
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>

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2020-06-03 10:10 [cip-dev] [PATCH 4.4.y-cip] ARM: dts: am33xx: Added macros for numeric pinmux addresses johnsonch.chen@moxa.com
2020-06-03 15:24 ` Pavel Machek
2020-06-04  2:18   ` johnsonch.chen@moxa.com

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