From: Samuel Holland <samuel@sholland.org> To: Jisheng Zhang <jszhang@kernel.org> Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, "Conor Dooley" <conor.dooley@microchip.com>, "Rob Herring" <robh+dt@kernel.org>, "Conor Dooley" <conor@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Jiri Slaby" <jirislaby@kernel.org>, "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com> Subject: Re: [PATCH v2 3/9] riscv: add the Bouffalolab SoC family Kconfig option Date: Wed, 30 Nov 2022 00:48:58 -0600 [thread overview] Message-ID: <d0344e62-b9ff-8465-9556-5562e195f4a3@sholland.org> (raw) In-Reply-To: <20221127132448.4034-4-jszhang@kernel.org> On 11/27/22 07:24, Jisheng Zhang wrote: > The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and > LP. The D0 is 64bit RISC-V GC compatible, so can run linux. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/Kconfig.socs | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 69774bb362d6..90256f44ed4a 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -1,5 +1,11 @@ > menu "SoC selection" > > +config SOC_BOUFFALOLAB The options in this file are getting renamed soon, so this should be named ARCH_BOUFFALOLAB. See https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ Regards, Samuel > + bool "Bouffalolab SoCs" > + select SIFIVE_PLIC > + help > + This enables support for Bouffalolab SoC platforms. > + > config SOC_MICROCHIP_POLARFIRE > bool "Microchip PolarFire SoCs" > select MCHP_CLK_MPFS
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel@sholland.org> To: Jisheng Zhang <jszhang@kernel.org> Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, "Conor Dooley" <conor.dooley@microchip.com>, "Rob Herring" <robh+dt@kernel.org>, "Conor Dooley" <conor@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Jiri Slaby" <jirislaby@kernel.org>, "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com> Subject: Re: [PATCH v2 3/9] riscv: add the Bouffalolab SoC family Kconfig option Date: Wed, 30 Nov 2022 00:48:58 -0600 [thread overview] Message-ID: <d0344e62-b9ff-8465-9556-5562e195f4a3@sholland.org> (raw) In-Reply-To: <20221127132448.4034-4-jszhang@kernel.org> On 11/27/22 07:24, Jisheng Zhang wrote: > The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and > LP. The D0 is 64bit RISC-V GC compatible, so can run linux. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/Kconfig.socs | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 69774bb362d6..90256f44ed4a 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -1,5 +1,11 @@ > menu "SoC selection" > > +config SOC_BOUFFALOLAB The options in this file are getting renamed soon, so this should be named ARCH_BOUFFALOLAB. See https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ Regards, Samuel > + bool "Bouffalolab SoCs" > + select SIFIVE_PLIC > + help > + This enables support for Bouffalolab SoC platforms. > + > config SOC_MICROCHIP_POLARFIRE > bool "Microchip PolarFire SoCs" > select MCHP_CLK_MPFS _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-30 6:49 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-27 13:24 [PATCH v2 0/9] riscv: add Bouffalolab bl808 support Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 13:24 ` [PATCH v2 1/9] dt-bindings: serial: add documentation for Bouffalolab UART Driver Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-30 5:45 ` Samuel Holland 2022-11-30 5:45 ` Samuel Holland 2022-12-01 11:02 ` Krzysztof Kozlowski 2022-12-01 11:02 ` Krzysztof Kozlowski 2022-11-27 13:24 ` [PATCH v2 2/9] serial: bflb_uart: add " Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-28 6:10 ` Jiri Slaby 2022-11-28 6:10 ` Jiri Slaby 2022-11-28 14:21 ` Jisheng Zhang 2022-11-28 14:21 ` Jisheng Zhang 2022-11-28 16:01 ` Ilpo Järvinen 2022-11-28 16:01 ` Ilpo Järvinen 2022-11-28 23:20 ` Jisheng Zhang 2022-11-28 23:20 ` Jisheng Zhang 2022-11-29 6:32 ` Jiri Slaby 2022-11-29 6:32 ` Jiri Slaby 2022-12-05 20:03 ` kernel test robot 2022-12-05 20:03 ` kernel test robot 2022-11-27 13:24 ` [PATCH v2 3/9] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-30 6:48 ` Samuel Holland [this message] 2022-11-30 6:48 ` Samuel Holland 2022-11-27 13:24 ` [PATCH v2 4/9] dt-bindings: vendor-prefixes: add bouffalolab Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:23 ` Conor Dooley 2022-11-27 17:23 ` Conor Dooley 2022-12-01 11:03 ` Krzysztof Kozlowski 2022-12-01 11:03 ` Krzysztof Kozlowski 2022-11-27 13:24 ` [PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 16:25 ` Rob Herring 2022-11-27 16:25 ` Rob Herring 2022-11-27 17:29 ` Conor Dooley 2022-11-27 17:29 ` Conor Dooley 2022-12-01 11:05 ` Krzysztof Kozlowski 2022-12-01 11:05 ` Krzysztof Kozlowski 2022-12-01 11:14 ` Conor Dooley 2022-12-01 11:14 ` Conor Dooley 2022-12-01 11:41 ` Krzysztof Kozlowski 2022-12-01 11:41 ` Krzysztof Kozlowski 2022-11-27 13:24 ` [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:21 ` Conor Dooley 2022-11-27 17:21 ` Conor Dooley 2022-11-28 9:52 ` Icenowy Zheng 2022-11-28 9:52 ` Icenowy Zheng 2022-11-28 14:52 ` Conor Dooley 2022-11-28 14:52 ` Conor Dooley 2022-11-30 7:21 ` Samuel Holland 2022-11-30 7:21 ` Samuel Holland 2022-12-05 8:17 ` Icenowy Zheng 2022-12-05 8:17 ` Icenowy Zheng 2022-12-05 10:29 ` Conor Dooley 2022-12-05 10:29 ` Conor Dooley 2023-01-04 8:32 ` Michael Walle 2023-01-04 8:32 ` Michael Walle 2022-11-27 13:24 ` [PATCH v2 7/9] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:32 ` Conor Dooley 2022-11-27 17:32 ` Conor Dooley 2022-11-30 7:25 ` Samuel Holland 2022-11-30 7:25 ` Samuel Holland 2022-12-05 8:15 ` Icenowy Zheng 2022-12-05 8:15 ` Icenowy Zheng 2022-11-27 13:24 ` [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:35 ` Conor Dooley 2022-11-27 17:35 ` Conor Dooley 2022-11-27 17:36 ` Conor Dooley 2022-11-27 17:36 ` Conor Dooley 2022-11-28 14:30 ` Jisheng Zhang 2022-11-28 14:30 ` Jisheng Zhang 2022-11-28 14:34 ` Jisheng Zhang 2022-11-28 14:34 ` Jisheng Zhang 2022-11-28 14:50 ` Conor Dooley 2022-11-28 14:50 ` Conor Dooley 2022-11-30 7:27 ` Samuel Holland 2022-11-30 7:27 ` Samuel Holland 2022-11-27 13:24 ` [PATCH v2 9/9] riscv: defconfig: enable BOUFFALOLAB SoC Jisheng Zhang 2022-11-27 13:24 ` Jisheng Zhang 2022-11-27 17:36 ` Conor Dooley 2022-11-27 17:36 ` Conor Dooley 2022-12-02 17:54 ` [PATCH v2 0/9] riscv: add Bouffalolab bl808 support Palmer Dabbelt 2022-12-02 17:54 ` Palmer Dabbelt
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