From: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: Jagan Teki
<jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>,
Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
Philipp Tomsich
<philipp.tomsich-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
sunil-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org,
patrick-Er2xLVyhcs+zQB+pC5nmwQ@public.gmane.org,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org,
u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org
Subject: Re: [PATCH 4/8] clk: rk3399: Disable PCIE_PHY clock【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips.com@lists.infradead.org代发】
Date: Tue, 28 Apr 2020 17:53:31 +0800 [thread overview]
Message-ID: <d4b055de-4cde-d99a-28e8-e98460786067@rock-chips.com> (raw)
In-Reply-To: <20200425110354.12381-5-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
On 2020/4/25 下午7:03, Jagan Teki wrote:
> Add PCIE_PHY clock disablement support on rk3399
> clock driver.
>
> This would trigger if the PCIe PHY driver failed to
> initialize or power on the PHY.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> drivers/clk/rockchip/clk_rk3399.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 8e069fbade..2d447f96f7 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1085,6 +1085,22 @@ static int rk3399_clk_enable(struct clk *clk)
> return 0;
> }
>
> +static int rk3399_clk_disable(struct clk *clk)
> +{
> + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + switch (clk->id) {
> + case SCLK_PCIEPHY_REF:
> + rk_clrreg(&priv->cru->clksel_con[18], BIT(7));
> + break;
> + default:
> + debug("%s: unsupported clk %ld\n", __func__, clk->id);
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> static struct clk_ops rk3399_clk_ops = {
> .get_rate = rk3399_clk_get_rate,
> .set_rate = rk3399_clk_set_rate,
> @@ -1092,6 +1108,7 @@ static struct clk_ops rk3399_clk_ops = {
> .set_parent = rk3399_clk_set_parent,
> #endif
> .enable = rk3399_clk_enable,
> + .disable = rk3399_clk_disable,
> };
>
> #ifdef CONFIG_SPL_BUILD
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WARNING: multiple messages have this Message-ID (diff)
From: Kever Yang <kever.yang@rock-chips.com>
To: u-boot@lists.denx.de
Subject: Re: [PATCH 4/8] clk: rk3399: Disable PCIE_PHY clock【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips.com@lists.infradead.org代发】
Date: Tue, 28 Apr 2020 17:53:31 +0800 [thread overview]
Message-ID: <d4b055de-4cde-d99a-28e8-e98460786067@rock-chips.com> (raw)
In-Reply-To: <20200425110354.12381-5-jagan@amarulasolutions.com>
On 2020/4/25 ??7:03, Jagan Teki wrote:
> Add PCIE_PHY clock disablement support on rk3399
> clock driver.
>
> This would trigger if the PCIe PHY driver failed to
> initialize or power on the PHY.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> drivers/clk/rockchip/clk_rk3399.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 8e069fbade..2d447f96f7 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1085,6 +1085,22 @@ static int rk3399_clk_enable(struct clk *clk)
> return 0;
> }
>
> +static int rk3399_clk_disable(struct clk *clk)
> +{
> + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + switch (clk->id) {
> + case SCLK_PCIEPHY_REF:
> + rk_clrreg(&priv->cru->clksel_con[18], BIT(7));
> + break;
> + default:
> + debug("%s: unsupported clk %ld\n", __func__, clk->id);
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> static struct clk_ops rk3399_clk_ops = {
> .get_rate = rk3399_clk_get_rate,
> .set_rate = rk3399_clk_set_rate,
> @@ -1092,6 +1108,7 @@ static struct clk_ops rk3399_clk_ops = {
> .set_parent = rk3399_clk_set_parent,
> #endif
> .enable = rk3399_clk_enable,
> + .disable = rk3399_clk_disable,
> };
>
> #ifdef CONFIG_SPL_BUILD
next prev parent reply other threads:[~2020-04-28 9:53 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-25 11:03 [PATCH 0/8] rockchip: Add PCIe host support Jagan Teki
2020-04-25 11:03 ` Jagan Teki
[not found] ` <20200425110354.12381-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2020-04-25 11:03 ` [PATCH 1/8] iopoll: Add dealy to read poll Jagan Teki
2020-04-25 11:03 ` Jagan Teki
2020-04-25 11:03 ` [PATCH 2/8] iopoll: Add readl_poll_sleep_timeout Jagan Teki
2020-04-25 11:03 ` Jagan Teki
2020-04-25 11:03 ` [PATCH 3/8] clk: rk3399: Enable PCIE_PHY clock Jagan Teki
2020-04-25 11:03 ` Jagan Teki
2020-04-25 20:24 ` Mark Kettenis
2020-04-25 20:24 ` Mark Kettenis
[not found] ` <016196395ae8077b-Sse5TxTiDWuxJFhkpKByzTXZidJgq2Oi@public.gmane.org>
2020-04-26 9:38 ` Jagan Teki
2020-04-26 9:38 ` Jagan Teki
2020-04-25 11:03 ` [PATCH 4/8] clk: rk3399: Disable " Jagan Teki
2020-04-25 11:03 ` Jagan Teki
[not found] ` <20200425110354.12381-5-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2020-04-28 9:53 ` Kever Yang [this message]
2020-04-28 9:53 ` [PATCH 4/8] clk: rk3399: Disable PCIE_PHY clock【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips.com@lists.infradead.org代发】 Kever Yang
2020-04-25 11:03 ` [PATCH 5/8] pci: Add Rockchip PCIe controller driver Jagan Teki
2020-04-25 11:03 ` Jagan Teki
2020-04-25 18:53 ` Mark Kettenis
2020-04-25 18:53 ` Mark Kettenis
2020-04-25 19:36 ` Jagan Teki
2020-04-25 19:36 ` Jagan Teki
2020-04-25 20:29 ` Mark Kettenis
2020-04-25 20:29 ` Mark Kettenis
2020-04-28 19:09 ` Jagan Teki
2020-04-28 19:09 ` Jagan Teki
[not found] ` <CAMty3ZC+DiW2gGjN3rWcrwHPXZfxuGhjJN-1caUXW-Ry7VNR+A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-04-27 17:19 ` Robin Murphy
2020-04-27 17:19 ` Robin Murphy
[not found] ` <20200425110354.12381-6-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2020-04-25 23:51 ` [PATCH 5/8] pci: Add Rockchip PCIe controller driver【请注意，邮件由linux-rockchip-bounces+shawn.lin=rock-chips.com@lists.infradead.org代发】 Shawn Lin
2020-04-25 23:51 ` Shawn Lin
2020-04-28 19:39 ` Jagan Teki
2020-04-28 19:39 ` Jagan Teki
2020-04-28 9:53 ` [PATCH 5/8] pci: Add Rockchip PCIe controller driver Kever Yang
2020-04-28 9:53 ` Kever Yang
2020-04-25 11:03 ` [PATCH 6/8] pci: Add Rockchip PCIe PHY " Jagan Teki
2020-04-25 11:03 ` Jagan Teki
2020-04-25 11:03 ` [PATCH 7/8] rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2 Jagan Teki
2020-04-25 11:03 ` Jagan Teki
2020-04-25 11:03 ` [PATCH 8/8] rockchip: Enable PCIe/M.2 on rock960 board Jagan Teki
2020-04-25 11:03 ` Jagan Teki
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