From: Dan Carpenter <dan.carpenter@oracle.com>
To: dragos.bogdan@analog.com
Cc: dmaengine@vger.kernel.org
Subject: [bug report] dmaengine: axi-dmac: Add support for interleaved cyclic transfers
Date: Mon, 24 Jun 2019 15:13:57 +0300 [thread overview]
Message-ID: <20190624121357.GA29335@mwanda> (raw)
Hello Dragos Bogdan,
The patch 8add6cce9848: "dmaengine: axi-dmac: Add support for
interleaved cyclic transfers" from May 16, 2019, leads to the
following static checker warning:
drivers/dma/dma-axi-dmac.c:666 axi_dmac_prep_interleaved()
warn: bit shifter 'DMA_CYCLIC' used for logical '&'
drivers/dma/dma-axi-dmac.c
658 if (chan->hw_2d) {
659 desc->sg[0].x_len = xt->sgl[0].size;
660 desc->sg[0].y_len = xt->numf;
661 } else {
662 desc->sg[0].x_len = xt->sgl[0].size * xt->numf;
663 desc->sg[0].y_len = 1;
664 }
665
666 if (flags & DMA_CYCLIC)
667 desc->cyclic = true;
This won't work. I think you have to use dma_has_cap() or test_bit() or
something. Or you could do:
if (flags & (1 << DMA_CYCLIC)) {
DMA_CYCLIC is 0xb so this will return true for a bunch of stuff when it
shouldn't.
668
669 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
670 }
regards,
dan carpenter
reply other threads:[~2019-06-24 12:14 UTC|newest]
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