* [PATCH v5 1/3] dt-bindings: dmaengine: dma-common: Change dma-channel-mask to uint32-array
2019-10-25 7:30 [PATCH v5 0/3] dmaengine: bindings/edma: dma-channel-mask to array Peter Ujfalusi
@ 2019-10-25 7:30 ` Peter Ujfalusi
2019-10-25 7:30 ` [PATCH v5 2/3] dt-bindings: dma: ti-edma: Document dma-channel-mask for EDMA Peter Ujfalusi
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Peter Ujfalusi @ 2019-10-25 7:30 UTC (permalink / raw)
To: vkoul, robh+dt; +Cc: dmaengine, linux-kernel, dan.j.williams, devicetree
Make the dma-channel-mask to be usable for controllers with more than 32
channels.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/dma/dma-common.yaml | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/dma-common.yaml b/Documentation/devicetree/bindings/dma/dma-common.yaml
index ed0a49a6f020..02a34ba2b49b 100644
--- a/Documentation/devicetree/bindings/dma/dma-common.yaml
+++ b/Documentation/devicetree/bindings/dma/dma-common.yaml
@@ -25,11 +25,18 @@ properties:
Used to provide DMA controller specific information.
dma-channel-mask:
- $ref: /schemas/types.yaml#definitions/uint32
description:
Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.
+ The first item in the array is for channels 0-31, the second is for
+ channels 32-63, etc.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ minItems: 1
+ # Should be enough
+ maxItems: 255
dma-channels:
$ref: /schemas/types.yaml#definitions/uint32
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v5 2/3] dt-bindings: dma: ti-edma: Document dma-channel-mask for EDMA
2019-10-25 7:30 [PATCH v5 0/3] dmaengine: bindings/edma: dma-channel-mask to array Peter Ujfalusi
2019-10-25 7:30 ` [PATCH v5 1/3] dt-bindings: dmaengine: dma-common: Change dma-channel-mask to uint32-array Peter Ujfalusi
@ 2019-10-25 7:30 ` Peter Ujfalusi
2019-10-25 7:30 ` [PATCH v5 3/3] dmaengine: ti: edma: Add support for handling reserved channels Peter Ujfalusi
2019-11-05 17:01 ` [PATCH v5 0/3] dmaengine: bindings/edma: dma-channel-mask to array Vinod Koul
3 siblings, 0 replies; 6+ messages in thread
From: Peter Ujfalusi @ 2019-10-25 7:30 UTC (permalink / raw)
To: vkoul, robh+dt; +Cc: dmaengine, linux-kernel, dan.j.williams, devicetree
Similarly to paRAM slots, channels can be used by other cores.
The common dma-channel-mask property can be used for specifying the
available channels.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/dma/ti-edma.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
index 4bbc94d829c8..0e1398f93aa2 100644
--- a/Documentation/devicetree/bindings/dma/ti-edma.txt
+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
@@ -42,6 +42,11 @@ Optional properties:
- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
the driver, they are allocated to be used by for example the
DSP. See example.
+- dma-channel-mask: Mask of usable channels.
+ Single uint32 for EDMA with 32 channels, array of two uint32 for
+ EDMA with 64 channels. See example and
+ Documentation/devicetree/bindings/dma/dma-common.yaml
+
------------------------------------------------------------------------------
eDMA3 Transfer Controller
@@ -91,6 +96,9 @@ edma: edma@49000000 {
ti,edma-memcpy-channels = <20 21>;
/* The following PaRAM slots are reserved: 35-44 and 100-109 */
ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
+ /* The following channels are reserved: 35-44 */
+ dma-channel-mask = <0xffffffff /* Channel 0-31 */
+ 0xffffe007>; /* Channel 32-63 */
};
edma_tptc0: tptc@49800000 {
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v5 3/3] dmaengine: ti: edma: Add support for handling reserved channels
2019-10-25 7:30 [PATCH v5 0/3] dmaengine: bindings/edma: dma-channel-mask to array Peter Ujfalusi
2019-10-25 7:30 ` [PATCH v5 1/3] dt-bindings: dmaengine: dma-common: Change dma-channel-mask to uint32-array Peter Ujfalusi
2019-10-25 7:30 ` [PATCH v5 2/3] dt-bindings: dma: ti-edma: Document dma-channel-mask for EDMA Peter Ujfalusi
@ 2019-10-25 7:30 ` Peter Ujfalusi
2019-11-05 17:01 ` [PATCH v5 0/3] dmaengine: bindings/edma: dma-channel-mask to array Vinod Koul
3 siblings, 0 replies; 6+ messages in thread
From: Peter Ujfalusi @ 2019-10-25 7:30 UTC (permalink / raw)
To: vkoul, robh+dt; +Cc: dmaengine, linux-kernel, dan.j.williams, devicetree
Like paRAM slots, channels could be used by other cores and in this case
we need to make sure that the driver do not alter these channels.
Handle the generic dma-channel-mask property to mark channels in a bitmap
which can not be used by Linux and convert the legacy rsv_chans if it is
provided by platform_data.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/ti/edma.c | 59 ++++++++++++++++++++++++++++++++++++++-----
1 file changed, 53 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c
index 54fd981e3db5..0ecfc2e1d798 100644
--- a/drivers/dma/ti/edma.c
+++ b/drivers/dma/ti/edma.c
@@ -260,6 +260,13 @@ struct edma_cc {
*/
unsigned long *slot_inuse;
+ /*
+ * For tracking reserved channels used by DSP.
+ * If the bit is cleared, the channel is allocated to be used by DSP
+ * and Linux must not touch it.
+ */
+ unsigned long *channels_mask;
+
struct dma_device dma_slave;
struct dma_device *dma_memcpy;
struct edma_chan *slave_chans;
@@ -716,6 +723,12 @@ static int edma_alloc_channel(struct edma_chan *echan,
struct edma_cc *ecc = echan->ecc;
int channel = EDMA_CHAN_SLOT(echan->ch_num);
+ if (!test_bit(echan->ch_num, ecc->channels_mask)) {
+ dev_err(ecc->dev, "Channel%d is reserved, can not be used!\n",
+ echan->ch_num);
+ return -EINVAL;
+ }
+
/* ensure access through shadow region 0 */
edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel),
EDMA_CHANNEL_BIT(channel));
@@ -2249,7 +2262,7 @@ static int edma_probe(struct platform_device *pdev)
{
struct edma_soc_info *info = pdev->dev.platform_data;
s8 (*queue_priority_mapping)[2];
- const s16 (*rsv_slots)[2];
+ const s16 (*reserved)[2];
int i, irq;
char *irq_name;
struct resource *mem;
@@ -2329,15 +2342,32 @@ static int edma_probe(struct platform_device *pdev)
if (!ecc->slot_inuse)
return -ENOMEM;
+ ecc->channels_mask = devm_kcalloc(dev,
+ BITS_TO_LONGS(ecc->num_channels),
+ sizeof(unsigned long), GFP_KERNEL);
+ if (!ecc->channels_mask)
+ return -ENOMEM;
+
+ /* Mark all channels available initially */
+ bitmap_fill(ecc->channels_mask, ecc->num_channels);
+
ecc->default_queue = info->default_queue;
if (info->rsv) {
/* Set the reserved slots in inuse list */
- rsv_slots = info->rsv->rsv_slots;
- if (rsv_slots) {
- for (i = 0; rsv_slots[i][0] != -1; i++)
- bitmap_set(ecc->slot_inuse, rsv_slots[i][0],
- rsv_slots[i][1]);
+ reserved = info->rsv->rsv_slots;
+ if (reserved) {
+ for (i = 0; reserved[i][0] != -1; i++)
+ bitmap_set(ecc->slot_inuse, reserved[i][0],
+ reserved[i][1]);
+ }
+
+ /* Clear channels not usable for Linux */
+ reserved = info->rsv->rsv_chans;
+ if (reserved) {
+ for (i = 0; reserved[i][0] != -1; i++)
+ bitmap_clear(ecc->channels_mask, reserved[i][0],
+ reserved[i][1]);
}
}
@@ -2389,6 +2419,7 @@ static int edma_probe(struct platform_device *pdev)
if (!ecc->legacy_mode) {
int lowest_priority = 0;
+ unsigned int array_max;
struct of_phandle_args tc_args;
ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
@@ -2410,6 +2441,18 @@ static int edma_probe(struct platform_device *pdev)
info->default_queue = i;
}
}
+
+ /* See if we have optional dma-channel-mask array */
+ array_max = DIV_ROUND_UP(ecc->num_channels, BITS_PER_TYPE(u32));
+ ret = of_property_read_variable_u32_array(node,
+ "dma-channel-mask",
+ (u32 *)ecc->channels_mask,
+ 1, array_max);
+ if (ret > 0 && ret != array_max)
+ dev_warn(dev, "dma-channel-mask is not complete.\n");
+ else if (ret == -EOVERFLOW || ret == -ENODATA)
+ dev_warn(dev,
+ "dma-channel-mask is out of range or empty\n");
}
/* Event queue priority mapping */
@@ -2427,6 +2470,10 @@ static int edma_probe(struct platform_device *pdev)
edma_dma_init(ecc, legacy_mode);
for (i = 0; i < ecc->num_channels; i++) {
+ /* Do not touch reserved channels */
+ if (!test_bit(i, ecc->channels_mask))
+ continue;
+
/* Assign all channels to the default queue */
edma_assign_channel_eventq(&ecc->slave_chans[i],
info->default_queue);
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related [flat|nested] 6+ messages in thread