* [PATCH v8] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue @ 2020-12-23 9:30 EastL Lee 2020-12-23 9:30 ` [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL Lee ` (3 more replies) 0 siblings, 4 replies; 10+ messages in thread From: EastL Lee @ 2020-12-23 9:30 UTC (permalink / raw) To: Sean Wang Cc: vkoul, robh+dt, mark.rutland, matthias.bgg, dmaengine, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream, cc.hwang This patch set adds document the devicetree bindings for MediaTek Command-Queue DMA controller, and remove redundant queue structure. hanges since v6: - fix dt binding format hanges since v5: - fix full name hanges since v4: - fix yaml & dma-mask code flow hanges since v3: - fix dt_binding_check errors Changes since v2: - add devicetree bindings for MediaTek Command-Queue DMA controller Changes since v1: - remove redundant queue structure - fix wrong description and tags in the earlier patch - add dma-channel-mask for DMA capability - fix compatible for common ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings 2020-12-23 9:30 [PATCH v8] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL Lee @ 2020-12-23 9:30 ` EastL Lee 2021-01-03 16:58 ` Rob Herring 2020-12-23 9:30 ` [PATCH v8 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure EastL Lee ` (2 subsequent siblings) 3 siblings, 1 reply; 10+ messages in thread From: EastL Lee @ 2020-12-23 9:30 UTC (permalink / raw) To: Sean Wang Cc: vkoul, robh+dt, mark.rutland, matthias.bgg, dmaengine, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream, cc.hwang, EastL Lee Document the devicetree bindings for MediaTek Command-Queue DMA controller which could be found on MT6779 SoC or other similar Mediatek SoCs. Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> --- .../devicetree/bindings/dma/mtk-cqdma.yaml | 104 +++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml new file mode 100644 index 0000000..a76a263 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Command-Queue DMA controller Device Tree Binding + +maintainers: + - EastL Lee <EastL.Lee@mediatek.com> + +description: + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC + is dedicated to memory-to-memory transfer through queue based + descriptor management. + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + items: + - enum: + - mediatek,mt6765-cqdma + - mediatek,mt6779-cqdma + - const: mediatek,cqdma + + reg: + minItems: 1 + maxItems: 5 + description: + A base address of MediaTek Command-Queue DMA controller, + a channel will have a set of base address. + + interrupts: + minItems: 1 + maxItems: 5 + description: + A interrupt number of MediaTek Command-Queue DMA controller, + one interrupt number per dma-channels. + + clocks: + maxItems: 1 + + clock-names: + const: cqdma + + dma-channel-mask: + description: + For DMA capability, We will know the addressing capability of + MediaTek Command-Queue DMA controller through dma-channel-mask. + minimum: 1 + maximum: 63 + + dma-channels: + description: + Number of DMA channels supported by MediaTek Command-Queue DMA + controller, support up to five. + minimum: 1 + maximum: 5 + + dma-requests: + description: + Number of DMA request (virtual channel) supported by MediaTek + Command-Queue DMA controller, support up to 32. + minimum: 1 + maximum: 32 + +required: + - "#dma-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + - dma-channel-mask + - dma-channels + - dma-requests + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt6779-clk.h> + cqdma: dma-controller@10212000 { + compatible = "mediatek,mt6779-cqdma"; + reg = <0x10212000 0x80>, + <0x10212080 0x80>, + <0x10212100 0x80>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; + clock-names = "cqdma"; + dma-channel-mask = <63>; + dma-channels = <3>; + dma-requests = <32>; + #dma-cells = <1>; + }; + +... -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings 2020-12-23 9:30 ` [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL Lee @ 2021-01-03 16:58 ` Rob Herring 2021-01-06 9:25 ` EastL 0 siblings, 1 reply; 10+ messages in thread From: Rob Herring @ 2021-01-03 16:58 UTC (permalink / raw) To: EastL Lee Cc: Sean Wang, vkoul, mark.rutland, matthias.bgg, dmaengine, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream, cc.hwang On Wed, Dec 23, 2020 at 05:30:44PM +0800, EastL Lee wrote: > Document the devicetree bindings for MediaTek Command-Queue DMA controller > which could be found on MT6779 SoC or other similar Mediatek SoCs. > > Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> > --- > .../devicetree/bindings/dma/mtk-cqdma.yaml | 104 +++++++++++++++++++++ Use compatible string for filename: mediatek,cqdma.yaml > 1 file changed, 104 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > new file mode 100644 > index 0000000..a76a263 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > @@ -0,0 +1,104 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# Don't forget to update this. > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Command-Queue DMA controller Device Tree Binding > + > +maintainers: > + - EastL Lee <EastL.Lee@mediatek.com> > + > +description: > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC > + is dedicated to memory-to-memory transfer through queue based > + descriptor management. > + > +allOf: > + - $ref: "dma-controller.yaml#" > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt6765-cqdma > + - mediatek,mt6779-cqdma > + - const: mediatek,cqdma > + > + reg: > + minItems: 1 > + maxItems: 5 > + description: > + A base address of MediaTek Command-Queue DMA controller, > + a channel will have a set of base address. > + > + interrupts: > + minItems: 1 > + maxItems: 5 > + description: > + A interrupt number of MediaTek Command-Queue DMA controller, > + one interrupt number per dma-channels. > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: cqdma > + > + dma-channel-mask: > + description: > + For DMA capability, We will know the addressing capability of > + MediaTek Command-Queue DMA controller through dma-channel-mask. > + minimum: 1 > + maximum: 63 Indentation is wrong here so this has no effect. A mask of 63 is 6 channels... > + > + dma-channels: > + description: > + Number of DMA channels supported by MediaTek Command-Queue DMA > + controller, support up to five. > + minimum: 1 > + maximum: 5 Same here. Do you really need both dma-channels and dma-channel-mask? You should be able to get one from the other. > + > + dma-requests: > + description: > + Number of DMA request (virtual channel) supported by MediaTek > + Command-Queue DMA controller, support up to 32. > + minimum: 1 > + maximum: 32 And here. You are missing '#dma-cells' also. > + > +required: > + - "#dma-cells" > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - dma-channel-mask > + - dma-channels > + - dma-requests > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/mt6779-clk.h> > + cqdma: dma-controller@10212000 { > + compatible = "mediatek,mt6779-cqdma"; This should fail validation because it doesn't match the schema. You ran 'make dt_binding_check', right? > + reg = <0x10212000 0x80>, > + <0x10212080 0x80>, > + <0x10212100 0x80>; > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>, > + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>, > + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; > + clock-names = "cqdma"; > + dma-channel-mask = <63>; 6 channels or... > + dma-channels = <3>; 3? > + dma-requests = <32>; > + #dma-cells = <1>; > + }; > + > +... > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings 2021-01-03 16:58 ` Rob Herring @ 2021-01-06 9:25 ` EastL 2021-01-06 23:53 ` Rob Herring 0 siblings, 1 reply; 10+ messages in thread From: EastL @ 2021-01-06 9:25 UTC (permalink / raw) To: Rob Herring Cc: Sean Wang, vkoul, mark.rutland, matthias.bgg, dmaengine, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream, cc.hwang On Sun, 2021-01-03 at 09:58 -0700, Rob Herring wrote: > On Wed, Dec 23, 2020 at 05:30:44PM +0800, EastL Lee wrote: > > Document the devicetree bindings for MediaTek Command-Queue DMA controller > > which could be found on MT6779 SoC or other similar Mediatek SoCs. > > > > Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> > > --- > > .../devicetree/bindings/dma/mtk-cqdma.yaml | 104 +++++++++++++++++++++ > > Use compatible string for filename: OK > > mediatek,cqdma.yaml > > > 1 file changed, 104 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > > > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > new file mode 100644 > > index 0000000..a76a263 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > @@ -0,0 +1,104 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# > > Don't forget to update this. OK > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek Command-Queue DMA controller Device Tree Binding > > + > > +maintainers: > > + - EastL Lee <EastL.Lee@mediatek.com> > > + > > +description: > > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC > > + is dedicated to memory-to-memory transfer through queue based > > + descriptor management. > > + > > +allOf: > > + - $ref: "dma-controller.yaml#" > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt6765-cqdma > > + - mediatek,mt6779-cqdma > > + - const: mediatek,cqdma > > + > > + reg: > > + minItems: 1 > > + maxItems: 5 > > + description: > > + A base address of MediaTek Command-Queue DMA controller, > > + a channel will have a set of base address. > > + > > + interrupts: > > + minItems: 1 > > + maxItems: 5 > > + description: > > + A interrupt number of MediaTek Command-Queue DMA controller, > > + one interrupt number per dma-channels. > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + const: cqdma > > + > > + dma-channel-mask: > > + description: > > + For DMA capability, We will know the addressing capability of > > + MediaTek Command-Queue DMA controller through dma-channel-mask. > > + minimum: 1 > > + maximum: 63 > > Indentation is wrong here so this has no effect. I'll fix it > > A mask of 63 is 6 channels... In my opinion, kernel dma mask if for 32/64 bit capability... If I don't set dma mask I will get fail on DMATEST. > > > + > > + dma-channels: > > + description: > > + Number of DMA channels supported by MediaTek Command-Queue DMA > > + controller, support up to five. > > + minimum: 1 > > + maximum: 5 > > Same here. OK > > Do you really need both dma-channels and dma-channel-mask? You should be > able to get one from the other. > > > + > > + dma-requests: > > + description: > > + Number of DMA request (virtual channel) supported by MediaTek > > + Command-Queue DMA controller, support up to 32. > > + minimum: 1 > > + maximum: 32 > > And here. > > You are missing '#dma-cells' also. OK I'll fix it. > > > + > > +required: > > + - "#dma-cells" > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + - dma-channel-mask > > + - dma-channels > > + - dma-requests > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/clock/mt6779-clk.h> > > + cqdma: dma-controller@10212000 { > > + compatible = "mediatek,mt6779-cqdma"; > > This should fail validation because it doesn't match the schema. You ran > 'make dt_binding_check', right? Yes, but I got other fail on kernel-5.10... > > > + reg = <0x10212000 0x80>, > > + <0x10212080 0x80>, > > + <0x10212100 0x80>; > > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>, > > + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>, > > + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; > > + clock-names = "cqdma"; > > + dma-channel-mask = <63>; > > 6 channels or... > > > + dma-channels = <3>; > > 3? 3 channel, the mask is for DMATEST PASS. > > > + dma-requests = <32>; > > + #dma-cells = <1>; > > + }; > > + > > +... > > -- > > 1.9.1 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings 2021-01-06 9:25 ` EastL @ 2021-01-06 23:53 ` Rob Herring 2021-01-12 12:13 ` Vinod Koul 0 siblings, 1 reply; 10+ messages in thread From: Rob Herring @ 2021-01-06 23:53 UTC (permalink / raw) To: EastL Cc: Sean Wang, Vinod, Mark Rutland, Matthias Brugger, open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM, linux-kernel, linux-arm-kernel, moderated list:ARM/Mediatek SoC support, devicetree, wsd_upstream, CC Hwang On Wed, Jan 6, 2021 at 2:25 AM EastL <EastL.Lee@mediatek.com> wrote: > > On Sun, 2021-01-03 at 09:58 -0700, Rob Herring wrote: > > On Wed, Dec 23, 2020 at 05:30:44PM +0800, EastL Lee wrote: > > > Document the devicetree bindings for MediaTek Command-Queue DMA controller > > > which could be found on MT6779 SoC or other similar Mediatek SoCs. > > > > > > Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> > > > --- > > > .../devicetree/bindings/dma/mtk-cqdma.yaml | 104 +++++++++++++++++++++ > > > > Use compatible string for filename: > OK > > > > mediatek,cqdma.yaml > > > > > 1 file changed, 104 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > > new file mode 100644 > > > index 0000000..a76a263 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > > @@ -0,0 +1,104 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# > > > > Don't forget to update this. > OK > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: MediaTek Command-Queue DMA controller Device Tree Binding > > > + > > > +maintainers: > > > + - EastL Lee <EastL.Lee@mediatek.com> > > > + > > > +description: > > > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC > > > + is dedicated to memory-to-memory transfer through queue based > > > + descriptor management. > > > + > > > +allOf: > > > + - $ref: "dma-controller.yaml#" > > > + > > > +properties: > > > + compatible: > > > + items: > > > + - enum: > > > + - mediatek,mt6765-cqdma > > > + - mediatek,mt6779-cqdma > > > + - const: mediatek,cqdma > > > + > > > + reg: > > > + minItems: 1 > > > + maxItems: 5 > > > + description: > > > + A base address of MediaTek Command-Queue DMA controller, > > > + a channel will have a set of base address. > > > + > > > + interrupts: > > > + minItems: 1 > > > + maxItems: 5 > > > + description: > > > + A interrupt number of MediaTek Command-Queue DMA controller, > > > + one interrupt number per dma-channels. > > > + > > > + clocks: > > > + maxItems: 1 > > > + > > > + clock-names: > > > + const: cqdma > > > + > > > + dma-channel-mask: > > > + description: > > > + For DMA capability, We will know the addressing capability of > > > + MediaTek Command-Queue DMA controller through dma-channel-mask. > > > + minimum: 1 > > > + maximum: 63 > > > > Indentation is wrong here so this has no effect. > I'll fix it > > > > A mask of 63 is 6 channels... > In my opinion, kernel dma mask if for 32/64 bit capability... > If I don't set dma mask I will get fail on DMATEST. As in the kernel's 'dma_mask'? That's something entirely different. The driver should set the mask to the max the device supports. Typically this is a 32-bit or 64-bit mask. The default is 32-bit. If the SoC has limitations in its buses, then you need to use 'dma-ranges' in DT which will in turn set the bus_dma_limit. For the above, the purpose is if you have sparsely allocated DMA channels. Rob ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings 2021-01-06 23:53 ` Rob Herring @ 2021-01-12 12:13 ` Vinod Koul 0 siblings, 0 replies; 10+ messages in thread From: Vinod Koul @ 2021-01-12 12:13 UTC (permalink / raw) To: Rob Herring Cc: EastL, Sean Wang, Mark Rutland, Matthias Brugger, open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM, linux-kernel, linux-arm-kernel, moderated list:ARM/Mediatek SoC support, devicetree, wsd_upstream, CC Hwang On 06-01-21, 16:53, Rob Herring wrote: > > > > + dma-channel-mask: > > > > + description: > > > > + For DMA capability, We will know the addressing capability of > > > > + MediaTek Command-Queue DMA controller through dma-channel-mask. > > > > + minimum: 1 > > > > + maximum: 63 > > > > > > Indentation is wrong here so this has no effect. > > I'll fix it > > > > > > A mask of 63 is 6 channels... > > In my opinion, kernel dma mask if for 32/64 bit capability... > > If I don't set dma mask I will get fail on DMATEST. > > As in the kernel's 'dma_mask'? That's something entirely different. > The driver should set the mask to the max the device supports. > Typically this is a 32-bit or 64-bit mask. The default is 32-bit. If > the SoC has limitations in its buses, then you need to use > 'dma-ranges' in DT which will in turn set the bus_dma_limit. Correct, dma_mask tells dmatest the capability of the device and should be set accordingly dma-channel-mask defines the 'Bitmask of available DMA channels' and is deined in dma-common.yaml -- ~Vinod ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v8 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure 2020-12-23 9:30 [PATCH v8] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL Lee 2020-12-23 9:30 ` [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL Lee @ 2020-12-23 9:30 ` EastL Lee 2021-01-12 12:10 ` Vinod Koul 2020-12-23 9:30 ` [PATCH v8 3/4] dmaengine: mediatek-cqdma: add dma mask for capability EastL Lee 2020-12-23 9:30 ` [PATCH v8 4/4] dmaengine: mediatek-cqdma: fix compatible EastL Lee 3 siblings, 1 reply; 10+ messages in thread From: EastL Lee @ 2020-12-23 9:30 UTC (permalink / raw) To: Sean Wang Cc: vkoul, robh+dt, mark.rutland, matthias.bgg, dmaengine, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream, cc.hwang, EastL Lee This patch introduces active_vdec to indicate the virtual descriptor under processing by the CQDMA dmaengine, and simplify the control logic by removing redundant queue structure, tasklets, and completion management. Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> --- drivers/dma/mediatek/mtk-cqdma.c | 382 ++++++++++----------------------------- 1 file changed, 93 insertions(+), 289 deletions(-) diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c index 41ef9f1..905bbcb 100644 --- a/drivers/dma/mediatek/mtk-cqdma.c +++ b/drivers/dma/mediatek/mtk-cqdma.c @@ -22,6 +22,7 @@ #include <linux/of_dma.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/preempt.h> #include <linux/refcount.h> #include <linux/slab.h> @@ -47,7 +48,6 @@ #define MTK_CQDMA_SRC 0x1c #define MTK_CQDMA_DST 0x20 #define MTK_CQDMA_LEN1 0x24 -#define MTK_CQDMA_LEN2 0x28 #define MTK_CQDMA_SRC2 0x60 #define MTK_CQDMA_DST2 0x64 @@ -69,45 +69,32 @@ * descriptor (CVD) * @vd: An instance for struct virt_dma_desc * @len: The total data size device wants to move - * @residue: The remaining data size device will move * @dest: The destination address device wants to move to * @src: The source address device wants to move from * @ch: The pointer to the corresponding dma channel - * @node: The lise_head struct to build link-list for VDs - * @parent: The pointer to the parent CVD */ struct mtk_cqdma_vdesc { struct virt_dma_desc vd; size_t len; - size_t residue; dma_addr_t dest; dma_addr_t src; struct dma_chan *ch; - - struct list_head node; - struct mtk_cqdma_vdesc *parent; }; /** * struct mtk_cqdma_pchan - The struct holding info describing physical * channel (PC) - * @queue: Queue for the PDs issued to this PC + * @active_vdesc: The pointer to the CVD which is under processing * @base: The mapped register I/O base of this PC * @irq: The IRQ that this PC are using * @refcnt: Track how many VCs are using this PC - * @tasklet: Tasklet for this PC * @lock: Lock protect agaisting multiple VCs access PC */ struct mtk_cqdma_pchan { - struct list_head queue; + struct mtk_cqdma_vdesc *active_vdesc; void __iomem *base; u32 irq; - refcount_t refcnt; - - struct tasklet_struct tasklet; - - /* lock to protect PC */ spinlock_t lock; }; @@ -116,14 +103,11 @@ struct mtk_cqdma_pchan { * channel (VC) * @vc: An instance for struct virt_dma_chan * @pc: The pointer to the underlying PC - * @issue_completion: The wait for all issued descriptors completited - * @issue_synchronize: Bool indicating channel synchronization starts */ struct mtk_cqdma_vchan { struct virt_dma_chan vc; struct mtk_cqdma_pchan *pc; - struct completion issue_completion; - bool issue_synchronize; + struct completion cmp; }; /** @@ -202,22 +186,22 @@ static void mtk_cqdma_vdesc_free(struct virt_dma_desc *vd) kfree(to_cqdma_vdesc(vd)); } -static int mtk_cqdma_poll_engine_done(struct mtk_cqdma_pchan *pc, bool atomic) +static int mtk_cqdma_poll_engine_done(struct mtk_cqdma_pchan *pc) { u32 status = 0; - if (!atomic) + if (in_task()) + return readl_poll_timeout_atomic(pc->base + MTK_CQDMA_EN, + status, + !(status & MTK_CQDMA_EN_BIT), + MTK_CQDMA_USEC_POLL, + MTK_CQDMA_TIMEOUT_POLL); + else return readl_poll_timeout(pc->base + MTK_CQDMA_EN, status, !(status & MTK_CQDMA_EN_BIT), MTK_CQDMA_USEC_POLL, MTK_CQDMA_TIMEOUT_POLL); - - return readl_poll_timeout_atomic(pc->base + MTK_CQDMA_EN, - status, - !(status & MTK_CQDMA_EN_BIT), - MTK_CQDMA_USEC_POLL, - MTK_CQDMA_TIMEOUT_POLL); } static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc) @@ -225,20 +209,17 @@ static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc) mtk_dma_set(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT); mtk_dma_clr(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT); - return mtk_cqdma_poll_engine_done(pc, true); + return mtk_cqdma_poll_engine_done(pc); } static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc, struct mtk_cqdma_vdesc *cvd) { - /* wait for the previous transaction done */ - if (mtk_cqdma_poll_engine_done(pc, true) < 0) - dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma wait transaction timeout\n"); - /* warm reset the dma engine for the new transaction */ mtk_dma_set(pc, MTK_CQDMA_RESET, MTK_CQDMA_WARM_RST_BIT); - if (mtk_cqdma_poll_engine_done(pc, true) < 0) - dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma warm reset timeout\n"); + if (mtk_cqdma_poll_engine_done(pc) < 0) + dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), + "cqdma warm reset timeout\n"); /* setup the source */ mtk_dma_set(pc, MTK_CQDMA_SRC, cvd->src & MTK_CQDMA_ADDR_LIMIT); @@ -257,7 +238,8 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc, #endif /* setup the length */ - mtk_dma_set(pc, MTK_CQDMA_LEN1, cvd->len); + mtk_dma_set(pc, MTK_CQDMA_LEN1, (cvd->len < MTK_CQDMA_MAX_LEN) ? + cvd->len : MTK_CQDMA_MAX_LEN); /* start dma engine */ mtk_dma_set(pc, MTK_CQDMA_EN, MTK_CQDMA_EN_BIT); @@ -265,30 +247,17 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc, static void mtk_cqdma_issue_vchan_pending(struct mtk_cqdma_vchan *cvc) { - struct virt_dma_desc *vd, *vd2; + struct virt_dma_desc *vd; struct mtk_cqdma_pchan *pc = cvc->pc; - struct mtk_cqdma_vdesc *cvd; - bool trigger_engine = false; lockdep_assert_held(&cvc->vc.lock); lockdep_assert_held(&pc->lock); - list_for_each_entry_safe(vd, vd2, &cvc->vc.desc_issued, node) { - /* need to trigger dma engine if PC's queue is empty */ - if (list_empty(&pc->queue)) - trigger_engine = true; - - cvd = to_cqdma_vdesc(vd); - - /* add VD into PC's queue */ - list_add_tail(&cvd->node, &pc->queue); - - /* start the dma engine */ - if (trigger_engine) - mtk_cqdma_start(pc, cvd); + vd = vchan_next_desc(&cvc->vc); - /* remove VD from list desc_issued */ - list_del(&vd->node); + if (vd && !pc->active_vdesc) { + pc->active_vdesc = to_cqdma_vdesc(vd); + mtk_cqdma_start(pc, pc->active_vdesc); } } @@ -298,100 +267,55 @@ static void mtk_cqdma_issue_vchan_pending(struct mtk_cqdma_vchan *cvc) */ static bool mtk_cqdma_is_vchan_active(struct mtk_cqdma_vchan *cvc) { - struct mtk_cqdma_vdesc *cvd; - - list_for_each_entry(cvd, &cvc->pc->queue, node) - if (cvc == to_cqdma_vchan(cvd->ch)) - return true; - - return false; + return (!cvc->pc->active_vdesc) ? false : + (cvc == to_cqdma_vchan(cvc->pc->active_vdesc->ch)); } -/* - * return the pointer of the CVD that is just consumed by the PC - */ -static struct mtk_cqdma_vdesc -*mtk_cqdma_consume_work_queue(struct mtk_cqdma_pchan *pc) +static void mtk_cqdma_complete_vdesc(struct mtk_cqdma_pchan *pc) { struct mtk_cqdma_vchan *cvc; - struct mtk_cqdma_vdesc *cvd, *ret = NULL; - - /* consume a CVD from PC's queue */ - cvd = list_first_entry_or_null(&pc->queue, - struct mtk_cqdma_vdesc, node); - if (unlikely(!cvd || !cvd->parent)) - return NULL; + struct mtk_cqdma_vdesc *cvd; + struct virt_dma_desc *vd; + size_t tlen; + cvd = pc->active_vdesc; cvc = to_cqdma_vchan(cvd->ch); - ret = cvd; - - /* update residue of the parent CVD */ - cvd->parent->residue -= cvd->len; - /* delete CVD from PC's queue */ - list_del(&cvd->node); + tlen = (cvd->len < MTK_CQDMA_MAX_LEN) ? cvd->len : MTK_CQDMA_MAX_LEN; + cvd->len -= tlen; + cvd->src += tlen; + cvd->dest += tlen; spin_lock(&cvc->vc.lock); - /* check whether all the child CVDs completed */ - if (!cvd->parent->residue) { - /* add the parent VD into list desc_completed */ - vchan_cookie_complete(&cvd->parent->vd); + /* check whether the VD completed */ + if (!cvd->len) { + /* delete VD from desc_issued */ + list_del(&cvd->vd.node); - /* setup completion if this VC is under synchronization */ - if (cvc->issue_synchronize && !mtk_cqdma_is_vchan_active(cvc)) { - complete(&cvc->issue_completion); - cvc->issue_synchronize = false; - } - } - - spin_unlock(&cvc->vc.lock); + /* add the VD into list desc_completed */ + vchan_cookie_complete(&cvd->vd); - /* start transaction for next CVD in the queue */ - cvd = list_first_entry_or_null(&pc->queue, - struct mtk_cqdma_vdesc, node); - if (cvd) - mtk_cqdma_start(pc, cvd); - - return ret; -} - -static void mtk_cqdma_tasklet_cb(struct tasklet_struct *t) -{ - struct mtk_cqdma_pchan *pc = from_tasklet(pc, t, tasklet); - struct mtk_cqdma_vdesc *cvd = NULL; - unsigned long flags; - - spin_lock_irqsave(&pc->lock, flags); - /* consume the queue */ - cvd = mtk_cqdma_consume_work_queue(pc); - spin_unlock_irqrestore(&pc->lock, flags); - - /* submit the next CVD */ - if (cvd) { - dma_run_dependencies(&cvd->vd.tx); - - /* - * free child CVD after completion. - * the parent CVD would be freeed with desc_free by user. - */ - if (cvd->parent != cvd) - kfree(cvd); + /* get the next active VD */ + vd = vchan_next_desc(&cvc->vc); + pc->active_vdesc = (!vd) ? NULL : to_cqdma_vdesc(vd); } - /* re-enable interrupt before leaving tasklet */ - enable_irq(pc->irq); + /* start the next transaction */ + if (pc->active_vdesc) + mtk_cqdma_start(pc, pc->active_vdesc); + + spin_unlock(&cvc->vc.lock); } static irqreturn_t mtk_cqdma_irq(int irq, void *devid) { struct mtk_cqdma_device *cqdma = devid; irqreturn_t ret = IRQ_NONE; - bool schedule_tasklet = false; u32 i; /* clear interrupt flags for each PC */ - for (i = 0; i < cqdma->dma_channels; ++i, schedule_tasklet = false) { + for (i = 0; i < cqdma->dma_channels; ++i) { spin_lock(&cqdma->pc[i]->lock); if (mtk_dma_read(cqdma->pc[i], MTK_CQDMA_INT_FLAG) & MTK_CQDMA_INT_FLAG_BIT) { @@ -399,72 +323,21 @@ static irqreturn_t mtk_cqdma_irq(int irq, void *devid) mtk_dma_clr(cqdma->pc[i], MTK_CQDMA_INT_FLAG, MTK_CQDMA_INT_FLAG_BIT); - schedule_tasklet = true; + mtk_cqdma_complete_vdesc(cqdma->pc[i]); + ret = IRQ_HANDLED; } spin_unlock(&cqdma->pc[i]->lock); - - if (schedule_tasklet) { - /* disable interrupt */ - disable_irq_nosync(cqdma->pc[i]->irq); - - /* schedule the tasklet to handle the transactions */ - tasklet_schedule(&cqdma->pc[i]->tasklet); - } } return ret; } -static struct virt_dma_desc *mtk_cqdma_find_active_desc(struct dma_chan *c, - dma_cookie_t cookie) -{ - struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c); - struct virt_dma_desc *vd; - unsigned long flags; - - spin_lock_irqsave(&cvc->pc->lock, flags); - list_for_each_entry(vd, &cvc->pc->queue, node) - if (vd->tx.cookie == cookie) { - spin_unlock_irqrestore(&cvc->pc->lock, flags); - return vd; - } - spin_unlock_irqrestore(&cvc->pc->lock, flags); - - list_for_each_entry(vd, &cvc->vc.desc_issued, node) - if (vd->tx.cookie == cookie) - return vd; - - return NULL; -} - static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c, dma_cookie_t cookie, struct dma_tx_state *txstate) { - struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c); - struct mtk_cqdma_vdesc *cvd; - struct virt_dma_desc *vd; - enum dma_status ret; - unsigned long flags; - size_t bytes = 0; - - ret = dma_cookie_status(c, cookie, txstate); - if (ret == DMA_COMPLETE || !txstate) - return ret; - - spin_lock_irqsave(&cvc->vc.lock, flags); - vd = mtk_cqdma_find_active_desc(c, cookie); - spin_unlock_irqrestore(&cvc->vc.lock, flags); - - if (vd) { - cvd = to_cqdma_vdesc(vd); - bytes = cvd->residue; - } - - dma_set_residue(txstate, bytes); - - return ret; + return dma_cookie_status(c, cookie, txstate); } static void mtk_cqdma_issue_pending(struct dma_chan *c) @@ -473,13 +346,17 @@ static void mtk_cqdma_issue_pending(struct dma_chan *c) unsigned long pc_flags; unsigned long vc_flags; - /* acquire PC's lock before VS's lock for lock dependency in tasklet */ + /* acquire PC's lock before VC's lock for lock dependency in ISR */ spin_lock_irqsave(&cvc->pc->lock, pc_flags); spin_lock_irqsave(&cvc->vc.lock, vc_flags); + init_completion(&cvc->cmp); + if (vchan_issue_pending(&cvc->vc)) mtk_cqdma_issue_vchan_pending(cvc); + complete(&cvc->cmp); + spin_unlock_irqrestore(&cvc->vc.lock, vc_flags); spin_unlock_irqrestore(&cvc->pc->lock, pc_flags); } @@ -488,125 +365,50 @@ static void mtk_cqdma_issue_pending(struct dma_chan *c) mtk_cqdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) { - struct mtk_cqdma_vdesc **cvd; - struct dma_async_tx_descriptor *tx = NULL, *prev_tx = NULL; - size_t i, tlen, nr_vd; - - /* - * In the case that trsanction length is larger than the - * DMA engine supports, a single memcpy transaction needs - * to be separated into several DMA transactions. - * Each DMA transaction would be described by a CVD, - * and the first one is referred as the parent CVD, - * while the others are child CVDs. - * The parent CVD's tx descriptor is the only tx descriptor - * returned to the DMA user, and it should not be completed - * until all the child CVDs completed. - */ - nr_vd = DIV_ROUND_UP(len, MTK_CQDMA_MAX_LEN); - cvd = kcalloc(nr_vd, sizeof(*cvd), GFP_NOWAIT); + struct mtk_cqdma_vdesc *cvd; + + cvd = kzalloc(sizeof(*cvd), GFP_NOWAIT); if (!cvd) return NULL; - for (i = 0; i < nr_vd; ++i) { - cvd[i] = kzalloc(sizeof(*cvd[i]), GFP_NOWAIT); - if (!cvd[i]) { - for (; i > 0; --i) - kfree(cvd[i - 1]); - return NULL; - } - - /* setup dma channel */ - cvd[i]->ch = c; - - /* setup sourece, destination, and length */ - tlen = (len > MTK_CQDMA_MAX_LEN) ? MTK_CQDMA_MAX_LEN : len; - cvd[i]->len = tlen; - cvd[i]->src = src; - cvd[i]->dest = dest; - - /* setup tx descriptor */ - tx = vchan_tx_prep(to_virt_chan(c), &cvd[i]->vd, flags); - tx->next = NULL; + /* setup dma channel */ + cvd->ch = c; - if (!i) { - cvd[0]->residue = len; - } else { - prev_tx->next = tx; - cvd[i]->residue = tlen; - } - - cvd[i]->parent = cvd[0]; - - /* update the src, dest, len, prev_tx for the next CVD */ - src += tlen; - dest += tlen; - len -= tlen; - prev_tx = tx; - } + /* setup sourece, destination, and length */ + cvd->len = len; + cvd->src = src; + cvd->dest = dest; - return &cvd[0]->vd.tx; + return vchan_tx_prep(to_virt_chan(c), &cvd->vd, flags); } -static void mtk_cqdma_free_inactive_desc(struct dma_chan *c) -{ - struct virt_dma_chan *vc = to_virt_chan(c); - unsigned long flags; - LIST_HEAD(head); - - /* - * set desc_allocated, desc_submitted, - * and desc_issued as the candicates to be freed - */ - spin_lock_irqsave(&vc->lock, flags); - list_splice_tail_init(&vc->desc_allocated, &head); - list_splice_tail_init(&vc->desc_submitted, &head); - list_splice_tail_init(&vc->desc_issued, &head); - spin_unlock_irqrestore(&vc->lock, flags); - - /* free descriptor lists */ - vchan_dma_desc_free_list(vc, &head); -} - -static void mtk_cqdma_free_active_desc(struct dma_chan *c) +static int mtk_cqdma_terminate_all(struct dma_chan *c) { struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c); - bool sync_needed = false; + struct virt_dma_chan *vc = to_virt_chan(c); unsigned long pc_flags; unsigned long vc_flags; + LIST_HEAD(head); + + /* wait for the VC to be inactive */ + if (!wait_for_completion_timeout(&cvc->cmp, msecs_to_jiffies(3000))) + return -EAGAIN; /* acquire PC's lock first due to lock dependency in dma ISR */ spin_lock_irqsave(&cvc->pc->lock, pc_flags); spin_lock_irqsave(&cvc->vc.lock, vc_flags); - /* synchronization is required if this VC is active */ - if (mtk_cqdma_is_vchan_active(cvc)) { - cvc->issue_synchronize = true; - sync_needed = true; - } + /* get VDs from lists */ + vchan_get_all_descriptors(vc, &head); + + /* free all the VDs */ + vchan_dma_desc_free_list(vc, &head); spin_unlock_irqrestore(&cvc->vc.lock, vc_flags); spin_unlock_irqrestore(&cvc->pc->lock, pc_flags); - /* waiting for the completion of this VC */ - if (sync_needed) - wait_for_completion(&cvc->issue_completion); - - /* free all descriptors in list desc_completed */ vchan_synchronize(&cvc->vc); - WARN_ONCE(!list_empty(&cvc->vc.desc_completed), - "Desc pending still in list desc_completed\n"); -} - -static int mtk_cqdma_terminate_all(struct dma_chan *c) -{ - /* free descriptors not processed yet by hardware */ - mtk_cqdma_free_inactive_desc(c); - - /* free descriptors being processed by hardware */ - mtk_cqdma_free_active_desc(c); - return 0; } @@ -618,7 +420,7 @@ static int mtk_cqdma_alloc_chan_resources(struct dma_chan *c) u32 i, min_refcnt = U32_MAX, refcnt; unsigned long flags; - /* allocate PC with the minimun refcount */ + /* allocate PC with the minimum refcount */ for (i = 0; i < cqdma->dma_channels; ++i) { refcnt = refcount_read(&cqdma->pc[i]->refcnt); if (refcnt < min_refcnt) { @@ -671,8 +473,9 @@ static void mtk_cqdma_free_chan_resources(struct dma_chan *c) mtk_dma_set(cvc->pc, MTK_CQDMA_FLUSH, MTK_CQDMA_FLUSH_BIT); /* wait for the completion of flush operation */ - if (mtk_cqdma_poll_engine_done(cvc->pc, true) < 0) - dev_err(cqdma2dev(to_cqdma_dev(c)), "cqdma flush timeout\n"); + if (mtk_cqdma_poll_engine_done(cvc->pc) < 0) + dev_err(cqdma2dev(to_cqdma_dev(c)), + "cqdma flush timeout\n"); /* clear the flush bit and interrupt flag */ mtk_dma_clr(cvc->pc, MTK_CQDMA_FLUSH, MTK_CQDMA_FLUSH_BIT); @@ -816,10 +619,18 @@ static int mtk_cqdma_probe(struct platform_device *pdev) if (!cqdma->pc[i]) return -ENOMEM; - INIT_LIST_HEAD(&cqdma->pc[i]->queue); + cqdma->pc[i]->active_vdesc = NULL; spin_lock_init(&cqdma->pc[i]->lock); refcount_set(&cqdma->pc[i]->refcnt, 0); - cqdma->pc[i]->base = devm_platform_ioremap_resource(pdev, i); + + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) { + dev_err(&pdev->dev, "No mem resource for %s\n", + dev_name(&pdev->dev)); + return -EINVAL; + } + + cqdma->pc[i]->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(cqdma->pc[i]->base)) return PTR_ERR(cqdma->pc[i]->base); @@ -852,7 +663,6 @@ static int mtk_cqdma_probe(struct platform_device *pdev) vc = &cqdma->vc[i]; vc->vc.desc_free = mtk_cqdma_vdesc_free; vchan_init(&vc->vc, dd); - init_completion(&vc->issue_completion); } err = dma_async_device_register(dd); @@ -876,10 +686,6 @@ static int mtk_cqdma_probe(struct platform_device *pdev) platform_set_drvdata(pdev, cqdma); - /* initialize tasklet for each PC */ - for (i = 0; i < cqdma->dma_channels; ++i) - tasklet_setup(&cqdma->pc[i]->tasklet, mtk_cqdma_tasklet_cb); - dev_info(&pdev->dev, "MediaTek CQDMA driver registered\n"); return 0; @@ -914,8 +720,6 @@ static int mtk_cqdma_remove(struct platform_device *pdev) /* Waits for any pending IRQ handlers to complete */ synchronize_irq(cqdma->pc[i]->irq); - - tasklet_kill(&cqdma->pc[i]->tasklet); } /* disable hardware */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v8 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure 2020-12-23 9:30 ` [PATCH v8 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure EastL Lee @ 2021-01-12 12:10 ` Vinod Koul 0 siblings, 0 replies; 10+ messages in thread From: Vinod Koul @ 2021-01-12 12:10 UTC (permalink / raw) To: EastL Lee Cc: Sean Wang, robh+dt, mark.rutland, matthias.bgg, dmaengine, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream, cc.hwang On 23-12-20, 17:30, EastL Lee wrote: > This patch introduces active_vdec to indicate the virtual descriptor > under processing by the CQDMA dmaengine, and simplify the control logic > by removing redundant queue structure, tasklets, and completion > management. Can we split these changes up.. > > Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> > --- > drivers/dma/mediatek/mtk-cqdma.c | 382 ++++++++++----------------------------- > 1 file changed, 93 insertions(+), 289 deletions(-) > > diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c > index 41ef9f1..905bbcb 100644 > --- a/drivers/dma/mediatek/mtk-cqdma.c > +++ b/drivers/dma/mediatek/mtk-cqdma.c > @@ -22,6 +22,7 @@ > #include <linux/of_dma.h> > #include <linux/platform_device.h> > #include <linux/pm_runtime.h> > +#include <linux/preempt.h> why do you need this..? > #include <linux/refcount.h> > #include <linux/slab.h> > > @@ -47,7 +48,6 @@ > #define MTK_CQDMA_SRC 0x1c > #define MTK_CQDMA_DST 0x20 > #define MTK_CQDMA_LEN1 0x24 > -#define MTK_CQDMA_LEN2 0x28 > #define MTK_CQDMA_SRC2 0x60 > #define MTK_CQDMA_DST2 0x64 > > @@ -69,45 +69,32 @@ > * descriptor (CVD) > * @vd: An instance for struct virt_dma_desc > * @len: The total data size device wants to move > - * @residue: The remaining data size device will move > * @dest: The destination address device wants to move to > * @src: The source address device wants to move from > * @ch: The pointer to the corresponding dma channel > - * @node: The lise_head struct to build link-list for VDs > - * @parent: The pointer to the parent CVD > */ > struct mtk_cqdma_vdesc { > struct virt_dma_desc vd; > size_t len; > - size_t residue; > dma_addr_t dest; > dma_addr_t src; > struct dma_chan *ch; > - > - struct list_head node; > - struct mtk_cqdma_vdesc *parent; > }; > > /** > * struct mtk_cqdma_pchan - The struct holding info describing physical > * channel (PC) > - * @queue: Queue for the PDs issued to this PC > + * @active_vdesc: The pointer to the CVD which is under processing > * @base: The mapped register I/O base of this PC > * @irq: The IRQ that this PC are using > * @refcnt: Track how many VCs are using this PC > - * @tasklet: Tasklet for this PC > * @lock: Lock protect agaisting multiple VCs access PC > */ > struct mtk_cqdma_pchan { > - struct list_head queue; > + struct mtk_cqdma_vdesc *active_vdesc; > void __iomem *base; > u32 irq; > - > refcount_t refcnt; > - > - struct tasklet_struct tasklet; > - > - /* lock to protect PC */ > spinlock_t lock; > }; > > @@ -116,14 +103,11 @@ struct mtk_cqdma_pchan { > * channel (VC) > * @vc: An instance for struct virt_dma_chan > * @pc: The pointer to the underlying PC > - * @issue_completion: The wait for all issued descriptors completited > - * @issue_synchronize: Bool indicating channel synchronization starts > */ > struct mtk_cqdma_vchan { > struct virt_dma_chan vc; > struct mtk_cqdma_pchan *pc; > - struct completion issue_completion; > - bool issue_synchronize; > + struct completion cmp; > }; > > /** > @@ -202,22 +186,22 @@ static void mtk_cqdma_vdesc_free(struct virt_dma_desc *vd) > kfree(to_cqdma_vdesc(vd)); > } > > -static int mtk_cqdma_poll_engine_done(struct mtk_cqdma_pchan *pc, bool atomic) > +static int mtk_cqdma_poll_engine_done(struct mtk_cqdma_pchan *pc) > { > u32 status = 0; > > - if (!atomic) > + if (in_task()) > + return readl_poll_timeout_atomic(pc->base + MTK_CQDMA_EN, > + status, > + !(status & MTK_CQDMA_EN_BIT), > + MTK_CQDMA_USEC_POLL, > + MTK_CQDMA_TIMEOUT_POLL); > + else > return readl_poll_timeout(pc->base + MTK_CQDMA_EN, > status, > !(status & MTK_CQDMA_EN_BIT), > MTK_CQDMA_USEC_POLL, > MTK_CQDMA_TIMEOUT_POLL); > - > - return readl_poll_timeout_atomic(pc->base + MTK_CQDMA_EN, > - status, > - !(status & MTK_CQDMA_EN_BIT), > - MTK_CQDMA_USEC_POLL, > - MTK_CQDMA_TIMEOUT_POLL); > } > > static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc) > @@ -225,20 +209,17 @@ static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc) > mtk_dma_set(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT); > mtk_dma_clr(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT); > > - return mtk_cqdma_poll_engine_done(pc, true); > + return mtk_cqdma_poll_engine_done(pc); > } > > static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc, > struct mtk_cqdma_vdesc *cvd) > { > - /* wait for the previous transaction done */ > - if (mtk_cqdma_poll_engine_done(pc, true) < 0) > - dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma wait transaction timeout\n"); > - > /* warm reset the dma engine for the new transaction */ > mtk_dma_set(pc, MTK_CQDMA_RESET, MTK_CQDMA_WARM_RST_BIT); > - if (mtk_cqdma_poll_engine_done(pc, true) < 0) > - dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma warm reset timeout\n"); > + if (mtk_cqdma_poll_engine_done(pc) < 0) > + dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), > + "cqdma warm reset timeout\n"); > > /* setup the source */ > mtk_dma_set(pc, MTK_CQDMA_SRC, cvd->src & MTK_CQDMA_ADDR_LIMIT); > @@ -257,7 +238,8 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc, > #endif > > /* setup the length */ > - mtk_dma_set(pc, MTK_CQDMA_LEN1, cvd->len); > + mtk_dma_set(pc, MTK_CQDMA_LEN1, (cvd->len < MTK_CQDMA_MAX_LEN) ? > + cvd->len : MTK_CQDMA_MAX_LEN); > > /* start dma engine */ > mtk_dma_set(pc, MTK_CQDMA_EN, MTK_CQDMA_EN_BIT); > @@ -265,30 +247,17 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc, > > static void mtk_cqdma_issue_vchan_pending(struct mtk_cqdma_vchan *cvc) > { > - struct virt_dma_desc *vd, *vd2; > + struct virt_dma_desc *vd; > struct mtk_cqdma_pchan *pc = cvc->pc; > - struct mtk_cqdma_vdesc *cvd; > - bool trigger_engine = false; > > lockdep_assert_held(&cvc->vc.lock); > lockdep_assert_held(&pc->lock); > > - list_for_each_entry_safe(vd, vd2, &cvc->vc.desc_issued, node) { > - /* need to trigger dma engine if PC's queue is empty */ > - if (list_empty(&pc->queue)) > - trigger_engine = true; > - > - cvd = to_cqdma_vdesc(vd); > - > - /* add VD into PC's queue */ > - list_add_tail(&cvd->node, &pc->queue); > - > - /* start the dma engine */ > - if (trigger_engine) > - mtk_cqdma_start(pc, cvd); > + vd = vchan_next_desc(&cvc->vc); > > - /* remove VD from list desc_issued */ > - list_del(&vd->node); > + if (vd && !pc->active_vdesc) { > + pc->active_vdesc = to_cqdma_vdesc(vd); > + mtk_cqdma_start(pc, pc->active_vdesc); > } > } > > @@ -298,100 +267,55 @@ static void mtk_cqdma_issue_vchan_pending(struct mtk_cqdma_vchan *cvc) > */ > static bool mtk_cqdma_is_vchan_active(struct mtk_cqdma_vchan *cvc) > { > - struct mtk_cqdma_vdesc *cvd; > - > - list_for_each_entry(cvd, &cvc->pc->queue, node) > - if (cvc == to_cqdma_vchan(cvd->ch)) > - return true; > - > - return false; > + return (!cvc->pc->active_vdesc) ? false : > + (cvc == to_cqdma_vchan(cvc->pc->active_vdesc->ch)); > } > > -/* > - * return the pointer of the CVD that is just consumed by the PC > - */ > -static struct mtk_cqdma_vdesc > -*mtk_cqdma_consume_work_queue(struct mtk_cqdma_pchan *pc) > +static void mtk_cqdma_complete_vdesc(struct mtk_cqdma_pchan *pc) > { > struct mtk_cqdma_vchan *cvc; > - struct mtk_cqdma_vdesc *cvd, *ret = NULL; > - > - /* consume a CVD from PC's queue */ > - cvd = list_first_entry_or_null(&pc->queue, > - struct mtk_cqdma_vdesc, node); > - if (unlikely(!cvd || !cvd->parent)) > - return NULL; > + struct mtk_cqdma_vdesc *cvd; > + struct virt_dma_desc *vd; > + size_t tlen; > > + cvd = pc->active_vdesc; > cvc = to_cqdma_vchan(cvd->ch); > - ret = cvd; > - > - /* update residue of the parent CVD */ > - cvd->parent->residue -= cvd->len; > > - /* delete CVD from PC's queue */ > - list_del(&cvd->node); > + tlen = (cvd->len < MTK_CQDMA_MAX_LEN) ? cvd->len : MTK_CQDMA_MAX_LEN; > + cvd->len -= tlen; > + cvd->src += tlen; > + cvd->dest += tlen; > > spin_lock(&cvc->vc.lock); > > - /* check whether all the child CVDs completed */ > - if (!cvd->parent->residue) { > - /* add the parent VD into list desc_completed */ > - vchan_cookie_complete(&cvd->parent->vd); > + /* check whether the VD completed */ > + if (!cvd->len) { > + /* delete VD from desc_issued */ > + list_del(&cvd->vd.node); > > - /* setup completion if this VC is under synchronization */ > - if (cvc->issue_synchronize && !mtk_cqdma_is_vchan_active(cvc)) { > - complete(&cvc->issue_completion); > - cvc->issue_synchronize = false; > - } > - } > - > - spin_unlock(&cvc->vc.lock); > + /* add the VD into list desc_completed */ > + vchan_cookie_complete(&cvd->vd); > > - /* start transaction for next CVD in the queue */ > - cvd = list_first_entry_or_null(&pc->queue, > - struct mtk_cqdma_vdesc, node); > - if (cvd) > - mtk_cqdma_start(pc, cvd); > - > - return ret; > -} > - > -static void mtk_cqdma_tasklet_cb(struct tasklet_struct *t) > -{ > - struct mtk_cqdma_pchan *pc = from_tasklet(pc, t, tasklet); > - struct mtk_cqdma_vdesc *cvd = NULL; > - unsigned long flags; > - > - spin_lock_irqsave(&pc->lock, flags); > - /* consume the queue */ > - cvd = mtk_cqdma_consume_work_queue(pc); > - spin_unlock_irqrestore(&pc->lock, flags); > - > - /* submit the next CVD */ > - if (cvd) { > - dma_run_dependencies(&cvd->vd.tx); > - > - /* > - * free child CVD after completion. > - * the parent CVD would be freeed with desc_free by user. > - */ > - if (cvd->parent != cvd) > - kfree(cvd); > + /* get the next active VD */ > + vd = vchan_next_desc(&cvc->vc); > + pc->active_vdesc = (!vd) ? NULL : to_cqdma_vdesc(vd); > } > > - /* re-enable interrupt before leaving tasklet */ > - enable_irq(pc->irq); > + /* start the next transaction */ > + if (pc->active_vdesc) > + mtk_cqdma_start(pc, pc->active_vdesc); > + > + spin_unlock(&cvc->vc.lock); > } > > static irqreturn_t mtk_cqdma_irq(int irq, void *devid) > { > struct mtk_cqdma_device *cqdma = devid; > irqreturn_t ret = IRQ_NONE; > - bool schedule_tasklet = false; > u32 i; > > /* clear interrupt flags for each PC */ > - for (i = 0; i < cqdma->dma_channels; ++i, schedule_tasklet = false) { > + for (i = 0; i < cqdma->dma_channels; ++i) { > spin_lock(&cqdma->pc[i]->lock); > if (mtk_dma_read(cqdma->pc[i], > MTK_CQDMA_INT_FLAG) & MTK_CQDMA_INT_FLAG_BIT) { > @@ -399,72 +323,21 @@ static irqreturn_t mtk_cqdma_irq(int irq, void *devid) > mtk_dma_clr(cqdma->pc[i], MTK_CQDMA_INT_FLAG, > MTK_CQDMA_INT_FLAG_BIT); > > - schedule_tasklet = true; > + mtk_cqdma_complete_vdesc(cqdma->pc[i]); > + > ret = IRQ_HANDLED; > } > spin_unlock(&cqdma->pc[i]->lock); > - > - if (schedule_tasklet) { > - /* disable interrupt */ > - disable_irq_nosync(cqdma->pc[i]->irq); > - > - /* schedule the tasklet to handle the transactions */ > - tasklet_schedule(&cqdma->pc[i]->tasklet); > - } > } > > return ret; > } > > -static struct virt_dma_desc *mtk_cqdma_find_active_desc(struct dma_chan *c, > - dma_cookie_t cookie) > -{ > - struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c); > - struct virt_dma_desc *vd; > - unsigned long flags; > - > - spin_lock_irqsave(&cvc->pc->lock, flags); > - list_for_each_entry(vd, &cvc->pc->queue, node) > - if (vd->tx.cookie == cookie) { > - spin_unlock_irqrestore(&cvc->pc->lock, flags); > - return vd; > - } > - spin_unlock_irqrestore(&cvc->pc->lock, flags); > - > - list_for_each_entry(vd, &cvc->vc.desc_issued, node) > - if (vd->tx.cookie == cookie) > - return vd; > - > - return NULL; > -} > - > static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c, > dma_cookie_t cookie, > struct dma_tx_state *txstate) > { > - struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c); > - struct mtk_cqdma_vdesc *cvd; > - struct virt_dma_desc *vd; > - enum dma_status ret; > - unsigned long flags; > - size_t bytes = 0; > - > - ret = dma_cookie_status(c, cookie, txstate); > - if (ret == DMA_COMPLETE || !txstate) > - return ret; > - > - spin_lock_irqsave(&cvc->vc.lock, flags); > - vd = mtk_cqdma_find_active_desc(c, cookie); > - spin_unlock_irqrestore(&cvc->vc.lock, flags); > - > - if (vd) { > - cvd = to_cqdma_vdesc(vd); > - bytes = cvd->residue; > - } > - > - dma_set_residue(txstate, bytes); > - > - return ret; > + return dma_cookie_status(c, cookie, txstate); > } > > static void mtk_cqdma_issue_pending(struct dma_chan *c) > @@ -473,13 +346,17 @@ static void mtk_cqdma_issue_pending(struct dma_chan *c) > unsigned long pc_flags; > unsigned long vc_flags; > > - /* acquire PC's lock before VS's lock for lock dependency in tasklet */ > + /* acquire PC's lock before VC's lock for lock dependency in ISR */ > spin_lock_irqsave(&cvc->pc->lock, pc_flags); > spin_lock_irqsave(&cvc->vc.lock, vc_flags); > > + init_completion(&cvc->cmp); > + > if (vchan_issue_pending(&cvc->vc)) > mtk_cqdma_issue_vchan_pending(cvc); > > + complete(&cvc->cmp); > + > spin_unlock_irqrestore(&cvc->vc.lock, vc_flags); > spin_unlock_irqrestore(&cvc->pc->lock, pc_flags); > } > @@ -488,125 +365,50 @@ static void mtk_cqdma_issue_pending(struct dma_chan *c) > mtk_cqdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, > dma_addr_t src, size_t len, unsigned long flags) > { > - struct mtk_cqdma_vdesc **cvd; > - struct dma_async_tx_descriptor *tx = NULL, *prev_tx = NULL; > - size_t i, tlen, nr_vd; > - > - /* > - * In the case that trsanction length is larger than the > - * DMA engine supports, a single memcpy transaction needs > - * to be separated into several DMA transactions. > - * Each DMA transaction would be described by a CVD, > - * and the first one is referred as the parent CVD, > - * while the others are child CVDs. > - * The parent CVD's tx descriptor is the only tx descriptor > - * returned to the DMA user, and it should not be completed > - * until all the child CVDs completed. > - */ > - nr_vd = DIV_ROUND_UP(len, MTK_CQDMA_MAX_LEN); > - cvd = kcalloc(nr_vd, sizeof(*cvd), GFP_NOWAIT); > + struct mtk_cqdma_vdesc *cvd; > + > + cvd = kzalloc(sizeof(*cvd), GFP_NOWAIT); > if (!cvd) > return NULL; > > - for (i = 0; i < nr_vd; ++i) { > - cvd[i] = kzalloc(sizeof(*cvd[i]), GFP_NOWAIT); > - if (!cvd[i]) { > - for (; i > 0; --i) > - kfree(cvd[i - 1]); > - return NULL; > - } > - > - /* setup dma channel */ > - cvd[i]->ch = c; > - > - /* setup sourece, destination, and length */ > - tlen = (len > MTK_CQDMA_MAX_LEN) ? MTK_CQDMA_MAX_LEN : len; > - cvd[i]->len = tlen; > - cvd[i]->src = src; > - cvd[i]->dest = dest; > - > - /* setup tx descriptor */ > - tx = vchan_tx_prep(to_virt_chan(c), &cvd[i]->vd, flags); > - tx->next = NULL; > + /* setup dma channel */ > + cvd->ch = c; > > - if (!i) { > - cvd[0]->residue = len; > - } else { > - prev_tx->next = tx; > - cvd[i]->residue = tlen; > - } > - > - cvd[i]->parent = cvd[0]; > - > - /* update the src, dest, len, prev_tx for the next CVD */ > - src += tlen; > - dest += tlen; > - len -= tlen; > - prev_tx = tx; > - } > + /* setup sourece, destination, and length */ > + cvd->len = len; > + cvd->src = src; > + cvd->dest = dest; > > - return &cvd[0]->vd.tx; > + return vchan_tx_prep(to_virt_chan(c), &cvd->vd, flags); > } > > -static void mtk_cqdma_free_inactive_desc(struct dma_chan *c) > -{ > - struct virt_dma_chan *vc = to_virt_chan(c); > - unsigned long flags; > - LIST_HEAD(head); > - > - /* > - * set desc_allocated, desc_submitted, > - * and desc_issued as the candicates to be freed > - */ > - spin_lock_irqsave(&vc->lock, flags); > - list_splice_tail_init(&vc->desc_allocated, &head); > - list_splice_tail_init(&vc->desc_submitted, &head); > - list_splice_tail_init(&vc->desc_issued, &head); > - spin_unlock_irqrestore(&vc->lock, flags); > - > - /* free descriptor lists */ > - vchan_dma_desc_free_list(vc, &head); > -} > - > -static void mtk_cqdma_free_active_desc(struct dma_chan *c) > +static int mtk_cqdma_terminate_all(struct dma_chan *c) > { > struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c); > - bool sync_needed = false; > + struct virt_dma_chan *vc = to_virt_chan(c); > unsigned long pc_flags; > unsigned long vc_flags; > + LIST_HEAD(head); > + > + /* wait for the VC to be inactive */ > + if (!wait_for_completion_timeout(&cvc->cmp, msecs_to_jiffies(3000))) > + return -EAGAIN; > > /* acquire PC's lock first due to lock dependency in dma ISR */ > spin_lock_irqsave(&cvc->pc->lock, pc_flags); > spin_lock_irqsave(&cvc->vc.lock, vc_flags); > > - /* synchronization is required if this VC is active */ > - if (mtk_cqdma_is_vchan_active(cvc)) { > - cvc->issue_synchronize = true; > - sync_needed = true; > - } > + /* get VDs from lists */ > + vchan_get_all_descriptors(vc, &head); > + > + /* free all the VDs */ > + vchan_dma_desc_free_list(vc, &head); > > spin_unlock_irqrestore(&cvc->vc.lock, vc_flags); > spin_unlock_irqrestore(&cvc->pc->lock, pc_flags); > > - /* waiting for the completion of this VC */ > - if (sync_needed) > - wait_for_completion(&cvc->issue_completion); > - > - /* free all descriptors in list desc_completed */ > vchan_synchronize(&cvc->vc); > > - WARN_ONCE(!list_empty(&cvc->vc.desc_completed), > - "Desc pending still in list desc_completed\n"); > -} > - > -static int mtk_cqdma_terminate_all(struct dma_chan *c) > -{ > - /* free descriptors not processed yet by hardware */ > - mtk_cqdma_free_inactive_desc(c); > - > - /* free descriptors being processed by hardware */ > - mtk_cqdma_free_active_desc(c); > - > return 0; > } > > @@ -618,7 +420,7 @@ static int mtk_cqdma_alloc_chan_resources(struct dma_chan *c) > u32 i, min_refcnt = U32_MAX, refcnt; > unsigned long flags; > > - /* allocate PC with the minimun refcount */ > + /* allocate PC with the minimum refcount */ > for (i = 0; i < cqdma->dma_channels; ++i) { > refcnt = refcount_read(&cqdma->pc[i]->refcnt); > if (refcnt < min_refcnt) { > @@ -671,8 +473,9 @@ static void mtk_cqdma_free_chan_resources(struct dma_chan *c) > mtk_dma_set(cvc->pc, MTK_CQDMA_FLUSH, MTK_CQDMA_FLUSH_BIT); > > /* wait for the completion of flush operation */ > - if (mtk_cqdma_poll_engine_done(cvc->pc, true) < 0) > - dev_err(cqdma2dev(to_cqdma_dev(c)), "cqdma flush timeout\n"); > + if (mtk_cqdma_poll_engine_done(cvc->pc) < 0) > + dev_err(cqdma2dev(to_cqdma_dev(c)), > + "cqdma flush timeout\n"); > > /* clear the flush bit and interrupt flag */ > mtk_dma_clr(cvc->pc, MTK_CQDMA_FLUSH, MTK_CQDMA_FLUSH_BIT); > @@ -816,10 +619,18 @@ static int mtk_cqdma_probe(struct platform_device *pdev) > if (!cqdma->pc[i]) > return -ENOMEM; > > - INIT_LIST_HEAD(&cqdma->pc[i]->queue); > + cqdma->pc[i]->active_vdesc = NULL; > spin_lock_init(&cqdma->pc[i]->lock); > refcount_set(&cqdma->pc[i]->refcnt, 0); > - cqdma->pc[i]->base = devm_platform_ioremap_resource(pdev, i); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, i); > + if (!res) { > + dev_err(&pdev->dev, "No mem resource for %s\n", > + dev_name(&pdev->dev)); > + return -EINVAL; > + } > + > + cqdma->pc[i]->base = devm_ioremap_resource(&pdev->dev, res); > if (IS_ERR(cqdma->pc[i]->base)) > return PTR_ERR(cqdma->pc[i]->base); > > @@ -852,7 +663,6 @@ static int mtk_cqdma_probe(struct platform_device *pdev) > vc = &cqdma->vc[i]; > vc->vc.desc_free = mtk_cqdma_vdesc_free; > vchan_init(&vc->vc, dd); > - init_completion(&vc->issue_completion); > } > > err = dma_async_device_register(dd); > @@ -876,10 +686,6 @@ static int mtk_cqdma_probe(struct platform_device *pdev) > > platform_set_drvdata(pdev, cqdma); > > - /* initialize tasklet for each PC */ > - for (i = 0; i < cqdma->dma_channels; ++i) > - tasklet_setup(&cqdma->pc[i]->tasklet, mtk_cqdma_tasklet_cb); > - > dev_info(&pdev->dev, "MediaTek CQDMA driver registered\n"); > > return 0; > @@ -914,8 +720,6 @@ static int mtk_cqdma_remove(struct platform_device *pdev) > > /* Waits for any pending IRQ handlers to complete */ > synchronize_irq(cqdma->pc[i]->irq); > - > - tasklet_kill(&cqdma->pc[i]->tasklet); > } > > /* disable hardware */ > -- > 1.9.1 -- ~Vinod ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v8 3/4] dmaengine: mediatek-cqdma: add dma mask for capability 2020-12-23 9:30 [PATCH v8] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL Lee 2020-12-23 9:30 ` [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL Lee 2020-12-23 9:30 ` [PATCH v8 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure EastL Lee @ 2020-12-23 9:30 ` EastL Lee 2020-12-23 9:30 ` [PATCH v8 4/4] dmaengine: mediatek-cqdma: fix compatible EastL Lee 3 siblings, 0 replies; 10+ messages in thread From: EastL Lee @ 2020-12-23 9:30 UTC (permalink / raw) To: Sean Wang Cc: vkoul, robh+dt, mark.rutland, matthias.bgg, dmaengine, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream, cc.hwang, EastL Lee This patch add dma mask for capability. Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> --- drivers/dma/mediatek/mtk-cqdma.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c index 905bbcb..1610632 100644 --- a/drivers/dma/mediatek/mtk-cqdma.c +++ b/drivers/dma/mediatek/mtk-cqdma.c @@ -117,6 +117,7 @@ struct mtk_cqdma_vchan { * @clk: The clock that device internal is using * @dma_requests: The number of VCs the device supports to * @dma_channels: The number of PCs the device supports to + * @dma_mask: A mask for DMA capability * @vc: The pointer to all available VCs * @pc: The pointer to all the underlying PCs */ @@ -126,6 +127,7 @@ struct mtk_cqdma_device { u32 dma_requests; u32 dma_channels; + u32 dma_mask; struct mtk_cqdma_vchan *vc; struct mtk_cqdma_pchan **pc; }; @@ -607,6 +609,21 @@ static int mtk_cqdma_probe(struct platform_device *pdev) cqdma->dma_channels = MTK_CQDMA_NR_PCHANS; } + if (pdev->dev.of_node) + err = of_property_read_u32(pdev->dev.of_node, + "dma-channel-mask", + &cqdma->dma_mask); + if (err) { + dev_warn(&pdev->dev, + "Using 0 as missing dma-channel-mask property\n"); + cqdma->dma_mask = 0; + } + + if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(cqdma->dma_mask))) { + dev_warn(&pdev->dev, "DMA set mask failed\n"); + return -EINVAL; + } + cqdma->pc = devm_kcalloc(&pdev->dev, cqdma->dma_channels, sizeof(*cqdma->pc), GFP_KERNEL); if (!cqdma->pc) -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v8 4/4] dmaengine: mediatek-cqdma: fix compatible 2020-12-23 9:30 [PATCH v8] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL Lee ` (2 preceding siblings ...) 2020-12-23 9:30 ` [PATCH v8 3/4] dmaengine: mediatek-cqdma: add dma mask for capability EastL Lee @ 2020-12-23 9:30 ` EastL Lee 3 siblings, 0 replies; 10+ messages in thread From: EastL Lee @ 2020-12-23 9:30 UTC (permalink / raw) To: Sean Wang Cc: vkoul, robh+dt, mark.rutland, matthias.bgg, dmaengine, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream, cc.hwang, EastL Lee This patch adds common compatible & platform compatiable. Signed-off-by: EastL Lee <EastL.Lee@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> --- drivers/dma/mediatek/mtk-cqdma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c index 1610632..17b3ab9 100644 --- a/drivers/dma/mediatek/mtk-cqdma.c +++ b/drivers/dma/mediatek/mtk-cqdma.c @@ -547,6 +547,7 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma) static const struct of_device_id mtk_cqdma_match[] = { { .compatible = "mediatek,mt6765-cqdma" }, + { .compatible = "mediatek,mt6779-cqdma" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_cqdma_match); -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-01-12 12:14 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-12-23 9:30 [PATCH v8] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL Lee 2020-12-23 9:30 ` [PATCH v8 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL Lee 2021-01-03 16:58 ` Rob Herring 2021-01-06 9:25 ` EastL 2021-01-06 23:53 ` Rob Herring 2021-01-12 12:13 ` Vinod Koul 2020-12-23 9:30 ` [PATCH v8 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure EastL Lee 2021-01-12 12:10 ` Vinod Koul 2020-12-23 9:30 ` [PATCH v8 3/4] dmaengine: mediatek-cqdma: add dma mask for capability EastL Lee 2020-12-23 9:30 ` [PATCH v8 4/4] dmaengine: mediatek-cqdma: fix compatible EastL Lee
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