* [PATCH 1/4] dmaengine: stm32-dma: introduce stm32_dma_sg_inc to manage chan->next_sg
2022-05-05 10:26 [PATCH 0/4] STM32 DMA pause/resume support Amelie Delaunay
@ 2022-05-05 10:26 ` Amelie Delaunay
2022-05-05 10:26 ` [PATCH 2/4] dmaengine: stm32-dma: pass DMA_SxSCR value to stm32_dma_handle_chan_done() Amelie Delaunay
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Amelie Delaunay @ 2022-05-05 10:26 UTC (permalink / raw)
To: Vinod Koul, Maxime Coquelin, Alexandre Torgue
Cc: dmaengine, linux-stm32, linux-arm-kernel, linux-kernel, Amelie Delaunay
chan->next_sg is used to know which transfer will start after the ongoing
one. It is incremented for each new transfer, either on transfer start for
non-cyclic transfers, or on transfer complete interrupt for cyclic
transfers.
For cyclic transfer, when the last item is reached, chan->next_sg must be
reinitialized to the first item.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
---
drivers/dma/stm32-dma.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index d2365fab1b7a..5afe4205f57b 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -535,6 +535,13 @@ static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr);
}
+static void stm32_dma_sg_inc(struct stm32_dma_chan *chan)
+{
+ chan->next_sg++;
+ if (chan->desc->cyclic && (chan->next_sg == chan->desc->num_sgs))
+ chan->next_sg = 0;
+}
+
static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
@@ -575,7 +582,7 @@ static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
- chan->next_sg++;
+ stm32_dma_sg_inc(chan);
/* Clear interrupt status if it is there */
status = stm32_dma_irq_status(chan);
@@ -606,9 +613,6 @@ static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
if (dma_scr & STM32_DMA_SCR_DBM) {
- if (chan->next_sg == chan->desc->num_sgs)
- chan->next_sg = 0;
-
sg_req = &chan->desc->sg_req[chan->next_sg];
if (dma_scr & STM32_DMA_SCR_CT) {
@@ -630,7 +634,7 @@ static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
if (chan->desc) {
if (chan->desc->cyclic) {
vchan_cyclic_callback(&chan->desc->vdesc);
- chan->next_sg++;
+ stm32_dma_sg_inc(chan);
stm32_dma_configure_next_sg(chan);
} else {
chan->busy = false;
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/4] dmaengine: stm32-dma: pass DMA_SxSCR value to stm32_dma_handle_chan_done()
2022-05-05 10:26 [PATCH 0/4] STM32 DMA pause/resume support Amelie Delaunay
2022-05-05 10:26 ` [PATCH 1/4] dmaengine: stm32-dma: introduce stm32_dma_sg_inc to manage chan->next_sg Amelie Delaunay
@ 2022-05-05 10:26 ` Amelie Delaunay
2022-05-05 10:26 ` [PATCH 3/4] dmaengine: stm32-dma: rename pm ops before dma pause/resume introduction Amelie Delaunay
2022-05-05 11:16 ` [PATCH 0/4] STM32 DMA pause/resume support Amelie Delaunay
3 siblings, 0 replies; 7+ messages in thread
From: Amelie Delaunay @ 2022-05-05 10:26 UTC (permalink / raw)
To: Vinod Koul, Maxime Coquelin, Alexandre Torgue
Cc: dmaengine, linux-stm32, linux-arm-kernel, linux-kernel, Amelie Delaunay
stm32_dma_handle_chan_done() is called on Transfer Complete interrupt.
As DMA_SxSCR register is read in interrupt handler, pass the value as
parameter of stm32_dma_handle_chan_done(). Also return directly if
chan->desc is null to remove one ident level.
Then, stm32_dma_configure_next_sg() is doing something only if
Double-Buffer Mode (DBM) is enabled, so, check it is enabled prior calling
stm32_dma_configure_next_sg(), to remove one ident level in
stm32_dma_configure_next_sg().
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
---
drivers/dma/stm32-dma.c | 54 ++++++++++++++++++++---------------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 5afe4205f57b..eecd13795943 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -612,38 +612,38 @@ static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
id = chan->id;
dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
- if (dma_scr & STM32_DMA_SCR_DBM) {
- sg_req = &chan->desc->sg_req[chan->next_sg];
-
- if (dma_scr & STM32_DMA_SCR_CT) {
- dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
- stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
- dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
- stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
- } else {
- dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
- stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
- dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
- stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
- }
+ sg_req = &chan->desc->sg_req[chan->next_sg];
+
+ if (dma_scr & STM32_DMA_SCR_CT) {
+ dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
+ stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
+ dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
+ stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
+ } else {
+ dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
+ stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
+ dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
+ stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
}
}
-static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
+static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan, u32 scr)
{
- if (chan->desc) {
- if (chan->desc->cyclic) {
- vchan_cyclic_callback(&chan->desc->vdesc);
- stm32_dma_sg_inc(chan);
+ if (!chan->desc)
+ return;
+
+ if (chan->desc->cyclic) {
+ vchan_cyclic_callback(&chan->desc->vdesc);
+ stm32_dma_sg_inc(chan);
+ if (scr & STM32_DMA_SCR_DBM)
stm32_dma_configure_next_sg(chan);
- } else {
- chan->busy = false;
- if (chan->next_sg == chan->desc->num_sgs) {
- vchan_cookie_complete(&chan->desc->vdesc);
- chan->desc = NULL;
- }
- stm32_dma_start_transfer(chan);
+ } else {
+ chan->busy = false;
+ if (chan->next_sg == chan->desc->num_sgs) {
+ vchan_cookie_complete(&chan->desc->vdesc);
+ chan->desc = NULL;
}
+ stm32_dma_start_transfer(chan);
}
}
@@ -680,7 +680,7 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
if (status & STM32_DMA_TCI) {
stm32_dma_irq_clear(chan, STM32_DMA_TCI);
if (scr & STM32_DMA_SCR_TCIE)
- stm32_dma_handle_chan_done(chan);
+ stm32_dma_handle_chan_done(chan, scr);
status &= ~STM32_DMA_TCI;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/4] dmaengine: stm32-dma: rename pm ops before dma pause/resume introduction
2022-05-05 10:26 [PATCH 0/4] STM32 DMA pause/resume support Amelie Delaunay
2022-05-05 10:26 ` [PATCH 1/4] dmaengine: stm32-dma: introduce stm32_dma_sg_inc to manage chan->next_sg Amelie Delaunay
2022-05-05 10:26 ` [PATCH 2/4] dmaengine: stm32-dma: pass DMA_SxSCR value to stm32_dma_handle_chan_done() Amelie Delaunay
@ 2022-05-05 10:26 ` Amelie Delaunay
2022-05-05 11:16 ` [PATCH 0/4] STM32 DMA pause/resume support Amelie Delaunay
3 siblings, 0 replies; 7+ messages in thread
From: Amelie Delaunay @ 2022-05-05 10:26 UTC (permalink / raw)
To: Vinod Koul, Maxime Coquelin, Alexandre Torgue
Cc: dmaengine, linux-stm32, linux-arm-kernel, linux-kernel, Amelie Delaunay
dmaengine framework offers device_pause and device_resume ops to pause an
on-going transfer and resume it later.
To avoid any misunderstanding with system sleep pm ops, rename pm ops into
stm32_dma_pm_suspend and stm32_dma_pm_resume.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
---
drivers/dma/stm32-dma.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index eecd13795943..0b35c5178501 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -1486,7 +1486,7 @@ static int stm32_dma_runtime_resume(struct device *dev)
#endif
#ifdef CONFIG_PM_SLEEP
-static int stm32_dma_suspend(struct device *dev)
+static int stm32_dma_pm_suspend(struct device *dev)
{
struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
int id, ret, scr;
@@ -1510,14 +1510,14 @@ static int stm32_dma_suspend(struct device *dev)
return 0;
}
-static int stm32_dma_resume(struct device *dev)
+static int stm32_dma_pm_resume(struct device *dev)
{
return pm_runtime_force_resume(dev);
}
#endif
static const struct dev_pm_ops stm32_dma_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_suspend, stm32_dma_resume)
+ SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_pm_suspend, stm32_dma_pm_resume)
SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend,
stm32_dma_runtime_resume, NULL)
};
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 0/4] STM32 DMA pause/resume support
2022-05-05 10:26 [PATCH 0/4] STM32 DMA pause/resume support Amelie Delaunay
` (2 preceding siblings ...)
2022-05-05 10:26 ` [PATCH 3/4] dmaengine: stm32-dma: rename pm ops before dma pause/resume introduction Amelie Delaunay
@ 2022-05-05 11:16 ` Amelie Delaunay
3 siblings, 0 replies; 7+ messages in thread
From: Amelie Delaunay @ 2022-05-05 11:16 UTC (permalink / raw)
To: Vinod Koul, Maxime Coquelin, Alexandre Torgue
Cc: dmaengine, linux-stm32, linux-arm-kernel, linux-kernel
Please drop this series, truncated :(
On 5/5/22 12:26, Amelie Delaunay wrote:
> This patchset introduces pause/resume support in stm32-dma driver.
> [1/4], [2/4] and [3/4] ease the introduction of device_pause/device_resume
> ops management in [4/4].
>
> Amelie Delaunay (4):
> dmaengine: stm32-dma: introduce stm32_dma_sg_inc to manage
> chan->next_sg
> dmaengine: stm32-dma: pass DMA_SxSCR value to
> stm32_dma_handle_chan_done()
> dmaengine: stm32-dma: rename pm ops before dma pause/resume
> introduction
> dmaengine: stm32-dma: add device_pause/device_resume support
>
> drivers/dma/stm32-dma.c | 311 ++++++++++++++++++++++++++++++++++------
> 1 file changed, 268 insertions(+), 43 deletions(-)
>
^ permalink raw reply [flat|nested] 7+ messages in thread