From: Serge Semin <fancer.lancer@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Vinod Koul" <vkoul@kernel.org>, "Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Frank Li" <Frank.Li@nxp.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
"Pavel Parkhomenko" <Pavel.Parkhomenko@baikalelectronics.ru>,
linux-pci@vger.kernel.org, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RESEND v5 24/24] PCI: dwc: Add DW eDMA engine support
Date: Wed, 24 Aug 2022 21:13:19 +0300 [thread overview]
Message-ID: <20220824181319.wkj4256a5jp2xjlp@mobilestation> (raw)
In-Reply-To: <20220824165118.GA2785269@bhelgaas>
On Wed, Aug 24, 2022 at 11:51:18AM -0500, Bjorn Helgaas wrote:
> On Mon, Aug 22, 2022 at 09:53:32PM +0300, Serge Semin wrote:
> > Since the DW eDMA driver now supports eDMA controllers embedded into the
> > locally accessible DW PCIe Root Ports and Endpoints, we can use the
> > updated interface to register DW eDMA as DMA engine device if it's
> > available. In order to successfully do that the DW PCIe core driver need
> > to perform some preparations first. First of all it needs to find out the
> > eDMA controller CSRs base address, whether they are accessible over the
> > Port Logic or iATU unrolled space. Afterwards it can try to auto-detect
> > the eDMA controller availability and number of it's read/write channels.
>
> s/it's//
Ok.
>
> > If none was found the procedure will just silently halt with no error
> > returned. Secondly the platform is supposed to provide either combined or
> > per-channel IRQ signals. If no valid IRQs set is found the procedure will
> > also halt with no error returned so to be backward compatible with the
> > platforms where DW PCIe controllers have eDMA embedded but lack of the
> > IRQs defined for them. Finally before actually probing the eDMA device we
> > need to allocate LLP items buffers. After that the DW eDMA can be
> > registered. If registration is successful the info-message regarding the
> > number of detected Read/Write eDMA channels will be printed to the system
> > log in the similar way as it's done for the iATU settings.
>
> s/in the similar way as it's done/as is done/
Ok
>
> > +static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
> > +{
> > + u32 val;
> > +
> > + val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> > + if (val == 0xFFFFFFFF && pci->edma.reg_base) {
> > + pci->edma.mf = EDMA_MF_EDMA_UNROLL;
> > +
> > + val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
> > + } else if (val != 0xFFFFFFFF) {
>
> Consider PCI_POSSIBLE_ERROR() as an annotation about the meaning of
> 0xFFFFFFFF and something to grep for.
In this case FFs don't mean an error but a special value, which
indicates that the eDMA is mapped via the unrolled CSRs space. The
similar approach has been implemented for the iATU legacy/unroll setup
auto-detection. So I don't see much reasons to have it grepped, so as
to have a macro-based parametrization since the special value will
unluckily change while having the explicit literal utilized gives a
better understanding of the way the algorithm works.
>
> > + pci->edma.mf = EDMA_MF_EDMA_LEGACY;
> > +
> > + pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE;
> > + } else {
> > + return -ENODEV;
> > + }
>
> > + * eDMA CSRs. DW PCIe IP-core v4.70a and older had the eDMA registers accessible
> > + * over the Port Logic registers space. Afterwords the unrolled mapping was
>
> s/Afterwords/Afterwards/
Ok.
-Sergey
>
> > + * introduced so eDMA and iATU could be accessed via a dedicated registers
> > + * space.
next prev parent reply other threads:[~2022-08-24 18:13 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-22 18:53 [PATCH RESEND v5 00/24] dmaengine: dw-edma: Add RP/EP local DMA controllers support Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 01/24] dmaengine: Fix dma_slave_config.dst_addr description Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 02/24] dmaengine: dw-edma: Release requested IRQs on failure Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 03/24] dmaengine: dw-edma: Convert ll/dt phys-address to PCIe bus/DMA address Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 04/24] dmaengine: dw-edma: Fix missing src/dst address of the interleaved xfers Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 05/24] dmaengine: dw-edma: Don't permit non-inc " Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 06/24] dmaengine: dw-edma: Fix invalid interleaved xfers semantics Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 07/24] dmaengine: dw-edma: Add CPU to PCIe bus address translation Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 08/24] dmaengine: dw-edma: Add PCIe bus address getter to the remote EP glue-driver Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 09/24] dmaengine: dw-edma: Drop chancnt initialization Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 10/24] dmaengine: dw-edma: Fix DebugFS reg entry type Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 11/24] dmaengine: dw-edma: Stop checking debugfs_create_*() return value Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 12/24] dmaengine: dw-edma: Add dw_edma prefix to the DebugFS nodes descriptor Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 13/24] dmaengine: dw-edma: Convert DebugFS descs to being kz-allocated Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 14/24] dmaengine: dw-edma: Rename DebugFS dentry variables to 'dent' Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 15/24] dmaengine: dw-edma: Simplify the DebugFS context CSRs init procedure Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 16/24] dmaengine: dw-edma: Move eDMA data pointer to DebugFS node descriptor Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 17/24] dmaengine: dw-edma: Join Write/Read channels into a single device Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 18/24] dmaengine: dw-edma: Use DMA-engine device DebugFS subdirectory Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 19/24] dmaengine: dw-edma: Use non-atomic io-64 methods Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 20/24] dmaengine: dw-edma: Drop DT-region allocation Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 21/24] dmaengine: dw-edma: Replace chip ID number with device name Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 22/24] dmaengine: dw-edma: Bypass dma-ranges mapping for the local setup Serge Semin
2022-08-31 9:17 ` Robin Murphy
2022-09-12 1:24 ` Serge Semin
2022-09-26 14:08 ` Robin Murphy
2022-09-27 10:48 ` Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 23/24] dmaengine: dw-edma: Skip cleanup procedure if no private data found Serge Semin
2022-08-22 18:53 ` [PATCH RESEND v5 24/24] PCI: dwc: Add DW eDMA engine support Serge Semin
2022-08-23 15:49 ` Manivannan Sadhasivam
2022-08-24 14:22 ` Serge Semin
2022-08-24 16:51 ` Bjorn Helgaas
2022-08-24 18:13 ` Serge Semin [this message]
2022-08-24 18:17 ` Bjorn Helgaas
2022-08-25 5:16 ` Serge Semin
2022-08-25 16:04 ` Bjorn Helgaas
2022-08-25 17:06 ` Serge Semin
2022-08-23 15:45 ` [PATCH RESEND v5 00/24] dmaengine: dw-edma: Add RP/EP local DMA controllers support Manivannan Sadhasivam
2022-08-24 14:07 ` Serge Semin
2022-08-25 4:42 ` Vinod Koul
2022-08-25 5:04 ` Serge Semin
2022-08-25 8:44 ` Vinod Koul
2022-08-25 11:28 ` Serge Semin
2022-08-24 16:39 ` Bjorn Helgaas
2022-08-24 18:00 ` Serge Semin
2022-10-25 7:59 ` Manivannan Sadhasivam
2022-10-25 20:50 ` Serge Semin
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