* [PATCH v6 1/4] dt-bindings: dma: snps,dw-axi-dmac: constrain the items of resets for JH7110 dma
2023-03-22 9:48 [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC Walker Chen
@ 2023-03-22 9:48 ` Walker Chen
2023-03-22 9:48 ` [PATCH v6 2/4] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA Walker Chen
` (3 subsequent siblings)
4 siblings, 0 replies; 13+ messages in thread
From: Walker Chen @ 2023-03-22 9:48 UTC (permalink / raw)
To: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, Walker Chen
Cc: dmaengine, devicetree, linux-kernel, linux-riscv
The DMA controller needs two reset items to work properly on JH7110 SoC,
so there is need to constrain the items' value to 2, other platforms
have 1 reset item at most.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
---
.../bindings/dma/snps,dw-axi-dmac.yaml | 23 ++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 5c81194e2300..363cf8bd150d 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -20,6 +20,7 @@ properties:
enum:
- snps,axi-dma-1.01a
- intel,kmb-axi-dma
+ - starfive,jh7110-axi-dma
reg:
minItems: 1
@@ -58,7 +59,8 @@ properties:
maximum: 8
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
snps,dma-masters:
description: |
@@ -109,6 +111,25 @@ required:
- snps,priority
- snps,block-size
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jh7110-axi-dma
+then:
+ properties:
+ resets:
+ minItems: 2
+ items:
+ - description: AXI reset line
+ - description: AHB reset line
+ - description: module reset
+else:
+ properties:
+ resets:
+ maxItems: 1
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 2/4] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA
2023-03-22 9:48 [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC Walker Chen
2023-03-22 9:48 ` [PATCH v6 1/4] dt-bindings: dma: snps,dw-axi-dmac: constrain the items of resets for JH7110 dma Walker Chen
@ 2023-03-22 9:48 ` Walker Chen
2023-03-24 13:33 ` Emil Renner Berthing
2023-03-31 12:04 ` Vinod Koul
2023-03-22 9:48 ` [PATCH v6 3/4] dmaengine: dw-axi-dmac: Increase polling time to DMA transmission completion status Walker Chen
` (2 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Walker Chen @ 2023-03-22 9:48 UTC (permalink / raw)
To: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, Walker Chen
Cc: dmaengine, devicetree, linux-kernel, linux-riscv
Add DMA reset operation in device probe and use different configuration
on CH_CFG registers according to match data. Update all uses of
of_device_is_compatible with of_device_get_match_data.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 4169e1d7d5ca..6cfcb541d8c3 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -21,10 +21,12 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/of_dma.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/types.h>
@@ -46,6 +48,10 @@
DMA_SLAVE_BUSWIDTH_32_BYTES | \
DMA_SLAVE_BUSWIDTH_64_BYTES)
+#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
+#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
+#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
+
static inline void
axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
{
@@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
- if (chan->chip->dw->hdata->reg_map_8_channels) {
+ if (chan->chip->dw->hdata->reg_map_8_channels &&
+ !chan->chip->dw->hdata->use_cfg2) {
cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
@@ -1367,10 +1374,11 @@ static int parse_device_properties(struct axi_dma_chip *chip)
static int dw_probe(struct platform_device *pdev)
{
- struct device_node *node = pdev->dev.of_node;
struct axi_dma_chip *chip;
struct dw_axi_dma *dw;
struct dw_axi_dma_hcfg *hdata;
+ struct reset_control *resets;
+ unsigned int flags;
u32 i;
int ret;
@@ -1398,12 +1406,25 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
- if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+ flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
+ if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(chip->apb_regs))
return PTR_ERR(chip->apb_regs);
}
+ if (flags & AXI_DMA_FLAG_HAS_RESETS) {
+ resets = devm_reset_control_array_get_exclusive(&pdev->dev);
+ if (IS_ERR(resets))
+ return PTR_ERR(resets);
+
+ ret = reset_control_deassert(resets);
+ if (ret)
+ return ret;
+ }
+
+ chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
@@ -1554,8 +1575,15 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
};
static const struct of_device_id dw_dma_of_id_table[] = {
- { .compatible = "snps,axi-dma-1.01a" },
- { .compatible = "intel,kmb-axi-dma" },
+ {
+ .compatible = "snps,axi-dma-1.01a"
+ }, {
+ .compatible = "intel,kmb-axi-dma",
+ .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
+ }, {
+ .compatible = "starfive,jh7110-axi-dma",
+ .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
+ },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index e9d5eb0fd594..eb267cb24f67 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
/* Register map for DMAX_NUM_CHANNELS <= 8 */
bool reg_map_8_channels;
bool restrict_axi_burst_len;
+ bool use_cfg2;
};
struct axi_dma_chan {
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/4] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA
2023-03-22 9:48 ` [PATCH v6 2/4] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA Walker Chen
@ 2023-03-24 13:33 ` Emil Renner Berthing
2023-03-31 12:04 ` Vinod Koul
1 sibling, 0 replies; 13+ messages in thread
From: Emil Renner Berthing @ 2023-03-24 13:33 UTC (permalink / raw)
To: Walker Chen
Cc: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, dmaengine, devicetree,
linux-kernel, linux-riscv
On Wed, 22 Mar 2023 at 10:48, Walker Chen <walker.chen@starfivetech.com> wrote:
>
> Add DMA reset operation in device probe and use different configuration
> on CH_CFG registers according to match data. Update all uses of
> of_device_is_compatible with of_device_get_match_data.
>
> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Thanks!
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> ---
> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
> 2 files changed, 34 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index 4169e1d7d5ca..6cfcb541d8c3 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -21,10 +21,12 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/of_dma.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/types.h>
>
> @@ -46,6 +48,10 @@
> DMA_SLAVE_BUSWIDTH_32_BYTES | \
> DMA_SLAVE_BUSWIDTH_64_BYTES)
>
> +#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
> +#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
> +#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
> +
> static inline void
> axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
> {
> @@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>
> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
> - if (chan->chip->dw->hdata->reg_map_8_channels) {
> + if (chan->chip->dw->hdata->reg_map_8_channels &&
> + !chan->chip->dw->hdata->use_cfg2) {
> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
> @@ -1367,10 +1374,11 @@ static int parse_device_properties(struct axi_dma_chip *chip)
>
> static int dw_probe(struct platform_device *pdev)
> {
> - struct device_node *node = pdev->dev.of_node;
> struct axi_dma_chip *chip;
> struct dw_axi_dma *dw;
> struct dw_axi_dma_hcfg *hdata;
> + struct reset_control *resets;
> + unsigned int flags;
> u32 i;
> int ret;
>
> @@ -1398,12 +1406,25 @@ static int dw_probe(struct platform_device *pdev)
> if (IS_ERR(chip->regs))
> return PTR_ERR(chip->regs);
>
> - if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
> + flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
> + if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
> chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
> if (IS_ERR(chip->apb_regs))
> return PTR_ERR(chip->apb_regs);
> }
>
> + if (flags & AXI_DMA_FLAG_HAS_RESETS) {
> + resets = devm_reset_control_array_get_exclusive(&pdev->dev);
> + if (IS_ERR(resets))
> + return PTR_ERR(resets);
> +
> + ret = reset_control_deassert(resets);
> + if (ret)
> + return ret;
> + }
> +
> + chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
> +
> chip->core_clk = devm_clk_get(chip->dev, "core-clk");
> if (IS_ERR(chip->core_clk))
> return PTR_ERR(chip->core_clk);
> @@ -1554,8 +1575,15 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
> };
>
> static const struct of_device_id dw_dma_of_id_table[] = {
> - { .compatible = "snps,axi-dma-1.01a" },
> - { .compatible = "intel,kmb-axi-dma" },
> + {
> + .compatible = "snps,axi-dma-1.01a"
> + }, {
> + .compatible = "intel,kmb-axi-dma",
> + .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
> + }, {
> + .compatible = "starfive,jh7110-axi-dma",
> + .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index e9d5eb0fd594..eb267cb24f67 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
> /* Register map for DMAX_NUM_CHANNELS <= 8 */
> bool reg_map_8_channels;
> bool restrict_axi_burst_len;
> + bool use_cfg2;
> };
>
> struct axi_dma_chan {
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/4] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA
2023-03-22 9:48 ` [PATCH v6 2/4] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA Walker Chen
2023-03-24 13:33 ` Emil Renner Berthing
@ 2023-03-31 12:04 ` Vinod Koul
2023-04-03 12:07 ` Walker Chen
1 sibling, 1 reply; 13+ messages in thread
From: Vinod Koul @ 2023-03-31 12:04 UTC (permalink / raw)
To: Walker Chen
Cc: Eugeniy Paltsev, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Palmer Dabbelt, Emil Renner Berthing, dmaengine, devicetree,
linux-kernel, linux-riscv
On 22-03-23, 17:48, Walker Chen wrote:
> Add DMA reset operation in device probe and use different configuration
> on CH_CFG registers according to match data. Update all uses of
> of_device_is_compatible with of_device_get_match_data.
>
> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
> ---
> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
> 2 files changed, 34 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index 4169e1d7d5ca..6cfcb541d8c3 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -21,10 +21,12 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/of_dma.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/types.h>
>
> @@ -46,6 +48,10 @@
> DMA_SLAVE_BUSWIDTH_32_BYTES | \
> DMA_SLAVE_BUSWIDTH_64_BYTES)
>
> +#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
> +#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
> +#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
> +
> static inline void
> axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
> {
> @@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>
> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
> - if (chan->chip->dw->hdata->reg_map_8_channels) {
> + if (chan->chip->dw->hdata->reg_map_8_channels &&
> + !chan->chip->dw->hdata->use_cfg2) {
I think this will break existing users..
This is set for reg_map_8_channels && use_cfg2, latter being set only
for new controller, so what about existing users of these bits?
> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
> @@ -1367,10 +1374,11 @@ static int parse_device_properties(struct axi_dma_chip *chip)
>
> static int dw_probe(struct platform_device *pdev)
> {
> - struct device_node *node = pdev->dev.of_node;
> struct axi_dma_chip *chip;
> struct dw_axi_dma *dw;
> struct dw_axi_dma_hcfg *hdata;
> + struct reset_control *resets;
> + unsigned int flags;
> u32 i;
> int ret;
>
> @@ -1398,12 +1406,25 @@ static int dw_probe(struct platform_device *pdev)
> if (IS_ERR(chip->regs))
> return PTR_ERR(chip->regs);
>
> - if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
> + flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
> + if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
> chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
> if (IS_ERR(chip->apb_regs))
> return PTR_ERR(chip->apb_regs);
> }
>
> + if (flags & AXI_DMA_FLAG_HAS_RESETS) {
> + resets = devm_reset_control_array_get_exclusive(&pdev->dev);
> + if (IS_ERR(resets))
> + return PTR_ERR(resets);
> +
> + ret = reset_control_deassert(resets);
> + if (ret)
> + return ret;
> + }
> +
> + chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
> +
> chip->core_clk = devm_clk_get(chip->dev, "core-clk");
> if (IS_ERR(chip->core_clk))
> return PTR_ERR(chip->core_clk);
> @@ -1554,8 +1575,15 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
> };
>
> static const struct of_device_id dw_dma_of_id_table[] = {
> - { .compatible = "snps,axi-dma-1.01a" },
> - { .compatible = "intel,kmb-axi-dma" },
> + {
> + .compatible = "snps,axi-dma-1.01a"
> + }, {
> + .compatible = "intel,kmb-axi-dma",
> + .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
> + }, {
> + .compatible = "starfive,jh7110-axi-dma",
> + .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index e9d5eb0fd594..eb267cb24f67 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
> /* Register map for DMAX_NUM_CHANNELS <= 8 */
> bool reg_map_8_channels;
> bool restrict_axi_burst_len;
> + bool use_cfg2;
> };
>
> struct axi_dma_chan {
> --
> 2.17.1
--
~Vinod
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/4] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA
2023-03-31 12:04 ` Vinod Koul
@ 2023-04-03 12:07 ` Walker Chen
0 siblings, 0 replies; 13+ messages in thread
From: Walker Chen @ 2023-04-03 12:07 UTC (permalink / raw)
To: Vinod Koul
Cc: Eugeniy Paltsev, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Palmer Dabbelt, Emil Renner Berthing, dmaengine, devicetree,
linux-kernel, linux-riscv
On 2023/3/31 20:04, Vinod Koul wrote:
> On 22-03-23, 17:48, Walker Chen wrote:
>> Add DMA reset operation in device probe and use different configuration
>> on CH_CFG registers according to match data. Update all uses of
>> of_device_is_compatible with of_device_get_match_data.
>>
>> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
>> ---
>> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
>> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
>> 2 files changed, 34 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> index 4169e1d7d5ca..6cfcb541d8c3 100644
>> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> @@ -21,10 +21,12 @@
>> #include <linux/kernel.h>
>> #include <linux/module.h>
>> #include <linux/of.h>
>> +#include <linux/of_device.h>
>> #include <linux/of_dma.h>
>> #include <linux/platform_device.h>
>> #include <linux/pm_runtime.h>
>> #include <linux/property.h>
>> +#include <linux/reset.h>
>> #include <linux/slab.h>
>> #include <linux/types.h>
>>
>> @@ -46,6 +48,10 @@
>> DMA_SLAVE_BUSWIDTH_32_BYTES | \
>> DMA_SLAVE_BUSWIDTH_64_BYTES)
>>
>> +#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
>> +#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
>> +#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
>> +
>> static inline void
>> axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
>> {
>> @@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>>
>> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
>> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
>> - if (chan->chip->dw->hdata->reg_map_8_channels) {
>> + if (chan->chip->dw->hdata->reg_map_8_channels &&
>> + !chan->chip->dw->hdata->use_cfg2) {
>
> I think this will break existing users..
>
> This is set for reg_map_8_channels && use_cfg2, latter being set only
> for new controller, so what about existing users of these bits?
Firstly thank you for your comments!
There is a statement 'use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);' to be added in dw_probe function.
Assuming older/existing platform run this code block, e.g. when compatible is "snps,axi-dma-1.01a",
the value of variable 'use_cfg2' is still false, the original logic will not be broken. So other existing
users are not affected by this.
Looking forward to your more comments. Thanks!
Best regards,
Walker
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 3/4] dmaengine: dw-axi-dmac: Increase polling time to DMA transmission completion status
2023-03-22 9:48 [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC Walker Chen
2023-03-22 9:48 ` [PATCH v6 1/4] dt-bindings: dma: snps,dw-axi-dmac: constrain the items of resets for JH7110 dma Walker Chen
2023-03-22 9:48 ` [PATCH v6 2/4] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA Walker Chen
@ 2023-03-22 9:48 ` Walker Chen
2023-03-22 9:48 ` [PATCH v6 4/4] riscv: dts: starfive: add dma controller node Walker Chen
2023-04-12 17:27 ` [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC Vinod Koul
4 siblings, 0 replies; 13+ messages in thread
From: Walker Chen @ 2023-03-22 9:48 UTC (permalink / raw)
To: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, Walker Chen
Cc: dmaengine, devicetree, linux-kernel, linux-riscv
The bit DMAC_CHEN[0] is automatically cleared by hardware to disable the
channel after the last AMBA transfer of the DMA transfer to the
destination has completed. Software can therefore poll this bit to
determine when this channel is free for a new DMA transfer.
This time requires at least 40 milliseconds on JH7110 SoC, otherwise an
error message 'failed to stop' will be reported.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 6cfcb541d8c3..6937cc0c0b65 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1147,7 +1147,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
axi_chan_disable(chan);
ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
- !(val & chan_active), 1000, 10000);
+ !(val & chan_active), 1000, 50000);
if (ret == -ETIMEDOUT)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 4/4] riscv: dts: starfive: add dma controller node
2023-03-22 9:48 [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC Walker Chen
` (2 preceding siblings ...)
2023-03-22 9:48 ` [PATCH v6 3/4] dmaengine: dw-axi-dmac: Increase polling time to DMA transmission completion status Walker Chen
@ 2023-03-22 9:48 ` Walker Chen
2023-07-01 22:01 ` Aurelien Jarno
2023-04-12 17:27 ` [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC Vinod Koul
4 siblings, 1 reply; 13+ messages in thread
From: Walker Chen @ 2023-03-22 9:48 UTC (permalink / raw)
To: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, Walker Chen
Cc: dmaengine, devicetree, linux-kernel, linux-riscv
Add the dma controller node for the Starfive JH7110 SoC.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 17220576b21c..b503b6137743 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -510,6 +510,24 @@
#gpio-cells = <2>;
};
+ dma: dma-controller@16050000 {
+ compatible = "starfive,jh7110-axi-dma";
+ reg = <0x0 0x16050000 0x0 0x10000>;
+ clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
+ <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
+ clock-names = "core-clk", "cfgr-clk";
+ resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
+ <&stgcrg JH7110_STGRST_DMA1P_AHB>;
+ interrupts = <73>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <3>;
+ snps,block-size = <65536 65536 65536 65536>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v6 4/4] riscv: dts: starfive: add dma controller node
2023-03-22 9:48 ` [PATCH v6 4/4] riscv: dts: starfive: add dma controller node Walker Chen
@ 2023-07-01 22:01 ` Aurelien Jarno
2023-07-01 23:03 ` Conor Dooley
2023-07-03 1:35 ` Walker Chen
0 siblings, 2 replies; 13+ messages in thread
From: Aurelien Jarno @ 2023-07-01 22:01 UTC (permalink / raw)
To: Walker Chen
Cc: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, dmaengine,
devicetree, linux-kernel, linux-riscv
On 2023-03-22 17:48, Walker Chen wrote:
> Add the dma controller node for the Starfive JH7110 SoC.
>
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 17220576b21c..b503b6137743 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -510,6 +510,24 @@
> #gpio-cells = <2>;
> };
>
> + dma: dma-controller@16050000 {
> + compatible = "starfive,jh7110-axi-dma";
> + reg = <0x0 0x16050000 0x0 0x10000>;
> + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
> + <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
> + clock-names = "core-clk", "cfgr-clk";
> + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
> + <&stgcrg JH7110_STGRST_DMA1P_AHB>;
> + interrupts = <73>;
> + #dma-cells = <1>;
> + dma-channels = <4>;
> + snps,dma-masters = <1>;
> + snps,data-width = <3>;
> + snps,block-size = <65536 65536 65536 65536>;
> + snps,priority = <0 1 2 3>;
> + snps,axi-max-burst-len = <16>;
> + };
> +
> aoncrg: clock-controller@17000000 {
> compatible = "starfive,jh7110-aoncrg";
> reg = <0x0 0x17000000 0x0 0x10000>;
It appears that this patch has never been applied, although the rest of
the series has already been merged. Unfortunately it doesn't apply
anymore due to other changes to that file.
Could you please rebase and repost it?
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://aurel32.net
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 4/4] riscv: dts: starfive: add dma controller node
2023-07-01 22:01 ` Aurelien Jarno
@ 2023-07-01 23:03 ` Conor Dooley
2023-07-03 1:35 ` Walker Chen
1 sibling, 0 replies; 13+ messages in thread
From: Conor Dooley @ 2023-07-01 23:03 UTC (permalink / raw)
To: Walker Chen, Eugeniy Paltsev, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt,
Emil Renner Berthing, dmaengine, devicetree, linux-kernel,
linux-riscv
[-- Attachment #1: Type: text/plain, Size: 1904 bytes --]
On Sun, Jul 02, 2023 at 12:01:29AM +0200, Aurelien Jarno wrote:
> On 2023-03-22 17:48, Walker Chen wrote:
> > Add the dma controller node for the Starfive JH7110 SoC.
> >
> > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 17220576b21c..b503b6137743 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -510,6 +510,24 @@
> > #gpio-cells = <2>;
> > };
> >
> > + dma: dma-controller@16050000 {
> > + compatible = "starfive,jh7110-axi-dma";
> > + reg = <0x0 0x16050000 0x0 0x10000>;
> > + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
> > + <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
> > + clock-names = "core-clk", "cfgr-clk";
> > + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
> > + <&stgcrg JH7110_STGRST_DMA1P_AHB>;
> > + interrupts = <73>;
> > + #dma-cells = <1>;
> > + dma-channels = <4>;
> > + snps,dma-masters = <1>;
> > + snps,data-width = <3>;
> > + snps,block-size = <65536 65536 65536 65536>;
> > + snps,priority = <0 1 2 3>;
> > + snps,axi-max-burst-len = <16>;
> > + };
> > +
> > aoncrg: clock-controller@17000000 {
> > compatible = "starfive,jh7110-aoncrg";
> > reg = <0x0 0x17000000 0x0 0x10000>;
>
> It appears that this patch has never been applied, although the rest of
> the series has already been merged.
Correct. I can't apply it because the stgcrg it depends on is still
pending.
> Unfortunately it doesn't apply
> anymore due to other changes to that file.
>
> Could you please rebase and repost it?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 4/4] riscv: dts: starfive: add dma controller node
2023-07-01 22:01 ` Aurelien Jarno
2023-07-01 23:03 ` Conor Dooley
@ 2023-07-03 1:35 ` Walker Chen
1 sibling, 0 replies; 13+ messages in thread
From: Walker Chen @ 2023-07-03 1:35 UTC (permalink / raw)
To: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, dmaengine,
devicetree, linux-kernel, linux-riscv
On 2023/7/2 6:01, Aurelien Jarno wrote:
> On 2023-03-22 17:48, Walker Chen wrote:
>> Add the dma controller node for the Starfive JH7110 SoC.
>>
>> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 17220576b21c..b503b6137743 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -510,6 +510,24 @@
>> #gpio-cells = <2>;
>> };
>>
>> + dma: dma-controller@16050000 {
>> + compatible = "starfive,jh7110-axi-dma";
>> + reg = <0x0 0x16050000 0x0 0x10000>;
>> + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
>> + <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
>> + clock-names = "core-clk", "cfgr-clk";
>> + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
>> + <&stgcrg JH7110_STGRST_DMA1P_AHB>;
>> + interrupts = <73>;
>> + #dma-cells = <1>;
>> + dma-channels = <4>;
>> + snps,dma-masters = <1>;
>> + snps,data-width = <3>;
>> + snps,block-size = <65536 65536 65536 65536>;
>> + snps,priority = <0 1 2 3>;
>> + snps,axi-max-burst-len = <16>;
>> + };
>> +
>> aoncrg: clock-controller@17000000 {
>> compatible = "starfive,jh7110-aoncrg";
>> reg = <0x0 0x17000000 0x0 0x10000>;
>
> It appears that this patch has never been applied, although the rest of
> the series has already been merged. Unfortunately it doesn't apply
> anymore due to other changes to that file.
>
> Could you please rebase and repost it?
>
Of course I will repost it, but this depends on whether the stg clock is merged.
Regards,
Walker
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC
2023-03-22 9:48 [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC Walker Chen
` (3 preceding siblings ...)
2023-03-22 9:48 ` [PATCH v6 4/4] riscv: dts: starfive: add dma controller node Walker Chen
@ 2023-04-12 17:27 ` Vinod Koul
2023-04-13 1:29 ` Walker Chen
4 siblings, 1 reply; 13+ messages in thread
From: Vinod Koul @ 2023-04-12 17:27 UTC (permalink / raw)
To: Walker Chen
Cc: Eugeniy Paltsev, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Palmer Dabbelt, Emil Renner Berthing, dmaengine, devicetree,
linux-kernel, linux-riscv
On 22-03-23, 17:48, Walker Chen wrote:
> Hello,
>
> This patch series adds dma support for the StarFive JH7110 RISC-V
> SoC. The first patch adds device tree binding. The second patch includes
> dma driver. The last patch adds device node of dma to JH7110 dts.
>
> The series has been tested on the VisionFive 2 board which equip with
> JH7110 SoC and works normally.
Applied 1-3, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC
2023-04-12 17:27 ` [PATCH v6 0/4] Add DMA driver for StarFive JH7110 SoC Vinod Koul
@ 2023-04-13 1:29 ` Walker Chen
0 siblings, 0 replies; 13+ messages in thread
From: Walker Chen @ 2023-04-13 1:29 UTC (permalink / raw)
To: Vinod Koul
Cc: Eugeniy Paltsev, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Palmer Dabbelt, Emil Renner Berthing, dmaengine, devicetree,
linux-kernel, linux-riscv
On 2023/4/13 1:27, Vinod Koul wrote:
> On 22-03-23, 17:48, Walker Chen wrote:
>> Hello,
>>
>> This patch series adds dma support for the StarFive JH7110 RISC-V
>> SoC. The first patch adds device tree binding. The second patch includes
>> dma driver. The last patch adds device node of dma to JH7110 dts.
>>
>> The series has been tested on the VisionFive 2 board which equip with
>> JH7110 SoC and works normally.
>
> Applied 1-3, thanks
>
Vinod, thank you very much!
Best regards,
Walker
^ permalink raw reply [flat|nested] 13+ messages in thread