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* [PATCH] Remove incorrect hard coded cache coherrency setting
@ 2023-06-15 22:43 Zhanjun Dong
  2023-06-16  7:39 ` [Intel-gfx] " Nirmoy Das
  0 siblings, 1 reply; 2+ messages in thread
From: Zhanjun Dong @ 2023-06-15 22:43 UTC (permalink / raw)
  To: intel-gfx, dri-devel; +Cc: Zhanjun Dong

The previouse i915_gem_object_create_internal already set it with proper value before function return. This hard coded setting is incorrect for platforms like MTL, thus need to be removed.

Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_timeline.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index b9640212d659..693d18e14b00 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -26,8 +26,6 @@ static struct i915_vma *hwsp_alloc(struct intel_gt *gt)
 	if (IS_ERR(obj))
 		return ERR_CAST(obj);
 
-	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
-
 	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 	if (IS_ERR(vma))
 		i915_gem_object_put(obj);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [Intel-gfx] [PATCH] Remove incorrect hard coded cache coherrency setting
  2023-06-15 22:43 [PATCH] Remove incorrect hard coded cache coherrency setting Zhanjun Dong
@ 2023-06-16  7:39 ` Nirmoy Das
  0 siblings, 0 replies; 2+ messages in thread
From: Nirmoy Das @ 2023-06-16  7:39 UTC (permalink / raw)
  To: Zhanjun Dong, intel-gfx, dri-devel

Hi Zhanjun,

Patch subject should specify component. In this case it should be

drm/i915/gt:  Remove incorrect hard coded cache coherency setting

On 6/16/2023 12:43 AM, Zhanjun Dong wrote:
> The previouse i915_gem_object_create_internal already set it with proper value before function return. This hard coded setting is incorrect for platforms like MTL, thus need to be removed.


This needs to be wrapped. Try ./scripts/checkpatch.pl on the patch to  
find out more.

Otherwise It makes sense to remove that line.

Thanks,

Nirmoy

>
> Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_timeline.c | 2 --
>   1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index b9640212d659..693d18e14b00 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -26,8 +26,6 @@ static struct i915_vma *hwsp_alloc(struct intel_gt *gt)
>   	if (IS_ERR(obj))
>   		return ERR_CAST(obj);
>   
> -	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
> -
>   	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
>   	if (IS_ERR(vma))
>   		i915_gem_object_put(obj);

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2023-06-15 22:43 [PATCH] Remove incorrect hard coded cache coherrency setting Zhanjun Dong
2023-06-16  7:39 ` [Intel-gfx] " Nirmoy Das

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