[PATCH 0/4] drm: rcar-du: Update to SoC manual revision 1.00

[PATCH 0/4] drm: rcar-du: Update to SoC manual revision 1.00

[Jacopo Mondi]

Hello Laurent,
   Revision 1.00 has brought several updates on how to handle some registers
in the DU. In particular

- ESCR cannot be written for channels with a DPLL
- OTAR cannot be written for channels without a digital output pad
- routing superimposition processor output to pincontrollers through DORCR2
  register cannot be performed for channels of group 1
- The plane super-imposition register PnMR can be written to groups with more
  than 1 channel.

Patches applied on top of your latest drm/du/next branch.

Tested on Salvator-X M3-W with VGA and HDMI output.
Tested on Salvator-XS M3-N with VGA and HDMI output.
No visible regression, but if you have ideas on how to better verify this
please let me know.

Thanks
   j

Jacopo Mondi (4):
  drm: rcar-du: Do not write ESCR for DPLL channels
  drm: rcar-du: Write OTAR for DPAD channels only
  drm: rcar-du: Fix handling of DORCR for group 1
  drm: rcar-du: Fix handling of PnMR register

 drivers/gpu/drm/rcar-du/rcar_du_crtc.c  | 18 +++++++++++-------
 drivers/gpu/drm/rcar-du/rcar_du_group.c | 19 ++++++++++++++++---
 drivers/gpu/drm/rcar-du/rcar_du_plane.c | 13 +++++++++++--
 3 files changed, 38 insertions(+), 12 deletions(-)

--
2.7.4

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[PATCH 1/4] drm: rcar-du: Do not write ESCR for DPLL channels

[Jacopo Mondi]

According to revision 1.00 of R-Car Gen3 Soc manual, writing to ESCR
register of DU channels equipped with a display PLL (DPLL) is invalid.

Fix this by writing ESCR only for channels making use of the DU internal
post-divider to generate the dotclockout signal, with R-Car H3 ES1.x being
a notable exception.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 1541152..7b1c05b 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -246,7 +246,6 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 	struct rcar_du_device *rcdu = rcrtc->group->dev;
 	unsigned long mode_clock = mode->clock * 1000;
 	u32 dsmr;
-	u32 escr;
 
 	if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
 		unsigned long target = mode_clock;
@@ -293,7 +292,11 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 
 		rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
 
-		escr = ESCR_DCLKSEL_DCLKIN | div;
+		/* Only H3 ES1.x has a post divider when a DPLL is present. */
+		if (soc_device_match(rcar_du_r8a7795_es1))
+			rcar_du_crtc_write(rcrtc,
+					   rcrtc->index % 2 ? ESCR13 : ESCR02,
+					   ESCR_DCLKSEL_DCLKIN | div);
 	} else {
 		struct du_clk_params params = { .diff = (unsigned long)-1 };
 
@@ -308,12 +311,10 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 			params.rate);
 
 		clk_set_rate(params.clk, params.rate);
-		escr = params.escr;
+		rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02,
+				   params.escr);
 	}
 
-	dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
-
-	rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
 	rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
 
 	/* Signal polarities */
-- 
2.7.4

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[PATCH 2/4] drm: rcar-du: Write OTAR for DPAD channels only

[Jacopo Mondi]

According to revision 1.00 of R-Car Gen3 SoC manual, writing to OTAR
register is valid only if the channel is equipped with a digital output
pad (DPAD).

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 7b1c05b..9ba5551 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -315,7 +315,10 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 				   params.escr);
 	}
 
-	rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
+	if (rcrtc->index &
+	    rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs)
+		rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02,
+				   0);
 
 	/* Signal polarities */
 	dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
-- 
2.7.4

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[PATCH 3/4] drm: rcar-du: Fix handling of DORCR for group 1

[Jacopo Mondi]

According to revision 1.00 of R-Car Gen3 Soc manual, only DU channels of
group 0 (DU0 and DU1) supports output control routing through register DORCR0.

For channels of group 1 (DU2 and DU3) which are only present on H3/M3-W/M3-N
SoCs, no routing options are available between super-imposition processors
and the output pin controller. The updated version of the SoC manual
prescribes thus to hardcode DPRCR2 bits that controls output pin routing for
those channels.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/gpu/drm/rcar-du/rcar_du_group.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index ef2c177..e79d424 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -127,10 +127,19 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
 		rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
 
 	/*
-	 * Use DS1PR and DS2PR to configure planes priorities and connects the
-	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
+	 * For group 0 (DU0/DU1) use DS1PR and DS2PR to configure planes
+	 * priorities and connects the superposition 0 to DU0 pins.
+	 * DU1 pins will be configured dynamically.
+	 *
+	 * For group 1 (DU2/DU3), if any, use DS2PR and DS3PT to configure
+	 * planes priorities and hardcode other bits.
 	 */
-	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
+	if (rgrp->index == 0)
+		rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
+	else
+		rcar_du_group_write(rgrp, DORCR, DORCR_PG2T | DORCR_DK2S |
+				    DORCR_PG2D_DS2 | DORCR_DPRS);
+
 
 	/* Apply planes to CRTCs association. */
 	mutex_lock(&rgrp->lock);
@@ -247,6 +256,10 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
 	struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
 	u32 dorcr = rcar_du_group_read(rgrp, DORCR);
 
+	/* Only group 0 (DU0/DU1) has pin routing options. */
+	if (rgrp->index > 0)
+		return 0;
+
 	dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
 
 	/*
-- 
2.7.4

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[PATCH 4/4] drm: rcar-du: Fix handling of PnMR register

[Jacopo Mondi]

According to revision 1.00 of R-Car Gen3 Soc manual, setting bits
PnMR[13:12] is only valid if the DU group has two channels.

It is then valid writing to PnMR[13:12] for:
R-Car H3 = DU group 0 and DU group 1
R-Car M3-W, M3-N: DU group 0 only
R-Car D3/E3: DU group 0 (no group 1)

It is always invalid writing PnMR[13:12] on:
R-Car V3M/V3H: only group 0 is present, but with a single channel

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/gpu/drm/rcar-du/rcar_du_plane.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
index 5c2462a..647d2fc 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
@@ -505,8 +505,17 @@ static void rcar_du_plane_setup_format_gen3(struct rcar_du_group *rgrp,
 					    unsigned int index,
 					    const struct rcar_du_plane_state *state)
 {
-	rcar_du_plane_write(rgrp, index, PnMR,
-			    PnMR_SPIM_TP_OFF | state->format->pnmr);
+	u32 mask = BIT(rgrp->index * 2) | BIT(rgrp->index * 2 + 1);
+	u32 pnmr = PnMR_SPIM_TP_OFF;
+
+	/*
+	 * Setting PnMR[13:12] is only allowed when more than 1 channel is
+	 * availble in the group.
+	 */
+	if ((rgrp->channels_mask & mask) == mask)
+		pnmr |= state->format->pnmr;
+
+	rcar_du_plane_write(rgrp, index, PnMR, pnmr);
 
 	rcar_du_plane_write(rgrp, index, PnDDCR4,
 			    state->format->edf | PnDDCR4_CODE);
-- 
2.7.4

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Re: [PATCH 0/4] drm: rcar-du: Update to SoC manual revision 1.00

[jacopo mondi]

[-- Attachment #1.1: Type: text/plain, Size: 1418 bytes --]

Hi Laurent,

On Thu, Aug 23, 2018 at 05:12:10PM +0200, Jacopo Mondi wrote:
> Hello Laurent,
>    Revision 1.00 has brought several updates on how to handle some registers
> in the DU. In particular
>
> - ESCR cannot be written for channels with a DPLL
> - OTAR cannot be written for channels without a digital output pad
> - routing superimposition processor output to pincontrollers through DORCR2
>   register cannot be performed for channels of group 1
> - The plane super-imposition register PnMR can be written to groups with more
>   than 1 channel.
>
> Patches applied on top of your latest drm/du/next branch.

Could you please consider including this series in your tree?

Thanks
  j
>
> Tested on Salvator-X M3-W with VGA and HDMI output.
> Tested on Salvator-XS M3-N with VGA and HDMI output.
> No visible regression, but if you have ideas on how to better verify this
> please let me know.
>
> Thanks
>    j
>
> Jacopo Mondi (4):
>   drm: rcar-du: Do not write ESCR for DPLL channels
>   drm: rcar-du: Write OTAR for DPAD channels only
>   drm: rcar-du: Fix handling of DORCR for group 1
>   drm: rcar-du: Fix handling of PnMR register
>
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c  | 18 +++++++++++-------
>  drivers/gpu/drm/rcar-du/rcar_du_group.c | 19 ++++++++++++++++---
>  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 13 +++++++++++--
>  3 files changed, 38 insertions(+), 12 deletions(-)
>
> --
> 2.7.4
>

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