* [PATCH v1 00/21] add drm support for MT8192
@ 2020-08-20 6:03 Yongqiang Niu
2020-08-20 6:03 ` [PATCH v1 01/21] drm/mediatek: add component OVL_2L2 Yongqiang Niu
` (21 more replies)
0 siblings, 22 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:03 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
Changes in v1:
- add some more ddp component
- add mt8192 mmsys support
- add ovl mount on support
- add 2 more clock into mutex device
- fix ovl smi_id_en and fb null software bug
- fix ddp compoent size config bug
- add mt8192 drm support
- add ddp bypass shadow register function
- add 8192 dts description
Yongqiang Niu (21):
drm/mediatek: add component OVL_2L2
drm/mediatek: add component POSTMASK
drm/mediatek: add component RDMA4
mtk-mmsys: add mt8192 mmsys support
mtk-mmsys: add ovl mout on support
drm/mediatek: add disp config and mm 26mhz clock into mutex device
drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
drm/mediatek: check if fb is null
drm/mediatek: fix aal size config
drm/mediatek: fix dither size config
drm/mediatek: fix gamma size config
drm/mediatek: fix ccorr size config
drm/mediatek: add support for mediatek SOC MT8192
drm/mediatek: add bypass shadow register function call for ddp
component
drm/mediatek: add color bypass shadow register function
drm/mediatek: add ovl bypass shadow register function
drm/mediatek: add rdma bypass shadow register function
drm/mediatek: add dither bypass shadow register function
drm/mediatek: add aal bypass shadow register function
drm/mediatek: add ccorr bypass shadow register function
arm64: dts: mt8192: add display node
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 126 +++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_color.c | 22 ++++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 41 ++++++-
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 27 +++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 84 +++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 80 +++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 8 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 48 ++++++++
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 182 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 8 ++
include/linux/soc/mediatek/mtk-mmsys.h | 6 +
13 files changed, 623 insertions(+), 13 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
--
1.8.1.1.dirty
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v1 01/21] drm/mediatek: add component OVL_2L2
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
@ 2020-08-20 6:03 ` Yongqiang Niu
2020-08-20 6:03 ` [PATCH v1 02/21] drm/mediatek: add component POSTMASK Yongqiang Niu
` (20 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:03 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 57c88de..5e97ca5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -401,6 +401,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL },
+ [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, NULL },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 89185c6..268d95a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
1.8.1.1.dirty
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 02/21] drm/mediatek: add component POSTMASK
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
2020-08-20 6:03 ` [PATCH v1 01/21] drm/mediatek: add component OVL_2L2 Yongqiang Niu
@ 2020-08-20 6:03 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 03/21] drm/mediatek: add component RDMA4 Yongqiang Niu
` (19 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:03 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
This patch add component POSTMASK
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 31 +++++++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 5e97ca5..8b9fb5e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -58,6 +58,10 @@
#define DISP_GAMMA_SIZE 0x0030
#define DISP_GAMMA_LUT 0x0700
+#define DISP_POSTMASK_EN 0x0000
+#define DISP_POSTMASK_CFG 0x0020
+#define DISP_POSTMASK_SIZE 0x0030
+
#define LUT_10BIT_MASK 0x03ff
#define OD_RELAYMODE BIT(0)
@@ -319,6 +323,24 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
}
}
+static void mtk_postmask_config(struct mtk_ddp_comp *comp, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_POSTMASK_SIZE);
+ mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_POSTMASK_CFG);
+}
+
+static void mtk_postmask_start(struct mtk_ddp_comp *comp)
+{
+ writel(DITHER_EN, comp->regs + DISP_POSTMASK_EN);
+}
+
+static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
+{
+ writel_relaxed(0x0, comp->regs + DISP_POSTMASK_EN);
+}
+
static const struct mtk_ddp_comp_funcs ddp_aal = {
.gamma_set = mtk_gamma_set,
.config = mtk_aal_config,
@@ -346,6 +368,12 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
.stop = mtk_gamma_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_postmask = {
+ .config = mtk_postmask_config,
+ .start = mtk_postmask_start,
+ .stop = mtk_postmask_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_od = {
.config = mtk_od_config,
.start = mtk_od_start,
@@ -372,6 +400,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_BLS] = "bls",
+ [MTK_DISP_POSTMASK] = "postmask",
};
struct mtk_ddp_comp_match {
@@ -402,6 +431,8 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL },
[DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, NULL },
+ [DDP_COMPONENT_POSTMASK0]
+ = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 161201f..ae11b46 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_UFOE,
MTK_DSI,
MTK_DPI,
+ MTK_DISP_POSTMASK,
MTK_DISP_PWM,
MTK_DISP_MUTEX,
MTK_DISP_OD,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 268d95a..cc22c3e 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -31,6 +31,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 03/21] drm/mediatek: add component RDMA4
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
2020-08-20 6:03 ` [PATCH v1 01/21] drm/mediatek: add component OVL_2L2 Yongqiang Niu
2020-08-20 6:03 ` [PATCH v1 02/21] drm/mediatek: add component POSTMASK Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 04/21] mtk-mmsys: add mt8192 mmsys support Yongqiang Niu
` (18 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
This patch add component RDMA4
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 8b9fb5e..c90d2ee 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -439,6 +439,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
+ [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, NULL },
[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index cc22c3e..8ef3eaa 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
--
1.8.1.1.dirty
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 04/21] mtk-mmsys: add mt8192 mmsys support
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (2 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 03/21] drm/mediatek: add component RDMA4 Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 23:35 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 05/21] mtk-mmsys: add ovl mout on support Yongqiang Niu
` (17 subsequent siblings)
21 siblings, 1 reply; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add mt8192 mmsys support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 159 ++++++++++++++++++++++++++++++
2 files changed, 160 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index 62cfedf..c4bb6be 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += mt2701-mmsys.o
obj-y += mt8183-mmsys.o
+obj-y += mt8192-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
new file mode 100644
index 0000000..006d41d
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
+#define DISP_OVL0_GO_BLEND BIT(0)
+#define DISP_OVL0_GO_BG BIT(1)
+#define DISP_OVL0_2L_GO_BLEND BIT(2)
+#define DISP_OVL0_2L_GO_BG BIT(3)
+#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
+#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
+#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
+#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
+#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3
+#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
+#define MT8192_RDMA0_SOUT_COLOR0 0x1
+#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
+#define MT8192_CCORR0_SOUT_AAL0 0x1
+#define MT8192_DISP_AAL0_SEL_IN 0xf38
+#define MT8192_AAL0_SEL_IN_CCORR0 0x1
+#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
+#define MT8192_DITHER0_MOUT_DSI0 BIT(0)
+#define MT8192_DISP_DSI0_SEL_IN 0xf40
+#define MT8192_DSI0_SEL_IN_DITHER0 0x1
+#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
+#define MT8192_OVL2_2L_MOUT_RDMA4 BIT(0)
+
+struct mmsys_path_sel {
+ enum mtk_ddp_comp_id cur;
+ enum mtk_ddp_comp_id next;
+ u32 addr;
+ u32 val;
+};
+
+static struct mmsys_path_sel mmsys_mout_en[] = {
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_DISP_RDMA0,
+ },
+ {
+ DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
+ MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_RDMA4,
+ },
+ {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_DSI0,
+ },
+};
+
+static struct mmsys_path_sel mmsys_sel_in[] = {
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
+ },
+ {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
+ },
+ {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
+ },
+};
+
+static struct mmsys_path_sel mmsys_sout_sel[] = {
+ {
+ DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
+ MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
+ },
+ {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
+ }
+};
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ u32 i;
+ struct mmsys_path_sel *path;
+
+ for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) {
+ path = &mmsys_mout_en[i];
+ if (cur == path->cur && next == path->next) {
+ *addr = path->addr;
+ return path->val;
+ }
+ }
+
+ return 0;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ u32 i;
+ struct mmsys_path_sel *path;
+
+ for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) {
+ path = &mmsys_sel_in[i];
+ if (cur == path->cur && next == path->next) {
+ *addr = path->addr;
+ return path->val;
+ }
+ }
+
+ return 0;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next)
+{
+ u32 i;
+ u32 val = 0;
+ u32 addr = 0;
+ struct mmsys_path_sel *path;
+
+ for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) {
+ path = &mmsys_sout_sel[i];
+ if (cur == path->cur && next == path->next) {
+ addr = path->addr;
+ writel_relaxed(path->val, config_regs + addr);
+ return;
+ }
+ }
+}
+
+static struct mtk_mmsys_conn_funcs mmsys_funcs = {
+ .mout_en = mtk_mmsys_ddp_mout_en,
+ .sel_in = mtk_mmsys_ddp_sel_in,
+ .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
+
+static int mmsys_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+ mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs);
+
+ return 0;
+}
+
+static struct platform_driver mmsys_drv = {
+ .probe = mmsys_probe,
+ .driver = {
+ .name = "mt8192-mmsys",
+ },
+};
+
+builtin_platform_driver(mmsys_drv);
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 05/21] mtk-mmsys: add ovl mout on support
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (3 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 04/21] mtk-mmsys: add mt8192 mmsys support Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 23:36 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 06/21] drm/mediatek: add disp config and mm 26mhz clock into mutex device Yongqiang Niu
` (16 subsequent siblings)
21 siblings, 1 reply; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add ovl mout on support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 23 +++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 8 ++++++++
include/linux/soc/mediatek/mtk-mmsys.h | 3 +++
3 files changed, 34 insertions(+)
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
index 006d41d..06080ad 100644
--- a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -134,10 +134,33 @@ static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
}
}
+static int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ int value = -1;
+
+ *addr = MT8192_MMSYS_OVL_MOUT_EN;
+
+ if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_2L_GO_BG;
+ else if (cur == DDP_COMPONENT_OVL0)
+ value = DISP_OVL0_GO_BLEND;
+ else if (cur == DDP_COMPONENT_OVL_2L0)
+ value = DISP_OVL0_2L_GO_BLEND;
+ else
+ value = -1;
+
+ return value;
+}
+
static struct mtk_mmsys_conn_funcs mmsys_funcs = {
.mout_en = mtk_mmsys_ddp_mout_en,
.sel_in = mtk_mmsys_ddp_sel_in,
.sout_sel = mtk_mmsys_ddp_sout_sel,
+ .ovl_mout_en = mtk_mmsys_ovl_mout_en,
};
static int mmsys_probe(struct platform_device *pdev)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 828d59e..1362d01 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -76,6 +76,14 @@ void mtk_mmsys_ddp_connect(struct device *dev,
reg = readl_relaxed(config_regs + addr) | value;
writel_relaxed(reg, config_regs + addr);
}
+
+ if (priv_funcs->ovl_mout_en) {
+ value = priv_funcs->ovl_mout_en(cur, next, &addr);
+ if (value >= 0) {
+ reg = readl_relaxed(config_regs + addr) | value;
+ writel_relaxed(reg, config_regs + addr);
+ }
+ }
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 8ef3eaa..eefc7b1 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -55,6 +55,9 @@ struct mtk_mmsys_conn_funcs {
void (*sout_sel)(void __iomem *config_regs,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+ int (*ovl_mout_en)(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr);
};
void mtk_mmsys_register_conn_funcs(struct device *dev,
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 06/21] drm/mediatek: add disp config and mm 26mhz clock into mutex device
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (4 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 05/21] mtk-mmsys: add ovl mout on support Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 23:40 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 07/21] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase Yongqiang Niu
` (15 subsequent siblings)
21 siblings, 1 reply; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
there are 2 more clock need enable for display.
parser these clock when mutex device probe,
enable and disable when mutex on/off
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 49 ++++++++++++++++++++++++++++------
1 file changed, 41 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 60788c1..de618a1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -118,7 +118,7 @@ struct mtk_ddp_data {
struct mtk_ddp {
struct device *dev;
- struct clk *clk;
+ struct clk *clk[3];
void __iomem *regs;
struct mtk_disp_mutex mutex[10];
const struct mtk_ddp_data *data;
@@ -257,14 +257,39 @@ int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex)
{
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
- return clk_prepare_enable(ddp->clk);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
+ if (IS_ERR(ddp->clk[i]))
+ continue;
+ ret = clk_prepare_enable(ddp->clk[i]);
+ if (ret) {
+ pr_err("failed to enable clock, err %d. i:%d\n",
+ ret, i);
+ goto err;
+ }
+ }
+
+ return 0;
+
+err:
+ while (--i >= 0)
+ clk_disable_unprepare(ddp->clk[i]);
+ return ret;
}
void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex)
{
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
- clk_disable_unprepare(ddp->clk);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
+ if (IS_ERR(ddp->clk[i]))
+ continue;
+ clk_disable_unprepare(ddp->clk[i]);
+ }
}
void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
@@ -415,11 +440,19 @@ static int mtk_ddp_probe(struct platform_device *pdev)
ddp->data = of_device_get_match_data(dev);
if (!ddp->data->no_clk) {
- ddp->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(ddp->clk)) {
- if (PTR_ERR(ddp->clk) != -EPROBE_DEFER)
- dev_err(dev, "Failed to get clock\n");
- return PTR_ERR(ddp->clk);
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
+ ddp->clk[i] = of_clk_get(dev->of_node, i);
+
+ if (IS_ERR(ddp->clk[i])) {
+ ret = PTR_ERR(ddp->clk[i]);
+ if (ret != EPROBE_DEFER)
+ dev_err(dev, "Failed to get clock %d\n",
+ ret);
+
+ return ret;
+ }
}
}
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 07/21] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (5 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 06/21] drm/mediatek: add disp config and mm 26mhz clock into mutex device Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 23:43 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 08/21] drm/mediatek: check if fb is null Yongqiang Niu
` (14 subsequent siblings)
21 siblings, 1 reply; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 8cf9f3b..427fe7f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -23,6 +23,7 @@
#define DISP_REG_OVL_RST 0x0014
#define DISP_REG_OVL_ROI_SIZE 0x0020
#define DISP_REG_OVL_DATAPATH_CON 0x0024
+#define OVL_LAYER_SMI_ID_EN BIT(0)
#define OVL_BGCLR_SEL_IN BIT(2)
#define DISP_REG_OVL_ROI_BGCLR 0x0028
#define DISP_REG_OVL_SRC_CON 0x002c
@@ -116,6 +117,8 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
static void mtk_ovl_start(struct mtk_ddp_comp *comp)
{
writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
+ mtk_ddp_write_mask(NULL, OVL_LAYER_SMI_ID_EN, comp,
+ DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_SMI_ID_EN);
}
static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
--
1.8.1.1.dirty
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 08/21] drm/mediatek: check if fb is null
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (6 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 07/21] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 23:44 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 09/21] drm/mediatek: fix aal size config Yongqiang Niu
` (13 subsequent siblings)
21 siblings, 1 reply; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
It's possible that state->base.fb is null. Add a check before access its
format.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 427fe7f..2506803 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -269,7 +269,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
}
con = ovl_fmt_convert(ovl, fmt);
- if (state->base.fb->format->has_alpha)
+ if (state->base.fb && state->base.fb->format->has_alpha)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
if (pending->rotation & DRM_MODE_REFLECT_Y) {
--
1.8.1.1.dirty
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 09/21] drm/mediatek: fix aal size config
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (7 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 08/21] drm/mediatek: check if fb is null Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 23:46 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 10/21] drm/mediatek: fix dither " Yongqiang Niu
` (12 subsequent siblings)
21 siblings, 1 reply; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
fix aal size config
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index c90d2ee..fe76387 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -31,8 +31,13 @@
#define DISP_REG_UFO_START 0x0000
#define DISP_AAL_EN 0x0000
+#define DISP_AAL_CFG 0x0020
+#define AAL_RELAY_MODE BIT(0)
+#define AAL_ENGINE_EN BIT(1)
#define DISP_AAL_SIZE 0x0030
+#define DISP_AAL_OUTPUT_SIZE 0x04d8
+
#define DISP_CCORR_EN 0x0000
#define CCORR_EN BIT(0)
#define DISP_CCORR_CFG 0x0020
@@ -182,7 +187,11 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_OUTPUT_SIZE);
+
+ mtk_ddp_write_mask(NULL, AAL_RELAY_MODE, comp, DISP_AAL_CFG,
+ AAL_RELAY_MODE | AAL_ENGINE_EN);
}
static void mtk_aal_start(struct mtk_ddp_comp *comp)
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 10/21] drm/mediatek: fix dither size config
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (8 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 09/21] drm/mediatek: fix aal size config Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 11/21] drm/mediatek: fix gamma " Yongqiang Niu
` (11 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
fix dither size config
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index fe76387..becd72d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -277,7 +277,7 @@ static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_DITHER_SIZE);
mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG);
}
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 11/21] drm/mediatek: fix gamma size config
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (9 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 10/21] drm/mediatek: fix dither " Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 12/21] drm/mediatek: fix ccorr " Yongqiang Niu
` (10 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
fix gamma size config
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index becd72d..1d8dc6a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -295,7 +295,7 @@ static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_GAMMA_SIZE);
mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
}
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 12/21] drm/mediatek: fix ccorr size config
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (10 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 11/21] drm/mediatek: fix gamma " Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 13/21] drm/mediatek: add support for mediatek SOC MT8192 Yongqiang Niu
` (9 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
fix ccorr size config
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 1d8dc6a..0c81253 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -208,7 +208,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_CCORR_SIZE);
mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
}
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 13/21] drm/mediatek: add support for mediatek SOC MT8192
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (11 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 12/21] drm/mediatek: fix ccorr " Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 14/21] drm/mediatek: add bypass shadow register function call for ddp component Yongqiang Niu
` (8 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add support for mediatek SOC MT8192
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +++++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 7 +++++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 35 ++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 48 +++++++++++++++++++++++++++++++
5 files changed, 117 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 3ae9c81..31918fa 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -152,11 +152,18 @@ static int mtk_disp_color_remove(struct platform_device *pdev)
.color_offset = DISP_COLOR_START_MT8173,
};
+static const struct mtk_disp_color_data mt8192_color_driver_data = {
+ .color_offset = DISP_COLOR_START_MT8173,
+ .has_shadow = true,
+};
+
static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-color",
.data = &mt2701_color_driver_data},
{ .compatible = "mediatek,mt8173-disp-color",
.data = &mt8173_color_driver_data},
+ { .compatible = "mediatek,mt8192-disp-color",
+ .data = &mt8192_color_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_color_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 2506803..03eaadb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -447,6 +447,22 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
.fmt_rgb565_is_0 = true,
};
+static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 4,
+ .fmt_rgb565_is_0 = true,
+ .has_shadow = true,
+};
+
+static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 2,
+ .fmt_rgb565_is_0 = true,
+ .has_shadow = true,
+};
+
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = &mt2701_ovl_driver_data},
@@ -456,6 +472,10 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
.data = &mt8183_ovl_driver_data},
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = &mt8183_ovl_2l_driver_data},
+ { .compatible = "mediatek,mt8192-disp-ovl",
+ .data = &mt8192_ovl_driver_data},
+ { .compatible = "mediatek,mt8192-disp-ovl-2l",
+ .data = &mt8192_ovl_2l_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 51f2a0c..0683bef 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -359,6 +359,11 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
+ .fifo_size = 5 * SZ_1K,
+ .has_shadow = true,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -366,6 +371,8 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
.data = &mt8173_rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = &mt8183_rdma_driver_data},
+ { .compatible = "mediatek,mt8192-disp-rdma",
+ .data = &mt8192_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index de618a1..14105b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -27,6 +27,18 @@
#define INT_MUTEX BIT(1)
+#define MT8192_MUTEX_MOD_DISP_OVL0 0
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
+#define MT8192_MUTEX_MOD_DISP_RDMA0 2
+#define MT8192_MUTEX_MOD_DISP_COLOR0 4
+#define MT8192_MUTEX_MOD_DISP_CCORR0 5
+#define MT8192_MUTEX_MOD_DISP_AAL0 6
+#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
+#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
+#define MT8192_MUTEX_MOD_DISP_DITHER0 9
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
+#define MT8192_MUTEX_MOD_DISP_RDMA4 17
+
#define MT8183_MUTEX_MOD_DISP_RDMA0 0
#define MT8183_MUTEX_MOD_DISP_RDMA1 1
#define MT8183_MUTEX_MOD_DISP_OVL0 9
@@ -185,6 +197,20 @@ struct mtk_ddp {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
+static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
+ [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
+ [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
+ [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
+};
+
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -229,6 +255,13 @@ struct mtk_ddp {
.mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
};
+static const struct mtk_ddp_data mt8192_ddp_driver_data = {
+ .mutex_mod = mt8192_mutex_mod,
+ .mutex_sof = mt8183_mutex_sof,
+ .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
+};
+
struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
{
struct mtk_ddp *ddp = dev_get_drvdata(dev);
@@ -482,6 +515,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
.data = &mt8173_ddp_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_ddp_driver_data},
+ { .compatible = "mediatek,mt8192-disp-mutex",
+ .data = &mt8192_ddp_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 267e91e..638346c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -137,6 +137,25 @@
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL_2L0,
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_POSTMASK0,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_2L2,
+ DDP_COMPONENT_RDMA4,
+ DDP_COMPONENT_DPI0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -168,6 +187,13 @@
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+ .main_path = mt8192_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
+ .ext_path = mt8192_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -409,26 +435,42 @@ static void mtk_drm_unbind(struct device *dev)
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
+ { .compatible = "mediatek,mt8192-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8192-disp-ovl-2l",
+ .data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8192-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
{ .compatible = "mediatek,mt8183-disp-ccorr",
.data = (void *)MTK_DISP_CCORR },
+ { .compatible = "mediatek,mt8192-disp-ccorr",
+ .data = (void *)MTK_DISP_CCORR },
{ .compatible = "mediatek,mt2701-disp-color",
.data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-color",
.data = (void *)MTK_DISP_COLOR },
+ { .compatible = "mediatek,mt8192-disp-color",
+ .data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-aal",
.data = (void *)MTK_DISP_AAL},
+ { .compatible = "mediatek,mt8192-disp-aal",
+ .data = (void *)MTK_DISP_AAL},
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8192-disp-gamma",
+ .data = (void *)MTK_DISP_GAMMA},
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8192-disp-dither",
+ .data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
@@ -451,12 +493,16 @@ static void mtk_drm_unbind(struct device *dev)
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8192-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8192-disp-postmask",
+ .data = (void *)MTK_DISP_POSTMASK },
{ }
};
@@ -469,6 +515,8 @@ static void mtk_drm_unbind(struct device *dev)
.data = &mt8173_mmsys_driver_data},
{ .compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data},
{ }
};
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 14/21] drm/mediatek: add bypass shadow register function call for ddp component
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (12 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 13/21] drm/mediatek: add support for mediatek SOC MT8192 Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 23:48 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 15/21] drm/mediatek: add color bypass shadow register function Yongqiang Niu
` (7 subsequent siblings)
21 siblings, 1 reply; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
the shadow register for mt8192 ddp component is enable,
we need disable it before enable ddp component
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 +++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index fe46c4b..16e9b88 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -299,6 +299,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
goto err_mutex_unprepare;
}
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
+ mtk_ddp_comp_bypass_shadow(mtk_crtc->ddp_comp[i]);
+
DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ae11b46..1f25705 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -45,6 +45,7 @@ struct mtk_ddp_comp_funcs {
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
void (*start)(struct mtk_ddp_comp *comp);
void (*stop)(struct mtk_ddp_comp *comp);
+ void (*bypass_shadow)(struct mtk_ddp_comp *comp);
void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc);
void (*disable_vblank)(struct mtk_ddp_comp *comp);
unsigned int (*supported_rotations)(struct mtk_ddp_comp *comp);
@@ -169,6 +170,12 @@ static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
comp->funcs->ctm_set(comp, state);
}
+static inline void mtk_ddp_comp_bypass_shadow(struct mtk_ddp_comp *comp)
+{
+ if (comp->funcs && comp->funcs->bypass_shadow)
+ comp->funcs->bypass_shadow(comp);
+}
+
int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 15/21] drm/mediatek: add color bypass shadow register function
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (13 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 14/21] drm/mediatek: add bypass shadow register function call for ddp component Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 16/21] drm/mediatek: add ovl " Yongqiang Niu
` (6 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add color bypass shadow register function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_color.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 31918fa..83b075a 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -17,6 +17,8 @@
#define DISP_COLOR_CFG_MAIN 0x0400
#define DISP_COLOR_START_MT2701 0x0f00
#define DISP_COLOR_START_MT8173 0x0c00
+#define DISP_COLOR_SHADOW_CTRL 0x0cb0
+#define COLOR_BYPASS_SHADOW BIT(0)
#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
#define DISP_COLOR_HEIGHT(comp) (DISP_COLOR_START(comp) + 0x54)
@@ -26,6 +28,7 @@
struct mtk_disp_color_data {
unsigned int color_offset;
+ bool has_shadow;
};
/**
@@ -63,9 +66,21 @@ static void mtk_color_start(struct mtk_ddp_comp *comp)
writel(0x1, comp->regs + DISP_COLOR_START(color));
}
+static void mtk_color_bypass_shadow(struct mtk_ddp_comp *comp)
+{
+ struct mtk_disp_color *color = comp_to_color(comp);
+
+ if (color->data->has_shadow) {
+ mtk_ddp_write_mask(NULL, COLOR_BYPASS_SHADOW, comp,
+ DISP_COLOR_SHADOW_CTRL,
+ COLOR_BYPASS_SHADOW);
+ }
+}
+
static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = {
.config = mtk_color_config,
.start = mtk_color_start,
+ .bypass_shadow = mtk_color_bypass_shadow,
};
static int mtk_disp_color_bind(struct device *dev, struct device *master,
--
1.8.1.1.dirty
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 16/21] drm/mediatek: add ovl bypass shadow register function
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (14 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 15/21] drm/mediatek: add color bypass shadow register function Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 17/21] drm/mediatek: add rdma " Yongqiang Niu
` (5 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add ovl bypass shadow register function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 03eaadb..fb0fe59 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -19,6 +19,9 @@
#define DISP_REG_OVL_INTEN 0x0004
#define OVL_FME_CPL_INT BIT(1)
#define DISP_REG_OVL_INTSTA 0x0008
+#define OVL_EN BIT(0)
+#define OVL_READ_WORK_REG BIT(20)
+#define OVL_BYPASS_SHADOW BIT(22)
#define DISP_REG_OVL_EN 0x000c
#define DISP_REG_OVL_RST 0x0014
#define DISP_REG_OVL_ROI_SIZE 0x0020
@@ -62,6 +65,7 @@ struct mtk_disp_ovl_data {
unsigned int gmc_bits;
unsigned int layer_nr;
bool fmt_rgb565_is_0;
+ bool has_shadow;
};
/**
@@ -126,6 +130,17 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN);
}
+static void mtk_ovl_bypass_shadow(struct mtk_ddp_comp *comp)
+{
+ struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
+
+ if (ovl->data->has_shadow) {
+ mtk_ddp_write_mask(NULL, OVL_BYPASS_SHADOW, comp,
+ DISP_REG_OVL_EN,
+ OVL_BYPASS_SHADOW);
+ }
+}
+
static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -318,6 +333,7 @@ static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
.config = mtk_ovl_config,
.start = mtk_ovl_start,
.stop = mtk_ovl_stop,
+ .bypass_shadow = mtk_ovl_bypass_shadow,
.enable_vblank = mtk_ovl_enable_vblank,
.disable_vblank = mtk_ovl_disable_vblank,
.supported_rotations = mtk_ovl_supported_rotations,
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 17/21] drm/mediatek: add rdma bypass shadow register function
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (15 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 16/21] drm/mediatek: add ovl " Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 18/21] drm/mediatek: add dither " Yongqiang Niu
` (4 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add rdma bypass shadow register function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 0683bef..91ed6c6 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -46,12 +46,16 @@
#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
#define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
+#define DISP_REG_RDMA_SHADOW_UPDATE 0x00bc
+#define DISP_RDMA_BYPASS_SHADOW BIT(1)
+#define DISP_RDMA_READ_WORK_REG BIT(2)
#define DISP_RDMA_MEM_START_ADDR 0x0f00
#define RDMA_MEM_GMC 0x40402020
struct mtk_disp_rdma_data {
unsigned int fifo_size;
+ bool has_shadow;
};
/**
@@ -125,6 +129,21 @@ static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
}
+static void mtk_rdma_bypass_shadow(struct mtk_ddp_comp *comp)
+{
+ struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+
+ if (rdma->data->has_shadow) {
+ pr_err("disable rdma shadow\n");
+ mtk_ddp_write_mask(NULL, DISP_RDMA_BYPASS_SHADOW, comp,
+ DISP_REG_RDMA_SHADOW_UPDATE,
+ DISP_RDMA_BYPASS_SHADOW);
+ mtk_ddp_write_mask(NULL, DISP_RDMA_READ_WORK_REG, comp,
+ DISP_REG_RDMA_SHADOW_UPDATE,
+ DISP_RDMA_READ_WORK_REG);
+ }
+}
+
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
unsigned int height, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -238,6 +257,7 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
.config = mtk_rdma_config,
.start = mtk_rdma_start,
.stop = mtk_rdma_stop,
+ .bypass_shadow = mtk_rdma_bypass_shadow,
.enable_vblank = mtk_rdma_enable_vblank,
.disable_vblank = mtk_rdma_disable_vblank,
.layer_nr = mtk_rdma_layer_nr,
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 18/21] drm/mediatek: add dither bypass shadow register function
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (16 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 17/21] drm/mediatek: add rdma " Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 19/21] drm/mediatek: add aal " Yongqiang Niu
` (3 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add dither bypass shadow register function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 0c81253..315bd3a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -23,6 +23,9 @@
#define DISP_OD_INTSTA 0x000c
#define DISP_OD_CFG 0x0020
#define DISP_OD_SIZE 0x0030
+
+#define DITHER_REG(idx) (0x100 + (idx) * 4)
+#define DITHER_BYPASS_SHADOW BIT(0)
#define DISP_DITHER_5 0x0114
#define DISP_DITHER_7 0x011c
#define DISP_DITHER_15 0x013c
@@ -291,6 +294,13 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
writel_relaxed(0x0, comp->regs + DISP_DITHER_EN);
}
+static void mtk_dither_bypass_shadow(struct mtk_ddp_comp *comp)
+{
+ mtk_ddp_write_mask(NULL, DITHER_BYPASS_SHADOW, comp,
+ DITHER_REG(0),
+ DITHER_BYPASS_SHADOW);
+}
+
static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -368,6 +378,7 @@ static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
.config = mtk_dither_config,
.start = mtk_dither_start,
.stop = mtk_dither_stop,
+ .bypass_shadow = mtk_dither_bypass_shadow,
};
static const struct mtk_ddp_comp_funcs ddp_gamma = {
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 19/21] drm/mediatek: add aal bypass shadow register function
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (17 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 18/21] drm/mediatek: add dither " Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 20/21] drm/mediatek: add ccorr " Yongqiang Niu
` (2 subsequent siblings)
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add aal bypass shadow register function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 315bd3a..b4a6df5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -38,7 +38,8 @@
#define AAL_RELAY_MODE BIT(0)
#define AAL_ENGINE_EN BIT(1)
#define DISP_AAL_SIZE 0x0030
-
+#define DISP_AAL_SHADOW_CTRL 0x00f0
+#define AAL_BYPASS_SHADOW BIT(0)
#define DISP_AAL_OUTPUT_SIZE 0x04d8
#define DISP_CCORR_EN 0x0000
@@ -207,6 +208,13 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp)
writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
}
+static void mtk_aal_bypass_shadow(struct mtk_ddp_comp *comp)
+{
+ mtk_ddp_write_mask(NULL, AAL_BYPASS_SHADOW, comp,
+ DISP_AAL_SHADOW_CTRL,
+ AAL_BYPASS_SHADOW);
+}
+
static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -365,6 +373,7 @@ static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
.config = mtk_aal_config,
.start = mtk_aal_start,
.stop = mtk_aal_stop,
+ .bypass_shadow = mtk_aal_bypass_shadow,
};
static const struct mtk_ddp_comp_funcs ddp_ccorr = {
--
1.8.1.1.dirty
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 20/21] drm/mediatek: add ccorr bypass shadow register function
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (18 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 19/21] drm/mediatek: add aal " Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 21/21] arm64: dts: mt8192: add display node Yongqiang Niu
2020-08-20 9:13 ` [PATCH v1 00/21] add drm support for MT8192 Matthias Brugger
21 siblings, 0 replies; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add ccorr bypass shadow register function
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b4a6df5..ff23a94 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -55,6 +55,8 @@
#define DISP_CCORR_COEF_2 0x0088
#define DISP_CCORR_COEF_3 0x008C
#define DISP_CCORR_COEF_4 0x0090
+#define DISP_CCORR_SHADOW 0x00A0
+#define CCORR_BYPASS_SHADOW BIT(2)
#define DISP_DITHER_EN 0x0000
#define DITHER_EN BIT(0)
@@ -284,6 +286,13 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
comp, DISP_CCORR_COEF_4);
}
+static void mtk_ccorr_bypass_shadow(struct mtk_ddp_comp *comp)
+{
+ mtk_ddp_write_mask(NULL, CCORR_BYPASS_SHADOW, comp,
+ DISP_CCORR_SHADOW,
+ CCORR_BYPASS_SHADOW);
+}
+
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -381,6 +390,7 @@ static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
.start = mtk_ccorr_start,
.stop = mtk_ccorr_stop,
.ctm_set = mtk_ccorr_ctm_set,
+ .bypass_shadow = mtk_ccorr_bypass_shadow
};
static const struct mtk_ddp_comp_funcs ddp_dither = {
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 21/21] arm64: dts: mt8192: add display node
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (19 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 20/21] drm/mediatek: add ccorr " Yongqiang Niu
@ 2020-08-20 6:04 ` Yongqiang Niu
2020-08-20 13:23 ` Rob Herring
2020-08-20 9:13 ` [PATCH v1 00/21] add drm support for MT8192 Matthias Brugger
21 siblings, 1 reply; 31+ messages in thread
From: Yongqiang Niu @ 2020-08-20 6:04 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel
add display node
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 126 +++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 931e1ca..d2a814d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -17,6 +17,13 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ ovl0 = &ovl0;
+ ovl_2l0 = &ovl_2l0;
+ ovl_2l2 = &ovl_2l2;
+ rdma0 = &rdma0;
+ rdma4 = &rdma4;
+ };
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -449,6 +456,125 @@
#clock-cells = <1>;
};
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8192-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_CONFIG>,
+ <&mmsys CLK_MM_26MHZ>,
+ <&mmsys CLK_MM_DISP_MUTEX0>;
+ };
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+ // <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ };
+
+ ovl_2l0: ovl@14006000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+ // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,rdma_fifo_size = <5>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8192-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+ };
+
+ ccorr0: ccorr@1400a000 {
+ compatible = "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
+ };
+
+ aal0: aal@1400b000 {
+ compatible = "mediatek,mt8192-disp-aal";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+ };
+
+ gamma0: gamma@1400c000 {
+ compatible = "mediatek,mt8192-disp-gamma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ };
+
+ postmask0: postmask@1400d000 {
+ compatible = "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ //iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ };
+
+ dither0: dither@1400e000 {
+ compatible = "mediatek,mt8192-disp-dither";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ };
+
+ ovl_2l2: ovl@14014000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+ //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+ // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
+ };
+
+ rdma4: rdma@14015000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+ //iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+ mediatek,rdma_fifo_size = <2>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+ };
+
imgsys: imgsys@15020000 {
compatible = "mediatek,mt8192-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH v1 00/21] add drm support for MT8192
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
` (20 preceding siblings ...)
2020-08-20 6:04 ` [PATCH v1 21/21] arm64: dts: mt8192: add display node Yongqiang Niu
@ 2020-08-20 9:13 ` Matthias Brugger
21 siblings, 0 replies; 31+ messages in thread
From: Matthias Brugger @ 2020-08-20 9:13 UTC (permalink / raw)
To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel
On 20/08/2020 08:03, Yongqiang Niu wrote:
> Changes in v1:
> - add some more ddp component
> - add mt8192 mmsys support
> - add ovl mount on support
> - add 2 more clock into mutex device
> - fix ovl smi_id_en and fb null software bug
> - fix ddp compoent size config bug
> - add mt8192 drm support
> - add ddp bypass shadow register function
> - add 8192 dts description
>
> Yongqiang Niu (21):
> drm/mediatek: add component OVL_2L2
> drm/mediatek: add component POSTMASK
> drm/mediatek: add component RDMA4
> mtk-mmsys: add mt8192 mmsys support
> mtk-mmsys: add ovl mout on support
> drm/mediatek: add disp config and mm 26mhz clock into mutex device
> drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
> drm/mediatek: check if fb is null
> drm/mediatek: fix aal size config
> drm/mediatek: fix dither size config
> drm/mediatek: fix gamma size config
> drm/mediatek: fix ccorr size config
> drm/mediatek: add support for mediatek SOC MT8192
> drm/mediatek: add bypass shadow register function call for ddp
> component
> drm/mediatek: add color bypass shadow register function
> drm/mediatek: add ovl bypass shadow register function
> drm/mediatek: add rdma bypass shadow register function
> drm/mediatek: add dither bypass shadow register function
> drm/mediatek: add aal bypass shadow register function
> drm/mediatek: add ccorr bypass shadow register function
> arm64: dts: mt8192: add display node
>
At least regarding mmsys and dtsi patches, these are not based on upstream.
Please rebase.
Regards,
Matthias
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 126 +++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_disp_color.c | 22 ++++
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 41 ++++++-
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 27 +++++
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 84 +++++++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 80 +++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 8 ++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 48 ++++++++
> drivers/soc/mediatek/mmsys/Makefile | 1 +
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 182 ++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 8 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 6 +
> 13 files changed, 623 insertions(+), 13 deletions(-)
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
>
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 21/21] arm64: dts: mt8192: add display node
2020-08-20 6:04 ` [PATCH v1 21/21] arm64: dts: mt8192: add display node Yongqiang Niu
@ 2020-08-20 13:23 ` Rob Herring
0 siblings, 0 replies; 31+ messages in thread
From: Rob Herring @ 2020-08-20 13:23 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel,
Matthias Brugger, moderated list:ARM/Mediatek SoC support,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Thu, Aug 20, 2020 at 12:06 AM Yongqiang Niu
<yongqiang.niu@mediatek.com> wrote:
>
> add display node
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 126 +++++++++++++++++++++++++++++++
> 1 file changed, 126 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 931e1ca..d2a814d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -17,6 +17,13 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + ovl0 = &ovl0;
> + ovl_2l0 = &ovl_2l0;
> + ovl_2l2 = &ovl_2l2;
> + rdma0 = &rdma0;
> + rdma4 = &rdma4;
No, please don't add a bunch of custom aliases that you probably don't need.
> + };
> clk26m: oscillator@0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -449,6 +456,125 @@
> #clock-cells = <1>;
> };
>
> + mutex: mutex@14001000 {
> + compatible = "mediatek,mt8192-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_CONFIG>,
> + <&mmsys CLK_MM_26MHZ>,
> + <&mmsys CLK_MM_DISP_MUTEX0>;
> + };
> + ovl0: ovl@14005000 {
> + compatible = "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> + // <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + };
> +
> + ovl_2l0: ovl@14006000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> + // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + };
> +
> + rdma0: rdma@14007000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> + mediatek,rdma_fifo_size = <5>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> + };
> +
> + color0: color@14009000 {
> + compatible = "mediatek,mt8192-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> + };
> +
> + ccorr0: ccorr@1400a000 {
> + compatible = "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> + };
> +
> + aal0: aal@1400b000 {
> + compatible = "mediatek,mt8192-disp-aal";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> + };
> +
> + gamma0: gamma@1400c000 {
> + compatible = "mediatek,mt8192-disp-gamma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> + };
> +
> + postmask0: postmask@1400d000 {
> + compatible = "mediatek,mt8192-disp-postmask";
> + reg = <0 0x1400d000 0 0x1000>;
> + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> + //iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> + };
> +
> + dither0: dither@1400e000 {
> + compatible = "mediatek,mt8192-disp-dither";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> + };
> +
> + ovl_2l2: ovl@14014000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> + //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> + // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> + };
> +
> + rdma4: rdma@14015000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14015000 0 0x1000>;
> + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> + //iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> + mediatek,rdma_fifo_size = <2>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> + };
> +
> imgsys: imgsys@15020000 {
> compatible = "mediatek,mt8192-imgsys", "syscon";
> reg = <0 0x15020000 0 0x1000>;
> --
> 1.8.1.1.dirty
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 04/21] mtk-mmsys: add mt8192 mmsys support
2020-08-20 6:04 ` [PATCH v1 04/21] mtk-mmsys: add mt8192 mmsys support Yongqiang Niu
@ 2020-08-20 23:35 ` Chun-Kuang Hu
0 siblings, 0 replies; 31+ messages in thread
From: Chun-Kuang Hu @ 2020-08-20 23:35 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel,
DRI Development, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年8月20日 週四 下午2:16寫道:
>
> add mt8192 mmsys support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/Makefile | 1 +
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 159 ++++++++++++++++++++++++++++++
> 2 files changed, 160 insertions(+)
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
>
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> index 62cfedf..c4bb6be 100644
> --- a/drivers/soc/mediatek/mmsys/Makefile
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-y += mt2701-mmsys.o
> obj-y += mt8183-mmsys.o
> +obj-y += mt8192-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> new file mode 100644
> index 0000000..006d41d
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> @@ -0,0 +1,159 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
> +#define DISP_OVL0_GO_BLEND BIT(0)
> +#define DISP_OVL0_GO_BG BIT(1)
> +#define DISP_OVL0_2L_GO_BLEND BIT(2)
> +#define DISP_OVL0_2L_GO_BG BIT(3)
> +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
> +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
> +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
> +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
> +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3
> +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
> +#define MT8192_RDMA0_SOUT_COLOR0 0x1
> +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
> +#define MT8192_CCORR0_SOUT_AAL0 0x1
> +#define MT8192_DISP_AAL0_SEL_IN 0xf38
> +#define MT8192_AAL0_SEL_IN_CCORR0 0x1
> +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
> +#define MT8192_DITHER0_MOUT_DSI0 BIT(0)
> +#define MT8192_DISP_DSI0_SEL_IN 0xf40
> +#define MT8192_DSI0_SEL_IN_DITHER0 0x1
> +#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
> +#define MT8192_OVL2_2L_MOUT_RDMA4 BIT(0)
> +
> +struct mmsys_path_sel {
> + enum mtk_ddp_comp_id cur;
> + enum mtk_ddp_comp_id next;
> + u32 addr;
> + u32 val;
> +};
> +
> +static struct mmsys_path_sel mmsys_mout_en[] = {
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8192_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_DISP_RDMA0,
> + },
> + {
> + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
> + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_RDMA4,
> + },
> + {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_DSI0,
> + },
> +};
> +
> +static struct mmsys_path_sel mmsys_sel_in[] = {
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
> + },
> + {
> + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
> + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
> + },
> + {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
> + },
> +};
> +
> +static struct mmsys_path_sel mmsys_sout_sel[] = {
> + {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
> + },
> + {
> + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
> + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
> + }
> +};
> +
> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + u32 i;
> + struct mmsys_path_sel *path;
> +
> + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) {
> + path = &mmsys_mout_en[i];
> + if (cur == path->cur && next == path->next) {
> + *addr = path->addr;
> + return path->val;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + u32 i;
> + struct mmsys_path_sel *path;
> +
> + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) {
> + path = &mmsys_sel_in[i];
> + if (cur == path->cur && next == path->next) {
> + *addr = path->addr;
> + return path->val;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next)
> +{
> + u32 i;
> + u32 val = 0;
> + u32 addr = 0;
> + struct mmsys_path_sel *path;
> +
> + for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) {
> + path = &mmsys_sout_sel[i];
> + if (cur == path->cur && next == path->next) {
> + addr = path->addr;
> + writel_relaxed(path->val, config_regs + addr);
> + return;
> + }
> + }
> +}
> +
> +static struct mtk_mmsys_conn_funcs mmsys_funcs = {
> + .mout_en = mtk_mmsys_ddp_mout_en,
> + .sel_in = mtk_mmsys_ddp_sel_in,
> + .sout_sel = mtk_mmsys_ddp_sout_sel,
> +};
I would like to do routing control like [1].
[1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2345186
Regards,
Chun-Kuang.
> +
> +static int mmsys_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> +
> + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs);
> +
> + return 0;
> +}
> +
> +static struct platform_driver mmsys_drv = {
> + .probe = mmsys_probe,
> + .driver = {
> + .name = "mt8192-mmsys",
> + },
> +};
> +
> +builtin_platform_driver(mmsys_drv);
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 05/21] mtk-mmsys: add ovl mout on support
2020-08-20 6:04 ` [PATCH v1 05/21] mtk-mmsys: add ovl mout on support Yongqiang Niu
@ 2020-08-20 23:36 ` Chun-Kuang Hu
0 siblings, 0 replies; 31+ messages in thread
From: Chun-Kuang Hu @ 2020-08-20 23:36 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel,
DRI Development, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年8月20日 週四 下午2:16寫道:
>
> add ovl mout on support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 23 +++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 8 ++++++++
> include/linux/soc/mediatek/mtk-mmsys.h | 3 +++
> 3 files changed, 34 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> index 006d41d..06080ad 100644
> --- a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> @@ -134,10 +134,33 @@ static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> }
> }
>
> +static int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + int value = -1;
> +
> + *addr = MT8192_MMSYS_OVL_MOUT_EN;
> +
> + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_2L_GO_BG;
> + else if (cur == DDP_COMPONENT_OVL0)
> + value = DISP_OVL0_GO_BLEND;
> + else if (cur == DDP_COMPONENT_OVL_2L0)
> + value = DISP_OVL0_2L_GO_BLEND;
> + else
> + value = -1;
> +
> + return value;
> +}
> +
> static struct mtk_mmsys_conn_funcs mmsys_funcs = {
> .mout_en = mtk_mmsys_ddp_mout_en,
> .sel_in = mtk_mmsys_ddp_sel_in,
> .sout_sel = mtk_mmsys_ddp_sout_sel,
> + .ovl_mout_en = mtk_mmsys_ovl_mout_en,
> };
>
> static int mmsys_probe(struct platform_device *pdev)
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 828d59e..1362d01 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -76,6 +76,14 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> reg = readl_relaxed(config_regs + addr) | value;
> writel_relaxed(reg, config_regs + addr);
> }
> +
> + if (priv_funcs->ovl_mout_en) {
> + value = priv_funcs->ovl_mout_en(cur, next, &addr);
> + if (value >= 0) {
> + reg = readl_relaxed(config_regs + addr) | value;
> + writel_relaxed(reg, config_regs + addr);
> + }
> + }
I would like to do routing control like [1].
[1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2345186
Regards,
Chun-Kuang.
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 8ef3eaa..eefc7b1 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -55,6 +55,9 @@ struct mtk_mmsys_conn_funcs {
> void (*sout_sel)(void __iomem *config_regs,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> + int (*ovl_mout_en)(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr);
> };
>
> void mtk_mmsys_register_conn_funcs(struct device *dev,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 06/21] drm/mediatek: add disp config and mm 26mhz clock into mutex device
2020-08-20 6:04 ` [PATCH v1 06/21] drm/mediatek: add disp config and mm 26mhz clock into mutex device Yongqiang Niu
@ 2020-08-20 23:40 ` Chun-Kuang Hu
0 siblings, 0 replies; 31+ messages in thread
From: Chun-Kuang Hu @ 2020-08-20 23:40 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel,
DRI Development, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年8月20日 週四 下午2:06寫道:
>
> there are 2 more clock need enable for display.
> parser these clock when mutex device probe,
> enable and disable when mutex on/off
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 49 ++++++++++++++++++++++++++++------
> 1 file changed, 41 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 60788c1..de618a1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -118,7 +118,7 @@ struct mtk_ddp_data {
>
> struct mtk_ddp {
> struct device *dev;
> - struct clk *clk;
> + struct clk *clk[3];
> void __iomem *regs;
> struct mtk_disp_mutex mutex[10];
> const struct mtk_ddp_data *data;
> @@ -257,14 +257,39 @@ int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex)
> {
> struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> mutex[mutex->id]);
> - return clk_prepare_enable(ddp->clk);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
> + if (IS_ERR(ddp->clk[i]))
> + continue;
> + ret = clk_prepare_enable(ddp->clk[i]);
> + if (ret) {
> + pr_err("failed to enable clock, err %d. i:%d\n",
> + ret, i);
> + goto err;
> + }
> + }
> +
> + return 0;
> +
> +err:
> + while (--i >= 0)
> + clk_disable_unprepare(ddp->clk[i]);
> + return ret;
> }
>
> void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex)
> {
> struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> mutex[mutex->id]);
> - clk_disable_unprepare(ddp->clk);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
> + if (IS_ERR(ddp->clk[i]))
> + continue;
> + clk_disable_unprepare(ddp->clk[i]);
> + }
> }
>
> void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> @@ -415,11 +440,19 @@ static int mtk_ddp_probe(struct platform_device *pdev)
> ddp->data = of_device_get_match_data(dev);
>
> if (!ddp->data->no_clk) {
> - ddp->clk = devm_clk_get(dev, NULL);
> - if (IS_ERR(ddp->clk)) {
> - if (PTR_ERR(ddp->clk) != -EPROBE_DEFER)
> - dev_err(dev, "Failed to get clock\n");
> - return PTR_ERR(ddp->clk);
> + int ret;
> +
> + for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
Modify binding document for this.
Regards,
Chun-Kuang.
> + ddp->clk[i] = of_clk_get(dev->of_node, i);
> +
> + if (IS_ERR(ddp->clk[i])) {
> + ret = PTR_ERR(ddp->clk[i]);
> + if (ret != EPROBE_DEFER)
> + dev_err(dev, "Failed to get clock %d\n",
> + ret);
> +
> + return ret;
> + }
> }
> }
>
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 07/21] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
2020-08-20 6:04 ` [PATCH v1 07/21] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase Yongqiang Niu
@ 2020-08-20 23:43 ` Chun-Kuang Hu
0 siblings, 0 replies; 31+ messages in thread
From: Chun-Kuang Hu @ 2020-08-20 23:43 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel,
DRI Development, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
HI, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年8月20日 週四 下午2:06寫道:
>
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 8cf9f3b..427fe7f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -23,6 +23,7 @@
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE 0x0020
> #define DISP_REG_OVL_DATAPATH_CON 0x0024
> +#define OVL_LAYER_SMI_ID_EN BIT(0)
> #define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> @@ -116,6 +117,8 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
> static void mtk_ovl_start(struct mtk_ddp_comp *comp)
> {
> writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
> + mtk_ddp_write_mask(NULL, OVL_LAYER_SMI_ID_EN, comp,
writel_relaxed instead of mtk_ddp_write_mask.
> + DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_SMI_ID_EN);
If this only should set in mt8192, add a private data to distinguish this.
Regards,
Chun-Kuang.
> }
>
> static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 08/21] drm/mediatek: check if fb is null
2020-08-20 6:04 ` [PATCH v1 08/21] drm/mediatek: check if fb is null Yongqiang Niu
@ 2020-08-20 23:44 ` Chun-Kuang Hu
0 siblings, 0 replies; 31+ messages in thread
From: Chun-Kuang Hu @ 2020-08-20 23:44 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel,
DRI Development, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年8月20日 週四 下午2:06寫道:
>
> It's possible that state->base.fb is null. Add a check before access its
> format.
Add a Fixes tag.
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 427fe7f..2506803 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -269,7 +269,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> }
>
> con = ovl_fmt_convert(ovl, fmt);
> - if (state->base.fb->format->has_alpha)
> + if (state->base.fb && state->base.fb->format->has_alpha)
> con |= OVL_CON_AEN | OVL_CON_ALPHA;
>
> if (pending->rotation & DRM_MODE_REFLECT_Y) {
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 09/21] drm/mediatek: fix aal size config
2020-08-20 6:04 ` [PATCH v1 09/21] drm/mediatek: fix aal size config Yongqiang Niu
@ 2020-08-20 23:46 ` Chun-Kuang Hu
0 siblings, 0 replies; 31+ messages in thread
From: Chun-Kuang Hu @ 2020-08-20 23:46 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel,
DRI Development, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年8月20日 週四 下午2:18寫道:
>
> fix aal size config
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index c90d2ee..fe76387 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -31,8 +31,13 @@
> #define DISP_REG_UFO_START 0x0000
>
> #define DISP_AAL_EN 0x0000
> +#define DISP_AAL_CFG 0x0020
> +#define AAL_RELAY_MODE BIT(0)
> +#define AAL_ENGINE_EN BIT(1)
> #define DISP_AAL_SIZE 0x0030
>
> +#define DISP_AAL_OUTPUT_SIZE 0x04d8
> +
> #define DISP_CCORR_EN 0x0000
> #define CCORR_EN BIT(0)
> #define DISP_CCORR_CFG 0x0020
> @@ -182,7 +187,11 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_OUTPUT_SIZE);
> +
> + mtk_ddp_write_mask(NULL, AAL_RELAY_MODE, comp, DISP_AAL_CFG,
> + AAL_RELAY_MODE | AAL_ENGINE_EN);
If this only should set in mt8192, add a private data to distinguish this.
Regards,
Chun-Kuang.
> }
>
> static void mtk_aal_start(struct mtk_ddp_comp *comp)
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 14/21] drm/mediatek: add bypass shadow register function call for ddp component
2020-08-20 6:04 ` [PATCH v1 14/21] drm/mediatek: add bypass shadow register function call for ddp component Yongqiang Niu
@ 2020-08-20 23:48 ` Chun-Kuang Hu
0 siblings, 0 replies; 31+ messages in thread
From: Chun-Kuang Hu @ 2020-08-20 23:48 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Mark Rutland, devicetree, David Airlie, linux-kernel,
DRI Development, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年8月20日 週四 下午2:18寫道:
>
> the shadow register for mt8192 ddp component is enable,
> we need disable it before enable ddp component
MT2701 has shadow register and use it. Why MT8192 have shadow register
but disable it? I would like to use shadow register like MT2701.
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 +++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index fe46c4b..16e9b88 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -299,6 +299,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> goto err_mutex_unprepare;
> }
>
> + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> + mtk_ddp_comp_bypass_shadow(mtk_crtc->ddp_comp[i]);
> +
> DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
> for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index ae11b46..1f25705 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -45,6 +45,7 @@ struct mtk_ddp_comp_funcs {
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void (*start)(struct mtk_ddp_comp *comp);
> void (*stop)(struct mtk_ddp_comp *comp);
> + void (*bypass_shadow)(struct mtk_ddp_comp *comp);
> void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc);
> void (*disable_vblank)(struct mtk_ddp_comp *comp);
> unsigned int (*supported_rotations)(struct mtk_ddp_comp *comp);
> @@ -169,6 +170,12 @@ static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> comp->funcs->ctm_set(comp, state);
> }
>
> +static inline void mtk_ddp_comp_bypass_shadow(struct mtk_ddp_comp *comp)
> +{
> + if (comp->funcs && comp->funcs->bypass_shadow)
> + comp->funcs->bypass_shadow(comp);
> +}
> +
> int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type);
> int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2020-08-20 23:48 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-20 6:03 [PATCH v1 00/21] add drm support for MT8192 Yongqiang Niu
2020-08-20 6:03 ` [PATCH v1 01/21] drm/mediatek: add component OVL_2L2 Yongqiang Niu
2020-08-20 6:03 ` [PATCH v1 02/21] drm/mediatek: add component POSTMASK Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 03/21] drm/mediatek: add component RDMA4 Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 04/21] mtk-mmsys: add mt8192 mmsys support Yongqiang Niu
2020-08-20 23:35 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 05/21] mtk-mmsys: add ovl mout on support Yongqiang Niu
2020-08-20 23:36 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 06/21] drm/mediatek: add disp config and mm 26mhz clock into mutex device Yongqiang Niu
2020-08-20 23:40 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 07/21] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase Yongqiang Niu
2020-08-20 23:43 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 08/21] drm/mediatek: check if fb is null Yongqiang Niu
2020-08-20 23:44 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 09/21] drm/mediatek: fix aal size config Yongqiang Niu
2020-08-20 23:46 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 10/21] drm/mediatek: fix dither " Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 11/21] drm/mediatek: fix gamma " Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 12/21] drm/mediatek: fix ccorr " Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 13/21] drm/mediatek: add support for mediatek SOC MT8192 Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 14/21] drm/mediatek: add bypass shadow register function call for ddp component Yongqiang Niu
2020-08-20 23:48 ` Chun-Kuang Hu
2020-08-20 6:04 ` [PATCH v1 15/21] drm/mediatek: add color bypass shadow register function Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 16/21] drm/mediatek: add ovl " Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 17/21] drm/mediatek: add rdma " Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 18/21] drm/mediatek: add dither " Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 19/21] drm/mediatek: add aal " Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 20/21] drm/mediatek: add ccorr " Yongqiang Niu
2020-08-20 6:04 ` [PATCH v1 21/21] arm64: dts: mt8192: add display node Yongqiang Niu
2020-08-20 13:23 ` Rob Herring
2020-08-20 9:13 ` [PATCH v1 00/21] add drm support for MT8192 Matthias Brugger
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