* [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs
@ 2021-03-10 9:55 Liu Ying
2021-03-10 9:55 ` [PATCH v5 01/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner Liu Ying
` (13 more replies)
0 siblings, 14 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
Hi,
This is the v5 series to add some DRM bridge drivers support
for i.MX8qm/qxp SoCs.
The bridges may chain one by one to form display pipes to support
LVDS displays. The relevant display controller is DPU embedded in
i.MX8qm/qxp SoCs.
The DPU KMS driver can be found at:
https://www.spinics.net/lists/arm-kernel/msg878542.html
This series supports the following display pipes:
1) i.MX8qxp:
prefetch eng -> DPU -> pixel combiner -> pixel link ->
pixel link to DPI(PXL2DPI) -> LVDS display bridge(LDB)
2) i.MX8qm:
prefetch eng -> DPU -> pixel combiner -> pixel link -> LVDS display bridge(LDB)
This series drops the patch 'phy: Add LVDS configuration options', as suggested
by Robert Foss, because it has already been sent with the following series to
add Mixel combo PHY found in i.MX8qxp:
https://www.spinics.net/lists/arm-kernel/msg879957.html
So, this version depends on that series.
Patch 1/14 and 2/14 add bus formats used by PXL2DPI.
Patch 7/14 adds dt-binding for Control and Status Registers module(a syscon
used by PXL2DPI and LDB), which references the PXL2DPI and LDB schemas.
Patch 10/14 adds a helper for LDB bridge drivers.
Patch 3/14 ~ 6/14, 8/14, 9/14 and 11/14 ~ 13/14 add drm bridge drivers and
dt-bindings support for the bridges.
Patch 14/14 updates MAINTAINERS.
I've tested this series with a koe,tx26d202vm0bwa dual link LVDS panel and
a LVDS to HDMI bridge(with a downstream drm bridge driver).
Welcome comments, thanks.
v4->v5:
* Drop the patch 'phy: Add LVDS configuration options'. (Robert)
* Add Robert's R-b tags on patch 1/14, 2/14, 4/14 and 6/14.
* Drop the 'PC_BUF_PARA_REG' register definition from the pixel combiner bridge
driver(patch 4/14). (Robert)
* Make a comment occupy a line in the pixel link bridge driver(patch 6/14).
(Robert)
* Introduce a new patch(patch 7/14) to add dt-binding for Control and Status
Registers module. (Rob)
* Make imx-ldb-helper be a pure object to be linked with i.MX8qxp LDB bridge
driver and i.MX8qm LDB bridge driver, instead of a module. Correspondingly,
rename 'imx8{qm, qxp}-ldb.c' to 'imx8{qm, qxp}-ldb-drv.c'. (Robert)
* Move 'imx_ldb_helper.h' to 'drivers/gpu/drm/bridge/imx/imx-ldb-helper.h'.
(Robert)
* s/__FSL_IMX_LDB__/__IMX_LDB_HELPER__/ for 'imx-ldb-helper.h'.
v3->v4:
* Use 'fsl,sc-resource' DT property to get the SCU resource ID associated with
the PXL2DPI instance instead of using alias ID. (Rob)
* Add Rob's R-b tag on patch 11/14.
v2->v3:
* Drop 'fsl,syscon' DT properties from fsl,imx8qxp-ldb.yaml and
fsl,imx8qxp-pxl2dpi.yaml. (Rob)
* Mention the CSR module controls LDB and PXL2DPI in fsl,imx8qxp-ldb.yaml and
fsl,imx8qxp-pxl2dpi.yaml.
* Call syscon_node_to_regmap() to get regmaps from LDB bridge helper driver
and PXL2DPI bridger driver instead of syscon_regmap_lookup_by_phandle().
* Drop two macros from pixel link bridge driver which help define functions
and define them directly.
* Properly disable all pixel link controls to POR value by calling
imx8qxp_pixel_link_disable_all_controls() from
imx8qxp_pixel_link_bridge_probe().
* Add Rob's R-b tags on patch 4/14 and 6/14.
v1->v2:
* Rebase the series upon the latest drm-misc-next branch(5.11-rc2 based).
* Use graph schema in the dt-bindings of the bridges. (Laurent)
* Require all four pixel link output ports in fsl,imx8qxp-pixel-link.yaml.
(Laurent)
* Side note i.MX8qm/qxp LDB official name 'pixel mapper' in fsl,imx8qxp-ldb.yaml.
(Laurent)
* Mention pixel link is accessed via SCU firmware in fsl,imx8qxp-pixel-link.yaml.
(Rob)
* Use enum instead of oneOf + const for the reg property of pixel combiner
channels in fsl,imx8qxp-pixel-combiner.yaml. (Rob)
* Rewrite the function to find the next bridge in pixel link bridge driver
by properly using OF APIs and dropping unnecessary DT validation. (Rob)
* Drop unnecessary port availability check in i.MX8qxp pixel link to DPI
bridge driver.
* Drop unnecessary DT validation from i.MX8qxp LDB bridge driver.
* Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to
get the input remote endpoint in imx8qxp_ldb_set_di_id() of i.MX8qxp LDB
bridge driver.
* Avoid using companion_port OF node after putting it in
imx8qxp_ldb_parse_dt_companion() of i.MX8qxp LDB bridge driver.
* Drop unnecessary check for maximum available LDB channels from
i.MX8qm LDB bridge driver.
* Mention i.MX8qm/qxp LDB official name 'pixel mapper' in i.MX8qm/qxp LDB
bridge drivers and Kconfig help messages.
Liu Ying (14):
media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding
drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link
binding
drm/bridge: imx: Add i.MX8qm/qxp display pixel link support
dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module
binding
dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding
drm/bridge: imx: Add i.MX8qxp pixel link to DPI support
drm/bridge: imx: Add LDB driver helper support
dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge
binding
drm/bridge: imx: Add LDB support for i.MX8qxp
drm/bridge: imx: Add LDB support for i.MX8qm
MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 173 +++++
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 +++++
.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++
.../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 108 ++++
.../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml | 202 ++++++
.../userspace-api/media/v4l/subdev-formats.rst | 156 +++++
MAINTAINERS | 10 +
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/imx/Kconfig | 42 ++
drivers/gpu/drm/bridge/imx/Makefile | 9 +
drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 232 +++++++
drivers/gpu/drm/bridge/imx/imx-ldb-helper.h | 98 +++
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c | 586 +++++++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c | 720 +++++++++++++++++++++
.../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c | 448 +++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 427 ++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 485 ++++++++++++++
include/uapi/linux/media-bus-format.h | 6 +-
19 files changed, 3954 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig
create mode 100644 drivers/gpu/drm/bridge/imx/Makefile
create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.h
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v5 01/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 13:45 ` Laurent Pinchart
2021-03-10 9:55 ` [PATCH v5 02/14] media: docs: " Liu Ying
` (12 subsequent siblings)
13 siblings, 1 reply; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output bus(12-bit per component) to a pixel link.
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* Add Robert's R-b tag.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
include/uapi/linux/media-bus-format.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h
index 0dfc11e..ec3323d 100644
--- a/include/uapi/linux/media-bus-format.h
+++ b/include/uapi/linux/media-bus-format.h
@@ -34,7 +34,7 @@
#define MEDIA_BUS_FMT_FIXED 0x0001
-/* RGB - next is 0x101e */
+/* RGB - next is 0x1022 */
#define MEDIA_BUS_FMT_RGB444_1X12 0x1016
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
@@ -59,9 +59,13 @@
#define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d
#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
+#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO 0x101e
+#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO 0x101f
#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018
+#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020
+#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021
#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019
#define MEDIA_BUS_FMT_RGB161616_1X48 0x101a
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 02/14] media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
2021-03-10 9:55 ` [PATCH v5 01/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 13:24 ` Laurent Pinchart
2021-03-10 9:55 ` [PATCH v5 03/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding Liu Ying
` (11 subsequent siblings)
13 siblings, 1 reply; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO,
RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp
pixel combiner. The RGB pixels with padding low per component are
transmitted on a 30-bit input bus(10-bit per component) from a display
controller or a 36-bit output bus(12-bit per component) to a pixel link.
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* Add Robert's R-b tag.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
.../userspace-api/media/v4l/subdev-formats.rst | 156 +++++++++++++++++++++
1 file changed, 156 insertions(+)
diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst b/Documentation/userspace-api/media/v4l/subdev-formats.rst
index 7f16cbe..201c16d 100644
--- a/Documentation/userspace-api/media/v4l/subdev-formats.rst
+++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst
@@ -1488,6 +1488,80 @@ The following tables list existing packed RGB formats.
- b\ :sub:`2`
- b\ :sub:`1`
- b\ :sub:`0`
+ * .. _MEDIA-BUS-FMT-RGB666-1X30-CPADLO:
+
+ - MEDIA_BUS_FMT_RGB666_1X30-CPADLO
+ - 0x101e
+ -
+ - 0
+ - 0
+ - r\ :sub:`5`
+ - r\ :sub:`4`
+ - r\ :sub:`3`
+ - r\ :sub:`2`
+ - r\ :sub:`1`
+ - r\ :sub:`0`
+ - 0
+ - 0
+ - 0
+ - 0
+ - g\ :sub:`5`
+ - g\ :sub:`4`
+ - g\ :sub:`3`
+ - g\ :sub:`2`
+ - g\ :sub:`1`
+ - g\ :sub:`0`
+ - 0
+ - 0
+ - 0
+ - 0
+ - b\ :sub:`5`
+ - b\ :sub:`4`
+ - b\ :sub:`3`
+ - b\ :sub:`2`
+ - b\ :sub:`1`
+ - b\ :sub:`0`
+ - 0
+ - 0
+ - 0
+ - 0
+ * .. _MEDIA-BUS-FMT-RGB888-1X30-CPADLO:
+
+ - MEDIA_BUS_FMT_RGB888_1X30-CPADLO
+ - 0x101f
+ -
+ - 0
+ - 0
+ - r\ :sub:`7`
+ - r\ :sub:`6`
+ - r\ :sub:`5`
+ - r\ :sub:`4`
+ - r\ :sub:`3`
+ - r\ :sub:`2`
+ - r\ :sub:`1`
+ - r\ :sub:`0`
+ - 0
+ - 0
+ - g\ :sub:`7`
+ - g\ :sub:`6`
+ - g\ :sub:`5`
+ - g\ :sub:`4`
+ - g\ :sub:`3`
+ - g\ :sub:`2`
+ - g\ :sub:`1`
+ - g\ :sub:`0`
+ - 0
+ - 0
+ - b\ :sub:`7`
+ - b\ :sub:`6`
+ - b\ :sub:`5`
+ - b\ :sub:`4`
+ - b\ :sub:`3`
+ - b\ :sub:`2`
+ - b\ :sub:`1`
+ - b\ :sub:`0`
+ - 0
+ - 0
* .. _MEDIA-BUS-FMT-ARGB888-1X32:
- MEDIA_BUS_FMT_ARGB888_1X32
@@ -1665,6 +1739,88 @@ The following table list existing packed 36bit wide RGB formats.
- 2
- 1
- 0
+ * .. _MEDIA-BUS-FMT-RGB666-1X36-CPADLO:
+
+ - MEDIA_BUS_FMT_RGB666_1X36_CPADLO
+ - 0x1020
+ -
+ - r\ :sub:`5`
+ - r\ :sub:`4`
+ - r\ :sub:`3`
+ - r\ :sub:`2`
+ - r\ :sub:`1`
+ - r\ :sub:`0`
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - g\ :sub:`5`
+ - g\ :sub:`4`
+ - g\ :sub:`3`
+ - g\ :sub:`2`
+ - g\ :sub:`1`
+ - g\ :sub:`0`
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - b\ :sub:`5`
+ - b\ :sub:`4`
+ - b\ :sub:`3`
+ - b\ :sub:`2`
+ - b\ :sub:`1`
+ - b\ :sub:`0`
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ * .. _MEDIA-BUS-FMT-RGB888-1X36-CPADLO:
+
+ - MEDIA_BUS_FMT_RGB888_1X36_CPADLO
+ - 0x1021
+ -
+ - r\ :sub:`7`
+ - r\ :sub:`6`
+ - r\ :sub:`5`
+ - r\ :sub:`4`
+ - r\ :sub:`3`
+ - r\ :sub:`2`
+ - r\ :sub:`1`
+ - r\ :sub:`0`
+ - 0
+ - 0
+ - 0
+ - 0
+ - g\ :sub:`7`
+ - g\ :sub:`6`
+ - g\ :sub:`5`
+ - g\ :sub:`4`
+ - g\ :sub:`3`
+ - g\ :sub:`2`
+ - g\ :sub:`1`
+ - g\ :sub:`0`
+ - 0
+ - 0
+ - 0
+ - 0
+ - b\ :sub:`7`
+ - b\ :sub:`6`
+ - b\ :sub:`5`
+ - b\ :sub:`4`
+ - b\ :sub:`3`
+ - b\ :sub:`2`
+ - b\ :sub:`1`
+ - b\ :sub:`0`
+ - 0
+ - 0
+ - 0
+ - 0
* .. _MEDIA-BUS-FMT-RGB121212-1X36:
- MEDIA_BUS_FMT_RGB121212_1X36
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 03/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
2021-03-10 9:55 ` [PATCH v5 01/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner Liu Ying
2021-03-10 9:55 ` [PATCH v5 02/14] media: docs: " Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 9:55 ` [PATCH v5 04/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support Liu Ying
` (10 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* Add Rob's R-b tag.
v1->v2:
* Use graph schema. (Laurent)
* Use enum instead of oneOf + const for the reg property of pixel combiner
channels. (Rob)
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 +++++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
new file mode 100644
index 00000000..50bae21
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Pixel Combiner
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
+ single display controller and manipulates the two streams to support a number
+ of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
+ either one screen, two screens, or virtual screens. The pixel combiner is
+ also responsible for generating some of the control signals for the pixel link
+ output channel.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-pixel-combiner
+ - fsl,imx8qxp-pixel-combiner
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: apb
+
+ power-domains:
+ maxItems: 1
+
+patternProperties:
+ "^channel@[0-1]$":
+ type: object
+ description: Represents a display stream of pixel combiner.
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ description: The display stream index.
+ enum: [ 0, 1 ]
+
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input endpoint of the display stream.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output endpoint of the display stream.
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - port@0
+ - port@1
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ pixel-combiner@56020000 {
+ compatible = "fsl,imx8qxp-pixel-combiner";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x56020000 0x10000>;
+ clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
+ remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
+ remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
+ };
+ };
+ };
+
+ channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ port@0 {
+ reg = <0>;
+
+ dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
+ remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
+ remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;
+ };
+ };
+ };
+ };
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 04/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (2 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 03/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 9:55 ` [PATCH v5 05/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding Liu Ying
` (9 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner.
The pixel combiner takes two output streams from a single display
controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
as either one screen, two screens, or virtual screens. The pixel
combiner is also responsible for generating some of the control signals
for the pixel link output channel. For now, the driver only supports
the bypass mode.
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* Drop the 'PC_BUF_PARA_REG' register definition. (Robert)
* Add Robert's R-b tag.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/imx/Kconfig | 8 +
drivers/gpu/drm/bridge/imx/Makefile | 1 +
.../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c | 448 +++++++++++++++++++++
5 files changed, 460 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig
create mode 100644 drivers/gpu/drm/bridge/imx/Makefile
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4110d6c..84944e0 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -256,6 +256,8 @@ source "drivers/gpu/drm/bridge/adv7511/Kconfig"
source "drivers/gpu/drm/bridge/cadence/Kconfig"
+source "drivers/gpu/drm/bridge/imx/Kconfig"
+
source "drivers/gpu/drm/bridge/synopsys/Kconfig"
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 86e7acc..bc80cae 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
obj-y += analogix/
obj-y += cadence/
+obj-y += imx/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
new file mode 100644
index 00000000..f1c91b6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -0,0 +1,8 @@
+config DRM_IMX8QXP_PIXEL_COMBINER
+ tristate "Freescale i.MX8QM/QXP pixel combiner"
+ depends on OF
+ depends on COMMON_CLK
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable pixel combiner found in
+ Freescale i.MX8qm/qxp processors.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
new file mode 100644
index 00000000..7d7c8d6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
new file mode 100644
index 00000000..0b9403a
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
@@ -0,0 +1,448 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_print.h>
+
+#define PC_CTRL_REG 0x0
+#define PC_COMBINE_ENABLE BIT(0)
+#define PC_DISP_BYPASS(n) BIT(1 + 21 * (n))
+#define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n))
+#define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n)
+#define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n))
+#define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n)
+#define PC_DISP_DVALID_POLARITY(n) BIT(4 + 11 * (n))
+#define PC_DISP_DVALID_POLARITY_POS(n) DISP_DVALID_POLARITY(n)
+#define PC_VSYNC_MASK_ENABLE BIT(5)
+#define PC_SKIP_MODE BIT(6)
+#define PC_SKIP_NUMBER_MASK GENMASK(12, 7)
+#define PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, (n))
+#define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16)
+#define PC_DISP0_PIX_DATA_FORMAT(fmt) \
+ FIELD_PREP(PC_DISP0_PIX_DATA_FORMAT_MASK, (fmt))
+#define PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19)
+#define PC_DISP1_PIX_DATA_FORMAT(fmt) \
+ FIELD_PREP(PC_DISP1_PIX_DATA_FORMAT_MASK, (fmt))
+
+#define PC_SW_RESET_REG 0x20
+#define PC_SW_RESET_N BIT(0)
+#define PC_DISP_SW_RESET_N(n) BIT(1 + (n))
+#define PC_FULL_RESET_N (PC_SW_RESET_N | \
+ PC_DISP_SW_RESET_N(0) | \
+ PC_DISP_SW_RESET_N(1))
+
+#define PC_REG_SET 0x4
+#define PC_REG_CLR 0x8
+
+#define DRIVER_NAME "imx8qxp-pixel-combiner"
+
+enum imx8qxp_pc_pix_data_format {
+ RGB,
+ YUV444,
+ YUV422,
+ SPLIT_RGB,
+};
+
+struct imx8qxp_pc_channel {
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct imx8qxp_pc *pc;
+ unsigned int stream_id;
+ bool is_available;
+};
+
+struct imx8qxp_pc {
+ struct device *dev;
+ struct imx8qxp_pc_channel ch[2];
+ struct clk *clk_apb;
+ void __iomem *base;
+};
+
+static inline u32 imx8qxp_pc_read(struct imx8qxp_pc *pc, unsigned int offset)
+{
+ return readl(pc->base + offset);
+}
+
+static inline void
+imx8qxp_pc_write(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
+{
+ writel(value, pc->base + offset);
+}
+
+static inline void
+imx8qxp_pc_write_set(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
+{
+ imx8qxp_pc_write(pc, offset + PC_REG_SET, value);
+}
+
+static inline void
+imx8qxp_pc_write_clr(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
+{
+ imx8qxp_pc_write(pc, offset + PC_REG_CLR, value);
+}
+
+static enum drm_mode_status
+imx8qxp_pc_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ if (mode->hdisplay > 2560)
+ return MODE_BAD_HVALUE;
+
+ return MODE_OK;
+}
+
+static int imx8qxp_pc_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct imx8qxp_pc_channel *ch = bridge->driver_private;
+ struct imx8qxp_pc *pc = ch->pc;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_DEV_ERROR(pc->dev,
+ "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ if (!bridge->encoder) {
+ DRM_DEV_ERROR(pc->dev, "missing encoder\n");
+ return -ENODEV;
+ }
+
+ return drm_bridge_attach(bridge->encoder,
+ ch->next_bridge, bridge,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static void
+imx8qxp_pc_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct imx8qxp_pc_channel *ch = bridge->driver_private;
+ struct imx8qxp_pc *pc = ch->pc;
+ u32 val;
+ int ret;
+
+ ret = pm_runtime_get_sync(pc->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(pc->dev,
+ "failed to get runtime PM sync: %d\n", ret);
+
+ ret = clk_prepare_enable(pc->clk_apb);
+ if (ret)
+ DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
+ __func__, ret);
+
+ /* HSYNC to pixel link is active low. */
+ imx8qxp_pc_write_clr(pc, PC_CTRL_REG,
+ PC_DISP_HSYNC_POLARITY(ch->stream_id));
+
+ /* VSYNC to pixel link is active low. */
+ imx8qxp_pc_write_clr(pc, PC_CTRL_REG,
+ PC_DISP_VSYNC_POLARITY(ch->stream_id));
+
+ /* Data enable to pixel link is active high. */
+ imx8qxp_pc_write_set(pc, PC_CTRL_REG,
+ PC_DISP_DVALID_POLARITY(ch->stream_id));
+
+ /* Mask the first frame output which may be incomplete. */
+ imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_VSYNC_MASK_ENABLE);
+
+ /* Only support RGB currently. */
+ val = imx8qxp_pc_read(pc, PC_CTRL_REG);
+ if (ch->stream_id == 0) {
+ val &= ~PC_DISP0_PIX_DATA_FORMAT_MASK;
+ val |= PC_DISP0_PIX_DATA_FORMAT(RGB);
+ } else {
+ val &= ~PC_DISP1_PIX_DATA_FORMAT_MASK;
+ val |= PC_DISP1_PIX_DATA_FORMAT(RGB);
+ }
+ imx8qxp_pc_write(pc, PC_CTRL_REG, val);
+
+ /* Only support bypass mode currently. */
+ imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_DISP_BYPASS(ch->stream_id));
+
+ clk_disable_unprepare(pc->clk_apb);
+}
+
+static void imx8qxp_pc_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pc_channel *ch = bridge->driver_private;
+ struct imx8qxp_pc *pc = ch->pc;
+ int ret;
+
+ ret = pm_runtime_put(pc->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(pc->dev, "failed to put runtime PM: %d\n", ret);
+}
+
+static const u32 imx8qxp_pc_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
+ MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
+};
+
+static bool imx8qxp_pc_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qxp_pc_bus_output_fmts); i++) {
+ if (imx8qxp_pc_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qxp_pc_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmts;
+
+ if (!imx8qxp_pc_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_RGB888_1X36_CPADLO:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X30_CPADLO;
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X36_CPADLO:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X30_CPADLO;
+ break;
+ default:
+ kfree(input_fmts);
+ input_fmts = NULL;
+ break;
+ }
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qxp_pc_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qxp_pc_bus_output_fmts);
+ return kmemdup(imx8qxp_pc_bus_output_fmts,
+ sizeof(imx8qxp_pc_bus_output_fmts), GFP_KERNEL);
+}
+
+static const struct drm_bridge_funcs imx8qxp_pc_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .mode_valid = imx8qxp_pc_bridge_mode_valid,
+ .attach = imx8qxp_pc_bridge_attach,
+ .mode_set = imx8qxp_pc_bridge_mode_set,
+ .atomic_disable = imx8qxp_pc_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qxp_pc_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qxp_pc_bridge_atomic_get_output_bus_fmts,
+};
+
+static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
+{
+ struct imx8qxp_pc *pc;
+ struct imx8qxp_pc_channel *ch;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *child, *remote;
+ u32 i;
+ int ret;
+
+ pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
+ if (!pc)
+ return -ENOMEM;
+
+ pc->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pc->base))
+ return PTR_ERR(pc->base);
+
+ pc->dev = dev;
+
+ pc->clk_apb = devm_clk_get(dev, "apb");
+ if (IS_ERR(pc->clk_apb)) {
+ ret = PTR_ERR(pc->clk_apb);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get apb clock: %d\n",
+ ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, pc);
+ pm_runtime_enable(dev);
+
+ for_each_available_child_of_node(np, child) {
+ ret = of_property_read_u32(child, "reg", &i);
+ if (ret || i > 1) {
+ ret = -EINVAL;
+ DRM_DEV_ERROR(dev,
+ "invalid channel(%u) node address\n", i);
+ goto free_child;
+ }
+
+ ch = &pc->ch[i];
+ ch->pc = pc;
+ ch->stream_id = i;
+
+ remote = of_graph_get_remote_node(child, 1, 0);
+ if (!remote) {
+ ret = -ENODEV;
+ DRM_DEV_ERROR(dev,
+ "channel%u failed to get port1's remote node: %d\n",
+ i, ret);
+ goto free_child;
+ }
+
+ ch->next_bridge = of_drm_find_bridge(remote);
+ if (!ch->next_bridge) {
+ of_node_put(remote);
+ ret = -EPROBE_DEFER;
+ DRM_DEV_DEBUG_DRIVER(dev,
+ "channel%u failed to find next bridge: %d\n",
+ i, ret);
+ goto free_child;
+ }
+
+ of_node_put(remote);
+
+ ch->bridge.driver_private = ch;
+ ch->bridge.funcs = &imx8qxp_pc_bridge_funcs;
+ ch->bridge.of_node = child;
+ ch->is_available = true;
+
+ drm_bridge_add(&ch->bridge);
+ }
+
+ return 0;
+
+free_child:
+ of_node_put(child);
+
+ if (i == 1 && pc->ch[0].next_bridge)
+ drm_bridge_remove(&pc->ch[0].bridge);
+
+ pm_runtime_disable(dev);
+ return ret;
+}
+
+static int imx8qxp_pc_bridge_remove(struct platform_device *pdev)
+{
+ struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
+ struct imx8qxp_pc_channel *ch;
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ ch = &pc->ch[i];
+
+ if (!ch->is_available)
+ continue;
+
+ drm_bridge_remove(&ch->bridge);
+ ch->is_available = false;
+ }
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static int __maybe_unused imx8qxp_pc_runtime_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = clk_prepare_enable(pc->clk_apb);
+ if (ret)
+ DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
+ __func__, ret);
+
+ /* Disable pixel combiner by full reset. */
+ imx8qxp_pc_write_clr(pc, PC_SW_RESET_REG, PC_FULL_RESET_N);
+
+ clk_disable_unprepare(pc->clk_apb);
+
+ /* Ensure the reset takes effect. */
+ usleep_range(10, 20);
+
+ return ret;
+}
+
+static int __maybe_unused imx8qxp_pc_runtime_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = clk_prepare_enable(pc->clk_apb);
+ if (ret) {
+ DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* out of reset */
+ imx8qxp_pc_write_set(pc, PC_SW_RESET_REG, PC_FULL_RESET_N);
+
+ clk_disable_unprepare(pc->clk_apb);
+
+ return ret;
+}
+
+static const struct dev_pm_ops imx8qxp_pc_pm_ops = {
+ SET_RUNTIME_PM_OPS(imx8qxp_pc_runtime_suspend,
+ imx8qxp_pc_runtime_resume, NULL)
+};
+
+static const struct of_device_id imx8qxp_pc_dt_ids[] = {
+ { .compatible = "fsl,imx8qm-pixel-combiner", },
+ { .compatible = "fsl,imx8qxp-pixel-combiner", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qxp_pc_dt_ids);
+
+static struct platform_driver imx8qxp_pc_bridge_driver = {
+ .probe = imx8qxp_pc_bridge_probe,
+ .remove = imx8qxp_pc_bridge_remove,
+ .driver = {
+ .pm = &imx8qxp_pc_pm_ops,
+ .name = DRIVER_NAME,
+ .of_match_table = imx8qxp_pc_dt_ids,
+ },
+};
+module_platform_driver(imx8qxp_pc_bridge_driver);
+
+MODULE_DESCRIPTION("i.MX8QM/QXP pixel combiner bridge driver");
+MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 05/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (3 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 04/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 9:55 ` [PATCH v5 06/14] drm/bridge: imx: Add i.MX8qm/qxp display pixel link support Liu Ying
` (8 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds bindings for i.MX8qm/qxp display pixel link.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* Add Rob's R-b tag.
v1->v2:
* Use graph schema. (Laurent)
* Require all four pixel link output ports. (Laurent)
* Mention pixel link is accessed via SCU firmware. (Rob)
.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++++++++++++++++++++
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
new file mode 100644
index 00000000..3af67cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Pixel Link
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
+ asynchronous linkage between pixel sources(display controller or
+ camera module) and pixel consumers(imaging or displays).
+ It consists of two distinct functions, a pixel transfer function and a
+ control interface. Multiple pixel channels can exist per one control channel.
+ This binding documentation is only for pixel links whose pixel sources are
+ display controllers.
+
+ The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
+ firmware.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-dc-pixel-link
+ - fsl,imx8qxp-dc-pixel-link
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The pixel link input port node from upstream video source.
+
+ patternProperties:
+ "^port@[1-4]$":
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The pixel link output port node to downstream bridge.
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+ - port@3
+ - port@4
+
+required:
+ - compatible
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ dc0-pixel-link0 {
+ compatible = "fsl,imx8qxp-dc-pixel-link";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* from dc0 pixel combiner channel0 */
+ port@0 {
+ reg = <0>;
+
+ dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
+ remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
+ };
+ };
+
+ /* to PXL2DPIs in MIPI/LVDS combo subsystems */
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
+ };
+
+ dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
+ };
+ };
+
+ /* unused */
+ port@2 {
+ reg = <2>;
+ };
+
+ /* unused */
+ port@3 {
+ reg = <3>;
+ };
+
+ /* to imaging subsystem */
+ port@4 {
+ reg = <4>;
+ };
+ };
+ };
--
2.7.4
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 06/14] drm/bridge: imx: Add i.MX8qm/qxp display pixel link support
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (4 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 05/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 9:55 ` [PATCH v5 07/14] dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding Liu Ying
` (7 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays). It consists of two distinct
functions, a pixel transfer function and a control interface.
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* Make a comment occupy a line. (Robert)
* Add Robert's R-b tag.
v3->v4:
* No change.
v2->v3:
* Drop two macros which help define functions and define them directly.
* Properly disable all pixel link controls to POR value by calling
imx8qxp_pixel_link_disable_all_controls() from
imx8qxp_pixel_link_bridge_probe().
v1->v2:
* Rewrite the function to find the next bridge by properly using OF APIs
and dropping unnecessary DT validation. (Rob)
drivers/gpu/drm/bridge/imx/Kconfig | 8 +
drivers/gpu/drm/bridge/imx/Makefile | 1 +
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 427 ++++++++++++++++++++++++
3 files changed, 436 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index f1c91b6..4d1f027 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -6,3 +6,11 @@ config DRM_IMX8QXP_PIXEL_COMBINER
help
Choose this to enable pixel combiner found in
Freescale i.MX8qm/qxp processors.
+
+config DRM_IMX8QXP_PIXEL_LINK
+ tristate "Freescale i.MX8QM/QXP display pixel link"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable display pixel link found in
+ Freescale i.MX8qm/qxp processors.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index 7d7c8d6..c15469f 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
new file mode 100644
index 00000000..a549624
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/firmware/imx/svc/misc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_print.h>
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+#define DRIVER_NAME "imx8qxp-display-pixel-link"
+#define PL_MAX_MST_ADDR 3
+#define PL_MAX_NEXT_BRIDGES 2
+
+struct imx8qxp_pixel_link {
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct device *dev;
+ struct imx_sc_ipc *ipc_handle;
+ int id;
+ int stream_id;
+ int dc_id;
+ u32 sink_rsc;
+ u32 mst_addr;
+ u8 mst_addr_ctrl;
+ u8 mst_en_ctrl;
+ u8 mst_vld_ctrl;
+ u8 sync_ctrl;
+};
+
+static void imx8qxp_pixel_link_enable_mst_en(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_en_ctrl, true);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to enable DC%d stream%d pixel link mst_en: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+}
+
+static void imx8qxp_pixel_link_enable_mst_vld(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_vld_ctrl, true);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to enable DC%d stream%d pixel link mst_vld: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+}
+
+static void imx8qxp_pixel_link_enable_sync(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->sync_ctrl, true);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to enable DC%d stream%d pixel link sync: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+}
+
+static int imx8qxp_pixel_link_disable_mst_en(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_en_ctrl, false);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to disable DC%d stream%d pixel link mst_en: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+
+ return ret;
+}
+
+static int imx8qxp_pixel_link_disable_mst_vld(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_vld_ctrl, false);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to disable DC%d stream%d pixel link mst_vld: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+
+ return ret;
+}
+
+static int imx8qxp_pixel_link_disable_sync(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->sync_ctrl, false);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to disable DC%d stream%d pixel link sync: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+
+ return ret;
+}
+
+static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle,
+ pl->sink_rsc, pl->mst_addr_ctrl,
+ pl->mst_addr);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to set DC%d stream%d pixel link mst addr(%u): %d\n",
+ pl->dc_id, pl->stream_id, pl->mst_addr, ret);
+}
+
+static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_DEV_ERROR(pl->dev,
+ "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ if (!bridge->encoder) {
+ DRM_DEV_ERROR(pl->dev, "missing encoder\n");
+ return -ENODEV;
+ }
+
+ return drm_bridge_attach(bridge->encoder,
+ pl->next_bridge, bridge,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static void
+imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ imx8qxp_pixel_link_set_mst_addr(pl);
+}
+
+static void imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ imx8qxp_pixel_link_enable_mst_en(pl);
+ imx8qxp_pixel_link_enable_mst_vld(pl);
+ imx8qxp_pixel_link_enable_sync(pl);
+}
+
+static void imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ imx8qxp_pixel_link_disable_mst_en(pl);
+ imx8qxp_pixel_link_disable_mst_vld(pl);
+ imx8qxp_pixel_link_disable_sync(pl);
+}
+
+static const u32 imx8qxp_pixel_link_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
+ MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
+};
+
+static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) {
+ if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmts;
+
+ if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ input_fmts[0] = output_fmt;
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts);
+ return kmemdup(imx8qxp_pixel_link_bus_output_fmts,
+ sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL);
+}
+
+static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .attach = imx8qxp_pixel_link_bridge_attach,
+ .mode_set = imx8qxp_pixel_link_bridge_mode_set,
+ .atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable,
+ .atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts,
+};
+
+static int imx8qxp_pixel_link_disable_all_controls(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx8qxp_pixel_link_disable_mst_en(pl);
+ if (ret)
+ return ret;
+
+ ret = imx8qxp_pixel_link_disable_mst_vld(pl);
+ if (ret)
+ return ret;
+
+ return imx8qxp_pixel_link_disable_sync(pl);
+}
+
+static struct drm_bridge *
+imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl)
+{
+ struct device_node *np = pl->dev->of_node;
+ struct device_node *port, *remote;
+ struct drm_bridge *next_bridge[PL_MAX_NEXT_BRIDGES];
+ u32 port_id;
+ bool found_port = false;
+ int reg, ep_cnt = 0;
+ /* select the first next bridge by default */
+ int bridge_sel = 0;
+
+ for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) {
+ port = of_graph_get_port_by_id(np, port_id);
+ if (!port)
+ continue;
+
+ if (of_device_is_available(port)) {
+ found_port = true;
+ of_node_put(port);
+ break;
+ }
+
+ of_node_put(port);
+ }
+
+ if (!found_port) {
+ DRM_DEV_ERROR(pl->dev, "no available output port\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ for (reg = 0; reg < PL_MAX_NEXT_BRIDGES; reg++) {
+ remote = of_graph_get_remote_node(np, port_id, reg);
+ if (!remote)
+ continue;
+
+ if (!of_device_is_available(remote->parent)) {
+ DRM_DEV_DEBUG(pl->dev,
+ "port%u endpoint%u remote parent is not available\n",
+ port_id, reg);
+ of_node_put(remote);
+ continue;
+ }
+
+ next_bridge[ep_cnt] = of_drm_find_bridge(remote);
+ if (!next_bridge[ep_cnt]) {
+ of_node_put(remote);
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ /* specially select the next bridge with companion PXL2DPI */
+ if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL))
+ bridge_sel = ep_cnt;
+
+ ep_cnt++;
+
+ of_node_put(remote);
+ }
+
+ pl->mst_addr = port_id - 1;
+
+ return next_bridge[bridge_sel];
+}
+
+static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
+{
+ struct imx8qxp_pixel_link *pl;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
+ if (!pl)
+ return -ENOMEM;
+
+ ret = imx_scu_get_handle(&pl->ipc_handle);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
+ ret);
+ return ret;
+ }
+
+ pl->id = of_alias_get_id(np, "dc_pl");
+ if (pl->id < 0) {
+ DRM_DEV_ERROR(dev,
+ "failed to get pixel link node alias id: %d\n",
+ pl->id);
+ return pl->id;
+ }
+
+ pl->dev = dev;
+
+ pl->dc_id = pl->id / 2;
+ pl->stream_id = pl->id % 2;
+
+ pl->sink_rsc = pl->dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0;
+
+ if (pl->stream_id == 0) {
+ pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST1_ADDR;
+ pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST1_ENB;
+ pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST1_VLD;
+ pl->sync_ctrl = IMX_SC_C_SYNC_CTRL0;
+ } else {
+ pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST2_ADDR;
+ pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST2_ENB;
+ pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST2_VLD;
+ pl->sync_ctrl = IMX_SC_C_SYNC_CTRL1;
+ }
+
+ /* disable all controls to POR default */
+ ret = imx8qxp_pixel_link_disable_all_controls(pl);
+ if (ret)
+ return ret;
+
+ pl->next_bridge = imx8qxp_pixel_link_find_next_bridge(pl);
+ if (IS_ERR(pl->next_bridge)) {
+ ret = PTR_ERR(pl->next_bridge);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
+ ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, pl);
+
+ pl->bridge.driver_private = pl;
+ pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs;
+ pl->bridge.of_node = np;
+
+ drm_bridge_add(&pl->bridge);
+
+ return ret;
+}
+
+static int imx8qxp_pixel_link_bridge_remove(struct platform_device *pdev)
+{
+ struct imx8qxp_pixel_link *pl = platform_get_drvdata(pdev);
+
+ drm_bridge_remove(&pl->bridge);
+
+ return 0;
+}
+
+static const struct of_device_id imx8qxp_pixel_link_dt_ids[] = {
+ { .compatible = "fsl,imx8qm-dc-pixel-link", },
+ { .compatible = "fsl,imx8qxp-dc-pixel-link", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qxp_pixel_link_dt_ids);
+
+static struct platform_driver imx8qxp_pixel_link_bridge_driver = {
+ .probe = imx8qxp_pixel_link_bridge_probe,
+ .remove = imx8qxp_pixel_link_bridge_remove,
+ .driver = {
+ .of_match_table = imx8qxp_pixel_link_dt_ids,
+ .name = DRIVER_NAME,
+ },
+};
+module_platform_driver(imx8qxp_pixel_link_bridge_driver);
+
+MODULE_DESCRIPTION("i.MX8QXP/QM display pixel link bridge driver");
+MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.7.4
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 07/14] dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (5 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 06/14] drm/bridge: imx: Add i.MX8qm/qxp display pixel link support Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-16 22:38 ` Rob Herring
2021-03-10 9:55 ` [PATCH v5 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding Liu Ying
` (6 subsequent siblings)
13 siblings, 1 reply; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* Newly introduced in v5. (Rob)
.../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml | 202 +++++++++++++++++++++
1 file changed, 202 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
diff --git a/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
new file mode 100644
index 00000000..0e724d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
@@ -0,0 +1,202 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ As a system controller, the Freescale i.MX8qm/qxp Control and Status
+ Registers(CSR) module represents a set of miscellaneous registers of a
+ specific subsystem. It may provide control and/or status report interfaces
+ to a mix of standalone hardware devices within that subsystem. One typical
+ use-case is for some other nodes to acquire a reference to the syscon node
+ by phandle, and the other typical use-case is that the operating system
+ should consider all subnodes of the CSR module as separate child devices.
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qxp-mipi-lvds-csr
+ - fsl,imx8qm-lvds-csr
+ required:
+ - compatible
+
+properties:
+ $nodename:
+ pattern: "^syscon@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - fsl,imx8qxp-mipi-lvds-csr
+ - fsl,imx8qm-lvds-csr
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ipg
+
+patternProperties:
+ "^(ldb|phy|pxl2dpi)$":
+ type: object
+ description: The possible child devices of the CSR module.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qxp-mipi-lvds-csr
+ then:
+ required:
+ - pxl2dpi
+ - ldb
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qm-lvds-csr
+ then:
+ required:
+ - phy
+ - ldb
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ mipi_lvds_0_csr: syscon@56221000 {
+ compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
+ reg = <0x56221000 0x1000>;
+ clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "ipg";
+
+ mipi_lvds_0_pxl2dpi: pxl2dpi {
+ compatible = "fsl,imx8qxp-pxl2dpi";
+ fsl,sc-resource = <IMX_SC_R_MIPI_0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+ };
+ };
+
+ mipi_lvds_0_ldb: ldb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ /* ... */
+ };
+ };
+
+ channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ /* ... */
+ };
+ };
+ };
+ };
+
+ mipi_lvds_0_phy: phy@56228300 {
+ compatible = "fsl,imx8qxp-mipi-dphy";
+ reg = <0x56228300 0x100>;
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
+ clock-names = "phy_ref";
+ #phy-cells = <0>;
+ fsl,syscon = <&mipi_lvds_0_csr>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (6 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 07/14] dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-16 22:40 ` Rob Herring
2021-03-10 9:55 ` [PATCH v5 09/14] drm/bridge: imx: Add i.MX8qxp pixel link to DPI support Liu Ying
` (5 subsequent siblings)
13 siblings, 1 reply; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* No change.
v3->v4:
* Add 'fsl,sc-resource' property. (Rob)
v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module controls PXL2DPI.
v1->v2:
* Use graph schema. (Laurent)
.../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 108 +++++++++++++++++++++
1 file changed, 108 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
new file mode 100644
index 00000000..e4e77fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
+ interfaces the pixel link 36-bit data output and the DSI controller’s
+ MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
+ used in LVDS mode, to remap the pixel color codings between those modules.
+ This module is purely combinatorial.
+
+ The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
+ The CSR module, as a system controller, contains the PXL2DPI's configuration
+ register.
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-pxl2dpi
+
+ fsl,sc-resource:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The SCU resource ID associated with this PXL2DPI instance.
+
+ power-domains:
+ maxItems: 1
+
+ fsl,companion-pxl2dpi:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ A phandle which points to companion PXL2DPI which is used by downstream
+ LVDS Display Bridge(LDB) in split mode.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The PXL2DPI input port node from pixel link.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The PXL2DPI output port node to downstream bridge.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - fsl,sc-resource
+ - power-domains
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ pxl2dpi {
+ compatible = "fsl,imx8qxp-pxl2dpi";
+ fsl,sc-resource = <IMX_SC_R_MIPI_0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+ };
+ };
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 09/14] drm/bridge: imx: Add i.MX8qxp pixel link to DPI support
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (7 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 9:55 ` [PATCH v5 10/14] drm/bridge: imx: Add LDB driver helper support Liu Ying
` (4 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color codings between those modules. The PXL2DPI is purely
combinatorial.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* No change.
v3->v4:
* Use 'fsl,sc-resource' DT property to get the SCU resource ID associated with
the PXL2DPI instance instead of using alias ID. (Rob)
v2->v3:
* Call syscon_node_to_regmap() to get regmap instead of
syscon_regmap_lookup_by_phandle().
v1->v2:
* Drop unnecessary port availability check.
drivers/gpu/drm/bridge/imx/Kconfig | 8 +
drivers/gpu/drm/bridge/imx/Makefile | 1 +
drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 485 +++++++++++++++++++++++++++
3 files changed, 494 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index 4d1f027..1ea1ce7 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -14,3 +14,11 @@ config DRM_IMX8QXP_PIXEL_LINK
help
Choose this to enable display pixel link found in
Freescale i.MX8qm/qxp processors.
+
+config DRM_IMX8QXP_PIXEL_LINK_TO_DPI
+ tristate "Freescale i.MX8QXP pixel link to display pixel interface"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable pixel link to display pixel interface(PXL2DPI)
+ found in Freescale i.MX8qxp processor.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index c15469f..e74dd64 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
new file mode 100644
index 00000000..6696855
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
@@ -0,0 +1,485 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/firmware/imx/svc/misc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+#define PXL2DPI_CTRL 0x40
+#define CFG1_16BIT 0x0
+#define CFG2_16BIT 0x1
+#define CFG3_16BIT 0x2
+#define CFG1_18BIT 0x3
+#define CFG2_18BIT 0x4
+#define CFG_24BIT 0x5
+
+#define DRIVER_NAME "imx8qxp-pxl2dpi"
+
+struct imx8qxp_pxl2dpi {
+ struct regmap *regmap;
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct drm_bridge *companion;
+ struct device *dev;
+ struct imx_sc_ipc *ipc_handle;
+ u32 sc_resource;
+ u32 in_bus_format;
+ u32 out_bus_format;
+ u32 pl_sel;
+};
+
+#define bridge_to_p2d(b) container_of(b, struct imx8qxp_pxl2dpi, bridge)
+
+static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_DEV_ERROR(p2d->dev,
+ "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ if (!bridge->encoder) {
+ DRM_DEV_ERROR(p2d->dev, "missing encoder\n");
+ return -ENODEV;
+ }
+
+ return drm_bridge_attach(bridge->encoder,
+ p2d->next_bridge, bridge,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static int
+imx8qxp_pxl2dpi_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+
+ p2d->in_bus_format = bridge_state->input_bus_cfg.format;
+ p2d->out_bus_format = bridge_state->output_bus_cfg.format;
+
+ return 0;
+}
+
+static void
+imx8qxp_pxl2dpi_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+ struct imx8qxp_pxl2dpi *companion_p2d;
+ int ret;
+
+ ret = pm_runtime_get_sync(p2d->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to get runtime PM sync: %d\n", ret);
+
+ ret = imx_sc_misc_set_control(p2d->ipc_handle, p2d->sc_resource,
+ IMX_SC_C_PXL_LINK_SEL, p2d->pl_sel);
+ if (ret)
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to set pixel link selection(%u): %d\n",
+ p2d->pl_sel, ret);
+
+ switch (p2d->out_bus_format) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG_24BIT);
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG2_18BIT);
+ break;
+ default:
+ DRM_DEV_ERROR(p2d->dev,
+ "unsupported output bus format 0x%08x\n",
+ p2d->out_bus_format);
+ }
+
+ if (p2d->companion) {
+ companion_p2d = bridge_to_p2d(p2d->companion);
+
+ companion_p2d->in_bus_format = p2d->in_bus_format;
+ companion_p2d->out_bus_format = p2d->out_bus_format;
+
+ p2d->companion->funcs->mode_set(p2d->companion, mode,
+ adjusted_mode);
+ }
+}
+
+static void
+imx8qxp_pxl2dpi_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+ int ret;
+
+ ret = pm_runtime_put(p2d->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(p2d->dev, "failed to put runtime PM: %d\n", ret);
+
+ if (p2d->companion)
+ p2d->companion->funcs->atomic_disable(p2d->companion,
+ old_bridge_state);
+}
+
+static const u32 imx8qxp_pxl2dpi_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB888_1X24,
+ MEDIA_BUS_FMT_RGB666_1X24_CPADHI,
+};
+
+static bool imx8qxp_pxl2dpi_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts); i++) {
+ if (imx8qxp_pxl2dpi_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmts;
+
+ if (!imx8qxp_pxl2dpi_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO;
+ break;
+ default:
+ kfree(input_fmts);
+ input_fmts = NULL;
+ break;
+ }
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts);
+ return kmemdup(imx8qxp_pxl2dpi_bus_output_fmts,
+ sizeof(imx8qxp_pxl2dpi_bus_output_fmts), GFP_KERNEL);
+}
+
+static const struct drm_bridge_funcs imx8qxp_pxl2dpi_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .attach = imx8qxp_pxl2dpi_bridge_attach,
+ .atomic_check = imx8qxp_pxl2dpi_bridge_atomic_check,
+ .mode_set = imx8qxp_pxl2dpi_bridge_mode_set,
+ .atomic_disable = imx8qxp_pxl2dpi_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts,
+};
+
+static struct device_node *
+imx8qxp_pxl2dpi_get_available_ep_from_port(struct imx8qxp_pxl2dpi *p2d,
+ u32 port_id)
+{
+ struct device_node *port, *ep;
+ int ep_cnt;
+
+ port = of_graph_get_port_by_id(p2d->dev->of_node, port_id);
+ if (!port) {
+ DRM_DEV_ERROR(p2d->dev, "failed to get port@%u\n", port_id);
+ return ERR_PTR(-ENODEV);
+ }
+
+ ep_cnt = of_get_available_child_count(port);
+ if (ep_cnt == 0) {
+ DRM_DEV_ERROR(p2d->dev, "no available endpoints of port@%u\n",
+ port_id);
+ ep = ERR_PTR(-ENODEV);
+ goto out;
+ } else if (ep_cnt > 1) {
+ DRM_DEV_ERROR(p2d->dev,
+ "invalid available endpoints of port@%u\n", port_id);
+ ep = ERR_PTR(-ENOTSUPP);
+ goto out;
+ }
+
+ ep = of_get_next_available_child(port, NULL);
+ if (!ep) {
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to get available endpoint of port@%u\n",
+ port_id);
+ ep = ERR_PTR(-ENODEV);
+ goto out;
+ }
+out:
+ of_node_put(port);
+ return ep;
+}
+
+static struct drm_bridge *
+imx8qxp_pxl2dpi_find_next_bridge(struct imx8qxp_pxl2dpi *p2d)
+{
+ struct device_node *ep, *remote;
+ struct drm_bridge *next_bridge;
+ int ret;
+
+ ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 1);
+ if (IS_ERR(ep)) {
+ ret = PTR_ERR(ep);
+ return ERR_PTR(ret);
+ }
+
+ remote = of_graph_get_remote_port_parent(ep);
+ if (!remote || !of_device_is_available(remote)) {
+ DRM_DEV_ERROR(p2d->dev, "no available remote\n");
+ next_bridge = ERR_PTR(-ENODEV);
+ goto out;
+ } else if (!of_device_is_available(remote->parent)) {
+ DRM_DEV_ERROR(p2d->dev, "remote parent is not available\n");
+ next_bridge = ERR_PTR(-ENODEV);
+ goto out;
+ }
+
+ next_bridge = of_drm_find_bridge(remote);
+ if (!next_bridge) {
+ next_bridge = ERR_PTR(-EPROBE_DEFER);
+ goto out;
+ }
+out:
+ of_node_put(remote);
+ of_node_put(ep);
+
+ return next_bridge;
+}
+
+static int imx8qxp_pxl2dpi_set_pixel_link_sel(struct imx8qxp_pxl2dpi *p2d)
+{
+ struct device_node *ep;
+ struct of_endpoint endpoint;
+ int ret;
+
+ ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 0);
+ if (IS_ERR(ep))
+ return PTR_ERR(ep);
+
+ ret = of_graph_parse_endpoint(ep, &endpoint);
+ if (ret) {
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to parse endpoint of port@0: %d\n", ret);
+ goto out;
+ }
+
+ p2d->pl_sel = endpoint.id;
+out:
+ of_node_put(ep);
+
+ return ret;
+}
+
+static int imx8qxp_pxl2dpi_parse_dt_companion(struct imx8qxp_pxl2dpi *p2d)
+{
+ struct imx8qxp_pxl2dpi *companion_p2d;
+ struct device *dev = p2d->dev;
+ struct device_node *companion;
+ struct device_node *port1, *port2;
+ const struct of_device_id *match;
+ int dual_link;
+ int ret = 0;
+
+ /* Locate the companion PXL2DPI for dual-link operation, if any. */
+ companion = of_parse_phandle(dev->of_node, "fsl,companion-pxl2dpi", 0);
+ if (!companion)
+ return 0;
+
+ if (!of_device_is_available(companion)) {
+ DRM_DEV_ERROR(dev, "companion PXL2DPI is not available\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ /*
+ * Sanity check: the companion bridge must have the same compatible
+ * string.
+ */
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!of_device_is_compatible(companion, match->compatible)) {
+ DRM_DEV_ERROR(dev, "companion PXL2DPI is incompatible\n");
+ ret = -ENXIO;
+ goto out;
+ }
+
+ p2d->companion = of_drm_find_bridge(companion);
+ if (!p2d->companion) {
+ ret = -EPROBE_DEFER;
+ DRM_DEV_DEBUG_DRIVER(p2d->dev,
+ "failed to find companion bridge: %d\n", ret);
+ goto out;
+ }
+
+ companion_p2d = bridge_to_p2d(p2d->companion);
+
+ /*
+ * We need to work out if the sink is expecting us to function in
+ * dual-link mode. We do this by looking at the DT port nodes that
+ * the next bridges are connected to. If they are marked as expecting
+ * even pixels and odd pixels than we need to use the companion PXL2DPI.
+ */
+ port1 = of_graph_get_port_by_id(p2d->next_bridge->of_node, 1);
+ port2 = of_graph_get_port_by_id(companion_p2d->next_bridge->of_node, 1);
+ dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
+ of_node_put(port1);
+ of_node_put(port2);
+
+ if (dual_link < 0) {
+ ret = dual_link;
+ DRM_DEV_ERROR(dev, "failed to get dual link pixel order: %d\n",
+ ret);
+ goto out;
+ }
+
+ DRM_DEV_DEBUG_DRIVER(dev,
+ "dual-link configuration detected (companion bridge %pOF)\n",
+ companion);
+out:
+ of_node_put(companion);
+ return ret;
+}
+
+static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev)
+{
+ struct imx8qxp_pxl2dpi *p2d;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ p2d = devm_kzalloc(dev, sizeof(*p2d), GFP_KERNEL);
+ if (!p2d)
+ return -ENOMEM;
+
+ p2d->regmap = syscon_node_to_regmap(np->parent);
+ if (IS_ERR(p2d->regmap)) {
+ ret = PTR_ERR(p2d->regmap);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ ret = imx_scu_get_handle(&p2d->ipc_handle);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
+ ret);
+ return ret;
+ }
+
+ p2d->dev = dev;
+
+ ret = of_property_read_u32(np, "fsl,sc-resource", &p2d->sc_resource);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to get SC resource %d\n", ret);
+ return ret;
+ }
+
+ p2d->next_bridge = imx8qxp_pxl2dpi_find_next_bridge(p2d);
+ if (IS_ERR(p2d->next_bridge)) {
+ ret = PTR_ERR(p2d->next_bridge);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = imx8qxp_pxl2dpi_set_pixel_link_sel(p2d);
+ if (ret)
+ return ret;
+
+ ret = imx8qxp_pxl2dpi_parse_dt_companion(p2d);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, p2d);
+ pm_runtime_enable(dev);
+
+ p2d->bridge.driver_private = p2d;
+ p2d->bridge.funcs = &imx8qxp_pxl2dpi_bridge_funcs;
+ p2d->bridge.of_node = np;
+
+ drm_bridge_add(&p2d->bridge);
+
+ return ret;
+}
+
+static int imx8qxp_pxl2dpi_bridge_remove(struct platform_device *pdev)
+{
+ struct imx8qxp_pxl2dpi *p2d = platform_get_drvdata(pdev);
+
+ drm_bridge_remove(&p2d->bridge);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id imx8qxp_pxl2dpi_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-pxl2dpi", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qxp_pxl2dpi_dt_ids);
+
+static struct platform_driver imx8qxp_pxl2dpi_bridge_driver = {
+ .probe = imx8qxp_pxl2dpi_bridge_probe,
+ .remove = imx8qxp_pxl2dpi_bridge_remove,
+ .driver = {
+ .of_match_table = imx8qxp_pxl2dpi_dt_ids,
+ .name = DRIVER_NAME,
+ },
+};
+module_platform_driver(imx8qxp_pxl2dpi_bridge_driver);
+
+MODULE_DESCRIPTION("i.MX8QXP pixel link to DPI bridge driver");
+MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 10/14] drm/bridge: imx: Add LDB driver helper support
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (8 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 09/14] drm/bridge: imx: Add i.MX8qxp pixel link to DPI support Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 9:55 ` [PATCH v5 11/14] dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding Liu Ying
` (3 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds a helper to support LDB drm bridge drivers for
i.MX SoCs. Helper functions supported by this helper should
implement common logics for all LDB modules embedded in i.MX SoCs.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* Make imx-ldb-helper be a pure object to be linked with i.MX8qxp LDB bridge
driver and i.MX8qm LDB bridge driver. (Robert)
* Move 'imx_ldb_helper.h' to 'drivers/gpu/drm/bridge/imx/imx-ldb-helper.h'.
(Robert)
* s/__FSL_IMX_LDB__/__IMX_LDB_HELPER__/ for 'imx-ldb-helper.h'.
v3->v4:
* No change.
v2->v3:
* Call syscon_node_to_regmap() to get regmap instead of
syscon_regmap_lookup_by_phandle().
v1->v2:
* No change.
drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 232 ++++++++++++++++++++++++++++
drivers/gpu/drm/bridge/imx/imx-ldb-helper.h | 98 ++++++++++++
2 files changed, 330 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.h
diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
new file mode 100644
index 00000000..d01c4ff9
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix
+ * Copyright 2019,2020 NXP
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+
+#include "imx-ldb-helper.h"
+
+bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch)
+{
+ return ldb_ch->link_type == LDB_CH_SINGLE_LINK;
+}
+
+bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch)
+{
+ return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS ||
+ ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
+}
+
+int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+
+ ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format;
+ ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format;
+
+ return 0;
+}
+
+void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+
+ if (is_split)
+ ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
+
+ switch (ldb_ch->out_bus_format) {
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
+ LDB_BIT_MAP_CH0_JEIDA;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
+ LDB_BIT_MAP_CH1_JEIDA;
+ break;
+ }
+}
+
+void ldb_bridge_enable_helper(struct drm_bridge *bridge)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+
+ /*
+ * Platform specific bridge drivers should set ldb_ctrl properly
+ * for the enablement, so just write the ctrl_reg here.
+ */
+ regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
+}
+
+void ldb_bridge_disable_helper(struct drm_bridge *bridge)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+
+ regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
+}
+
+int ldb_bridge_attach_helper(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_DEV_ERROR(ldb->dev,
+ "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ if (!bridge->encoder) {
+ DRM_DEV_ERROR(ldb->dev, "missing encoder\n");
+ return -ENODEV;
+ }
+
+ return drm_bridge_attach(bridge->encoder,
+ ldb_ch->next_bridge, bridge,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+int ldb_init_helper(struct ldb *ldb)
+{
+ struct device *dev = ldb->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *child;
+ int ret;
+ u32 i;
+
+ ldb->regmap = syscon_node_to_regmap(np->parent);
+ if (IS_ERR(ldb->regmap)) {
+ ret = PTR_ERR(ldb->regmap);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ for_each_available_child_of_node(np, child) {
+ struct ldb_channel *ldb_ch;
+
+ ret = of_property_read_u32(child, "reg", &i);
+ if (ret || i > MAX_LDB_CHAN_NUM - 1) {
+ ret = -EINVAL;
+ DRM_DEV_ERROR(dev,
+ "invalid channel node address: %u\n", i);
+ of_node_put(child);
+ return ret;
+ }
+
+ ldb_ch = ldb->channel[i];
+ ldb_ch->ldb = ldb;
+ ldb_ch->chno = i;
+ ldb_ch->is_available = true;
+ ldb_ch->np = child;
+
+ ldb->available_ch_cnt++;
+ }
+
+ return 0;
+}
+
+int ldb_find_next_bridge_helper(struct ldb *ldb)
+{
+ struct device *dev = ldb->dev;
+ struct ldb_channel *ldb_ch;
+ int ret, i;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ ldb_ch = ldb->channel[i];
+
+ if (!ldb_ch->is_available)
+ continue;
+
+ ret = drm_of_find_panel_or_bridge(ldb_ch->np, 1, 0,
+ &ldb_ch->panel,
+ &ldb_ch->next_bridge);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to find panel or bridge: %d\n",
+ ret);
+ return ret;
+ }
+
+ if (ldb_ch->panel) {
+ ldb_ch->next_bridge = devm_drm_panel_bridge_add(dev,
+ ldb_ch->panel);
+ if (IS_ERR(ldb_ch->next_bridge)) {
+ ret = PTR_ERR(ldb_ch->next_bridge);
+ DRM_DEV_ERROR(dev,
+ "failed to add panel bridge: %d\n",
+ ret);
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+void ldb_add_bridge_helper(struct ldb *ldb,
+ const struct drm_bridge_funcs *bridge_funcs)
+{
+ struct ldb_channel *ldb_ch;
+ int i;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ ldb_ch = ldb->channel[i];
+
+ if (!ldb_ch->is_available)
+ continue;
+
+ ldb_ch->bridge.driver_private = ldb_ch;
+ ldb_ch->bridge.funcs = bridge_funcs;
+ ldb_ch->bridge.of_node = ldb_ch->np;
+
+ drm_bridge_add(&ldb_ch->bridge);
+ }
+}
+
+void ldb_remove_bridge_helper(struct ldb *ldb)
+{
+ struct ldb_channel *ldb_ch;
+ int i;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ ldb_ch = ldb->channel[i];
+
+ if (!ldb_ch->is_available)
+ continue;
+
+ drm_bridge_remove(&ldb_ch->bridge);
+ }
+}
diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h
new file mode 100644
index 00000000..748c378
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Copyright 2019,2020 NXP
+ */
+
+#ifndef __IMX_LDB_HELPER__
+#define __IMX_LDB_HELPER__
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_device.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_modeset_helper_vtables.h>
+#include <drm/drm_panel.h>
+
+#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
+#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
+#define LDB_CH0_MODE_EN_MASK (3 << 0)
+#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
+#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
+#define LDB_CH1_MODE_EN_MASK (3 << 2)
+#define LDB_SPLIT_MODE_EN (1 << 4)
+#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
+#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
+#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
+#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
+#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
+#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
+
+#define MAX_LDB_CHAN_NUM 2
+
+enum ldb_channel_link_type {
+ LDB_CH_SINGLE_LINK,
+ LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS,
+ LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS,
+};
+
+struct ldb;
+
+struct ldb_channel {
+ struct ldb *ldb;
+ struct drm_bridge bridge;
+ struct drm_panel *panel;
+ struct drm_bridge *next_bridge;
+ struct device_node *np;
+ u32 chno;
+ bool is_available;
+ u32 in_bus_format;
+ u32 out_bus_format;
+ enum ldb_channel_link_type link_type;
+};
+
+struct ldb {
+ struct regmap *regmap;
+ struct device *dev;
+ struct ldb_channel *channel[MAX_LDB_CHAN_NUM];
+ unsigned int ctrl_reg;
+ u32 ldb_ctrl;
+ unsigned int available_ch_cnt;
+};
+
+#define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge)
+
+bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch);
+bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch);
+
+int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state);
+
+void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode);
+
+void ldb_bridge_enable_helper(struct drm_bridge *bridge);
+
+void ldb_bridge_disable_helper(struct drm_bridge *bridge);
+
+int ldb_bridge_attach_helper(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags);
+
+int ldb_init_helper(struct ldb *ldb);
+
+int ldb_find_next_bridge_helper(struct ldb *ldb);
+
+void ldb_add_bridge_helper(struct ldb *ldb,
+ const struct drm_bridge_funcs *bridge_funcs);
+
+void ldb_remove_bridge_helper(struct ldb *ldb);
+
+#endif /* __IMX_LDB_HELPER__ */
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 11/14] dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (9 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 10/14] drm/bridge: imx: Add LDB driver helper support Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 9:55 ` [PATCH v5 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp Liu Ying
` (2 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* No change.
v3->v4:
* Add Rob's R-b tag.
v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module controls LDB.
v1->v2:
* Use graph schema. (Laurent)
* Side note i.MX8qxp LDB official name 'pixel mapper'. (Laurent)
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 173 +++++++++++++++++++++
1 file changed, 173 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
new file mode 100644
index 00000000..9454300
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
+
+ The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
+ The CSR module, as a system controller, contains the LDB's configuration
+ registers.
+
+ For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
+ format and can map the input to VESA or JEIDA standards. The two channels
+ cannot be used simultaneously, that is to say, the user should pick one of
+ them to use. Two LDB channels from two LDB instances can work together in
+ LDB split mode to support a dual link LVDS display. The channel indexes
+ have to be different. Channel0 outputs odd pixels and channel1 outputs
+ even pixels.
+
+ For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
+ input color format. The two channels can be used simultaneously, either
+ in dual mode or split mode. In dual mode, the two channels output identical
+ data. In split mode, channel0 outputs odd pixels and channel1 outputs even
+ pixels.
+
+ A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
+ the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in
+ i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming
+ consistency, this binding calls it LDB.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-ldb
+ - fsl,imx8qxp-ldb
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: pixel clock
+ - description: bypass clock
+
+ clock-names:
+ items:
+ - const: pixel
+ - const: bypass
+
+ power-domains:
+ maxItems: 1
+
+ fsl,companion-ldb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ A phandle which points to companion LDB which is used in LDB split mode.
+
+patternProperties:
+ "^channel@[0-1]$":
+ type: object
+ description: Represents a channel of LDB.
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ description: The channel index.
+ enum: [ 0, 1 ]
+
+ phys:
+ description: A phandle to the phy module representing the LVDS PHY.
+ maxItems: 1
+
+ phy-names:
+ const: lvds_phy
+
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input port of the channel.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output port of the channel.
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - phys
+ - phy-names
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - power-domains
+ - channel@0
+ - channel@1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qm-ldb
+ then:
+ properties:
+ fsl,companion-ldb: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ ldb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+ };
+ };
+ };
+
+ channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+ };
+ };
+ };
+ };
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (10 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 11/14] dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 12:16 ` kernel test robot
2021-03-10 19:38 ` kernel test robot
2021-03-10 9:55 ` [PATCH v5 13/14] drm/bridge: imx: Add LDB support for i.MX8qm Liu Ying
2021-03-10 9:55 ` [PATCH v5 14/14] MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs Liu Ying
13 siblings, 2 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB)
which is officially named as pixel mapper. The LDB has two channels.
Each of them supports up to 24bpp parallel input color format and can map
the input to VESA or JEIDA standards. The two channels cannot be used
simultaneously, that is to say, the user should pick one of them to use.
Two LDB channels from two LDB instances can work together in LDB split
mode to support a dual link LVDS display. The channel indexes have to be
different. Channel0 outputs odd pixels and channel1 outputs even pixels.
This patch supports the LDB single mode and split mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
Note that this patch depends on the patch 'phy: Add LVDS configuration options',
which has already been sent with the following series to add Mixel combo PHY
found in i.MX8qxp:
https://www.spinics.net/lists/arm-kernel/msg879957.html
v4->v5:
* Link with the imx-ldb-helper object. (Robert)
* Correspondingly, rename 'imx8qxp-ldb.c' to 'imx8qxp-ldb-drv.c'.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* Drop unnecessary DT validation.
* Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to
get the input remote endpoint in imx8qxp_ldb_set_di_id().
* Avoid using companion_port OF node after putting it in
imx8qxp_ldb_parse_dt_companion().
* Mention i.MX8qxp LDB official name 'pixel mapper' in the bridge driver
and Kconfig help message.
drivers/gpu/drm/bridge/imx/Kconfig | 9 +
drivers/gpu/drm/bridge/imx/Makefile | 3 +
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c | 720 +++++++++++++++++++++++++++
3 files changed, 732 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index 1ea1ce7..94f8db4d 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -1,3 +1,12 @@
+config DRM_IMX8QXP_LDB
+ tristate "Freescale i.MX8QXP LVDS display bridge"
+ depends on OF
+ depends on COMMON_CLK
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable the internal LVDS Display Bridge(LDB) found in
+ Freescale i.MX8qxp processor. Official name of LDB is pixel mapper.
+
config DRM_IMX8QXP_PIXEL_COMBINER
tristate "Freescale i.MX8QM/QXP pixel combiner"
depends on OF
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index e74dd64..96d5d1e 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,3 +1,6 @@
+imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o
+obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
+
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c
new file mode 100644
index 00000000..d7f59c1
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c
@@ -0,0 +1,720 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/phy/phy.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#include "imx-ldb-helper.h"
+
+#define LDB_CH_SEL (1 << 28)
+
+#define SS_CTRL 0x20
+#define CH_HSYNC_M(id) BIT(0 + ((id) * 2))
+#define CH_VSYNC_M(id) BIT(1 + ((id) * 2))
+#define CH_PHSYNC(id) BIT(0 + ((id) * 2))
+#define CH_PVSYNC(id) BIT(1 + ((id) * 2))
+
+#define DRIVER_NAME "imx8qxp-ldb"
+
+struct imx8qxp_ldb_channel {
+ struct ldb_channel base;
+ struct phy *phy;
+ unsigned int di_id;
+};
+
+struct imx8qxp_ldb {
+ struct ldb base;
+ struct device *dev;
+ struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM];
+ struct clk *clk_pixel;
+ struct clk *clk_bypass;
+ struct drm_bridge *companion;
+ int active_chno;
+};
+
+static inline struct imx8qxp_ldb_channel *
+base_to_imx8qxp_ldb_channel(struct ldb_channel *base)
+{
+ return container_of(base, struct imx8qxp_ldb_channel, base);
+}
+
+static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base)
+{
+ return container_of(base, struct imx8qxp_ldb, base);
+}
+
+static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb,
+ unsigned long di_clk, bool is_split,
+ struct phy_configure_opts_lvds *phy_cfg)
+{
+ phy_cfg->bits_per_lane_and_dclk_cycle = 7;
+ phy_cfg->lanes = 4;
+
+ if (is_split) {
+ phy_cfg->differential_clk_rate = di_clk / 2;
+ phy_cfg->is_slave = !imx8qxp_ldb->companion;
+ } else {
+ phy_cfg->differential_clk_rate = di_clk;
+ phy_cfg->is_slave = false;
+ }
+}
+
+static int imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
+ base_to_imx8qxp_ldb_channel(ldb_ch);
+ struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
+ struct drm_bridge *companion = imx8qxp_ldb->companion;
+ struct drm_display_mode *adj = &crtc_state->adjusted_mode;
+ unsigned long di_clk = adj->clock * 1000;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ union phy_configure_opts opts = { };
+ struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
+ int ret;
+
+ ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
+ crtc_state, conn_state);
+ if (ret)
+ return ret;
+
+ imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
+ ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
+ if (ret < 0) {
+ DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev,
+ "failed to validate PHY: %d\n", ret);
+ return ret;
+ }
+
+ if (is_split && companion) {
+ ret = companion->funcs->atomic_check(companion,
+ bridge_state, crtc_state, conn_state);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static void
+imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb_channel *companion_ldb_ch;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
+ base_to_imx8qxp_ldb_channel(ldb_ch);
+ struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
+ struct drm_bridge *companion = imx8qxp_ldb->companion;
+ struct device *dev = imx8qxp_ldb->dev;
+ unsigned long di_clk = adjusted_mode->clock * 1000;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ union phy_configure_opts opts = { };
+ struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
+ u32 chno = ldb_ch->chno;
+ int ret;
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret);
+
+ ret = phy_init(imx8qxp_ldb_ch->phy);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret);
+
+ ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret);
+
+ if (is_split && companion) {
+ companion_ldb_ch = bridge_to_ldb_ch(companion);
+
+ companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format;
+ companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format;
+ }
+
+ clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk);
+ clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk);
+
+ imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
+ ret = phy_configure(imx8qxp_ldb_ch->phy, &opts);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret);
+
+ if (chno == 0)
+ ldb->ldb_ctrl &= ~LDB_CH_SEL;
+ else
+ ldb->ldb_ctrl |= LDB_CH_SEL;
+
+ /* input VSYNC signal from pixel link is active low */
+ if (imx8qxp_ldb_ch->di_id == 0)
+ ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
+ else
+ ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
+
+ /*
+ * For split mode, settle input VSYNC signal polarity and
+ * channel selection down early.
+ */
+ if (is_split)
+ regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
+
+ ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode);
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0);
+ else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL,
+ CH_VSYNC_M(chno), CH_PVSYNC(chno));
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0);
+ else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL,
+ CH_HSYNC_M(chno), CH_PHSYNC(chno));
+
+ if (is_split && companion)
+ companion->funcs->mode_set(companion, mode, adjusted_mode);
+}
+
+static void
+imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
+ struct drm_bridge *companion = imx8qxp_ldb->companion;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+
+ clk_prepare_enable(imx8qxp_ldb->clk_pixel);
+ clk_prepare_enable(imx8qxp_ldb->clk_bypass);
+
+ if (is_split && companion)
+ companion->funcs->atomic_pre_enable(companion, old_bridge_state);
+}
+
+static void
+imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
+ base_to_imx8qxp_ldb_channel(ldb_ch);
+ struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
+ struct drm_bridge *companion = imx8qxp_ldb->companion;
+ struct device *dev = imx8qxp_ldb->dev;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ int ret;
+
+ if (ldb_ch->chno == 0 || is_split) {
+ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+ ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?
+ LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1;
+ }
+ if (ldb_ch->chno == 1 || is_split) {
+ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+ ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?
+ LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1;
+ }
+
+ ldb_bridge_enable_helper(bridge);
+
+ ret = phy_power_on(imx8qxp_ldb_ch->phy);
+ if (ret)
+ DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret);
+
+ if (is_split && companion)
+ companion->funcs->atomic_enable(companion, old_bridge_state);
+}
+
+static void
+imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
+ base_to_imx8qxp_ldb_channel(ldb_ch);
+ struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
+ struct drm_bridge *companion = imx8qxp_ldb->companion;
+ struct device *dev = imx8qxp_ldb->dev;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ int ret;
+
+ ret = phy_power_off(imx8qxp_ldb_ch->phy);
+ if (ret)
+ DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret);
+
+ ret = phy_exit(imx8qxp_ldb_ch->phy);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret);
+
+ ldb_bridge_disable_helper(bridge);
+
+ clk_disable_unprepare(imx8qxp_ldb->clk_bypass);
+ clk_disable_unprepare(imx8qxp_ldb->clk_pixel);
+
+ if (is_split && companion)
+ companion->funcs->atomic_disable(companion, old_bridge_state);
+
+ ret = pm_runtime_put(dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret);
+}
+
+static const u32 imx8qxp_ldb_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
+ MEDIA_BUS_FMT_FIXED,
+};
+
+static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) {
+ if (imx8qxp_ldb_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ struct drm_display_info *di;
+ const struct drm_format_info *finfo;
+ u32 *input_fmts;
+
+ if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_FIXED:
+ di = &conn_state->connector->display_info;
+
+ /*
+ * Look at the first bus format to determine input format.
+ * Default to MEDIA_BUS_FMT_RGB888_1X24, if no match.
+ */
+ if (di->num_bus_formats) {
+ finfo = drm_format_info(di->bus_formats[0]);
+
+ input_fmts[0] = finfo->depth == 18 ?
+ MEDIA_BUS_FMT_RGB666_1X24_CPADHI :
+ MEDIA_BUS_FMT_RGB888_1X24;
+ } else {
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
+ }
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
+ break;
+ default:
+ kfree(input_fmts);
+ input_fmts = NULL;
+ break;
+ }
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts);
+ return kmemdup(imx8qxp_ldb_bus_output_fmts,
+ sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL);
+}
+
+static enum drm_mode_status
+imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ bool is_single = ldb_channel_is_single_link(ldb_ch);
+
+ if (mode->clock > 170000)
+ return MODE_CLOCK_HIGH;
+
+ if (mode->clock > 150000 && is_single)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .mode_valid = imx8qxp_ldb_bridge_mode_valid,
+ .attach = ldb_bridge_attach_helper,
+ .atomic_check = imx8qxp_ldb_bridge_atomic_check,
+ .mode_set = imx8qxp_ldb_bridge_mode_set,
+ .atomic_pre_enable = imx8qxp_ldb_bridge_atomic_pre_enable,
+ .atomic_enable = imx8qxp_ldb_bridge_atomic_enable,
+ .atomic_disable = imx8qxp_ldb_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qxp_ldb_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qxp_ldb_bridge_atomic_get_output_bus_fmts,
+};
+
+static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb)
+{
+ struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
+ &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];
+ struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
+ struct device_node *ep, *remote;
+ struct device *dev = imx8qxp_ldb->dev;
+ struct of_endpoint endpoint;
+ int ret;
+
+ ep = of_graph_get_endpoint_by_regs(ldb_ch->np, 0, -1);
+ if (!ep) {
+ DRM_DEV_ERROR(dev, "failed to get port0 endpoint\n");
+ return -EINVAL;
+ }
+
+ remote = of_graph_get_remote_endpoint(ep);
+ of_node_put(ep);
+ if (!remote) {
+ DRM_DEV_ERROR(dev, "failed to get port0 remote endpoint\n");
+ return -EINVAL;
+ }
+
+ ret = of_graph_parse_endpoint(remote, &endpoint);
+ of_node_put(remote);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to parse port0 remote endpoint: %d\n",
+ ret);
+ return ret;
+ }
+
+ imx8qxp_ldb_ch->di_id = endpoint.id;
+
+ return 0;
+}
+
+static int
+imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link)
+{
+ if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) ||
+ (link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb)
+{
+ struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
+ &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];
+ struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
+ struct ldb_channel *companion_ldb_ch;
+ struct device_node *companion;
+ struct device_node *child;
+ struct device_node *companion_port = NULL;
+ struct device_node *port1, *port2;
+ struct device *dev = imx8qxp_ldb->dev;
+ const struct of_device_id *match;
+ u32 i;
+ int dual_link;
+ int ret;
+
+ /* Locate the companion LDB for dual-link operation, if any. */
+ companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0);
+ if (!companion)
+ return 0;
+
+ if (!of_device_is_available(companion)) {
+ DRM_DEV_ERROR(dev, "companion LDB is not available\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ /*
+ * Sanity check: the companion bridge must have the same compatible
+ * string.
+ */
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!of_device_is_compatible(companion, match->compatible)) {
+ DRM_DEV_ERROR(dev, "companion LDB is incompatible\n");
+ ret = -ENXIO;
+ goto out;
+ }
+
+ for_each_available_child_of_node(companion, child) {
+ ret = of_property_read_u32(child, "reg", &i);
+ if (ret || i > MAX_LDB_CHAN_NUM - 1) {
+ DRM_DEV_ERROR(dev,
+ "invalid channel node address: %u\n", i);
+ ret = -EINVAL;
+ of_node_put(child);
+ goto out;
+ }
+
+ /*
+ * Channel numbers have to be different, because channel0
+ * transmits odd pixels and channel1 transmits even pixels.
+ */
+ if (i == (ldb_ch->chno ^ 0x1)) {
+ companion_port = child;
+ break;
+ }
+ }
+
+ if (companion_port == NULL) {
+ DRM_DEV_ERROR(dev,
+ "failed to find companion LDB channel port\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /*
+ * We need to work out if the sink is expecting us to function in
+ * dual-link mode. We do this by looking at the DT port nodes we are
+ * connected to. If they are marked as expecting odd pixels and
+ * even pixels than we need to enable LDB split mode.
+ */
+ port1 = of_graph_get_port_by_id(ldb_ch->np, 1);
+ port2 = of_graph_get_port_by_id(companion_port, 1);
+ dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
+ of_node_put(port1);
+ of_node_put(port2);
+
+ switch (dual_link) {
+ case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
+ ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
+ break;
+ case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
+ ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS;
+ break;
+ default:
+ ret = dual_link;
+ DRM_DEV_ERROR(dev,
+ "failed to get dual link pixel order: %d\n", ret);
+ goto out;
+ }
+
+ ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dev,
+ "unmatched channel number(%u) vs dual link(%d)\n",
+ ldb_ch->chno, dual_link);
+ goto out;
+ }
+
+ imx8qxp_ldb->companion = of_drm_find_bridge(companion_port);
+ if (!imx8qxp_ldb->companion) {
+ ret = -EPROBE_DEFER;
+ DRM_DEV_DEBUG_DRIVER(dev,
+ "failed to find bridge for companion bridge: %d\n", ret);
+ goto out;
+ }
+
+ DRM_DEV_DEBUG_DRIVER(dev,
+ "dual-link configuration detected (companion bridge %pOF)\n",
+ companion);
+
+ companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion);
+ companion_ldb_ch->link_type = ldb_ch->link_type;
+out:
+ of_node_put(companion_port);
+ of_node_put(companion);
+ return ret;
+}
+
+static int imx8qxp_ldb_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct imx8qxp_ldb *imx8qxp_ldb;
+ struct imx8qxp_ldb_channel *imx8qxp_ldb_ch;
+ struct ldb *ldb;
+ struct ldb_channel *ldb_ch;
+ int ret, i;
+
+ imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL);
+ if (!imx8qxp_ldb)
+ return -ENOMEM;
+
+ imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel");
+ if (IS_ERR(imx8qxp_ldb->clk_pixel)) {
+ ret = PTR_ERR(imx8qxp_ldb->clk_pixel);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get pixel clock: %d\n", ret);
+ return ret;
+ }
+
+ imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass");
+ if (IS_ERR(imx8qxp_ldb->clk_bypass)) {
+ ret = PTR_ERR(imx8qxp_ldb->clk_bypass);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get bypass clock: %d\n", ret);
+ return ret;
+ }
+
+ imx8qxp_ldb->dev = dev;
+
+ ldb = &imx8qxp_ldb->base;
+ ldb->dev = dev;
+ ldb->ctrl_reg = 0xe0;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++)
+ ldb->channel[i] = &imx8qxp_ldb->channel[i].base;
+
+ ret = ldb_init_helper(ldb);
+ if (ret)
+ return ret;
+
+ if (ldb->available_ch_cnt == 0) {
+ DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n");
+ return 0;
+ } else if (ldb->available_ch_cnt > 1) {
+ DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n",
+ ldb->available_ch_cnt);
+ return -ENOTSUPP;
+ }
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ imx8qxp_ldb_ch = &imx8qxp_ldb->channel[i];
+ ldb_ch = &imx8qxp_ldb_ch->base;
+
+ if (ldb_ch->is_available) {
+ imx8qxp_ldb->active_chno = ldb_ch->chno;
+ break;
+ }
+ }
+
+ imx8qxp_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, "lvds_phy");
+ if (IS_ERR(imx8qxp_ldb_ch->phy)) {
+ ret = PTR_ERR(imx8qxp_ldb_ch->phy);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get channel%d PHY: %d\n",
+ imx8qxp_ldb->active_chno, ret);
+ return ret;
+ }
+
+ ret = ldb_find_next_bridge_helper(ldb);
+ if (ret)
+ return ret;
+
+ ret = imx8qxp_ldb_set_di_id(imx8qxp_ldb);
+ if (ret)
+ return ret;
+
+ ret = imx8qxp_ldb_parse_dt_companion(imx8qxp_ldb);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, imx8qxp_ldb);
+ pm_runtime_enable(dev);
+
+ ldb_add_bridge_helper(ldb, &imx8qxp_ldb_bridge_funcs);
+
+ return ret;
+}
+
+static int imx8qxp_ldb_remove(struct platform_device *pdev)
+{
+ struct imx8qxp_ldb *imx8qxp_ldb = platform_get_drvdata(pdev);
+ struct ldb *ldb = &imx8qxp_ldb->base;
+
+ ldb_remove_bridge_helper(ldb);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static int __maybe_unused imx8qxp_ldb_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int __maybe_unused imx8qxp_ldb_runtime_resume(struct device *dev)
+{
+ struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev);
+ struct ldb *ldb = &imx8qxp_ldb->base;
+
+ /* disable LDB by resetting the control register to POR default */
+ regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
+
+ return 0;
+}
+
+static const struct dev_pm_ops imx8qxp_ldb_pm_ops = {
+ SET_RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend,
+ imx8qxp_ldb_runtime_resume, NULL)
+};
+
+static const struct of_device_id imx8qxp_ldb_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-ldb" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qxp_ldb_dt_ids);
+
+static struct platform_driver imx8qxp_ldb_driver = {
+ .probe = imx8qxp_ldb_probe,
+ .remove = imx8qxp_ldb_remove,
+ .driver = {
+ .pm = &imx8qxp_ldb_pm_ops,
+ .name = DRIVER_NAME,
+ .of_match_table = imx8qxp_ldb_dt_ids,
+ },
+};
+module_platform_driver(imx8qxp_ldb_driver);
+
+MODULE_DESCRIPTION("i.MX8QXP LVDS Display Bridge(LDB)/Pixel Mapper bridge driver");
+MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.7.4
_______________________________________________
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dri-devel@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 13/14] drm/bridge: imx: Add LDB support for i.MX8qm
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (11 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
2021-03-10 13:25 ` kernel test robot
2021-03-10 9:55 ` [PATCH v5 14/14] MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs Liu Ying
13 siblings, 1 reply; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB)
which is officially named as pixel mapper. The LDB has two channels.
Each of them supports up to 30bpp parallel input color format and can
map the input to VESA or JEIDA standards. The two channels can be used
simultaneously, either in dual mode or split mode. In dual mode, the
two channels output identical data. In split mode, channel0 outputs
odd pixels and channel1 outputs even pixels. This patch supports the
LDB single mode and split mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
Note that this patch depends on the patch 'phy: Add LVDS configuration options',
which has already been sent with the following series to add Mixel combo PHY
found in i.MX8qxp:
https://www.spinics.net/lists/arm-kernel/msg879957.html
v4->v5:
* Link with the imx-ldb-helper object. (Robert)
* Correspondingly, rename 'imx8qm-ldb.c' to 'imx8qm-ldb-drv.c'.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* Drop unnecessary check for maximum available LDB channels.
* Mention i.MX8qm LDB official name 'pixel mapper' in the bridge driver
and Kconfig help message.
drivers/gpu/drm/bridge/imx/Kconfig | 9 +
drivers/gpu/drm/bridge/imx/Makefile | 3 +
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c | 586 ++++++++++++++++++++++++++++
3 files changed, 598 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index 94f8db4d..3a8683f 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -1,3 +1,12 @@
+config DRM_IMX8QM_LDB
+ tristate "Freescale i.MX8QM LVDS display bridge"
+ depends on OF
+ depends on COMMON_CLK
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable the internal LVDS Display Bridge(LDB) found in
+ Freescale i.MX8qm processor. Official name of LDB is pixel mapper.
+
config DRM_IMX8QXP_LDB
tristate "Freescale i.MX8QXP LVDS display bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index 96d5d1e..aa90ec8 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,3 +1,6 @@
+imx8qm-ldb-objs := imx-ldb-helper.o imx8qm-ldb-drv.o
+obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
+
imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o
obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
new file mode 100644
index 00000000..6c92636
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
@@ -0,0 +1,586 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/phy/phy.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#include "imx-ldb-helper.h"
+
+#define LDB_CH0_10BIT_EN (1 << 22)
+#define LDB_CH1_10BIT_EN (1 << 23)
+#define LDB_CH0_DATA_WIDTH_24BIT (1 << 24)
+#define LDB_CH1_DATA_WIDTH_24BIT (1 << 26)
+#define LDB_CH0_DATA_WIDTH_30BIT (2 << 24)
+#define LDB_CH1_DATA_WIDTH_30BIT (2 << 26)
+
+#define SS_CTRL 0x20
+#define CH_HSYNC_M(id) BIT(0 + ((id) * 2))
+#define CH_VSYNC_M(id) BIT(1 + ((id) * 2))
+#define CH_PHSYNC(id) BIT(0 + ((id) * 2))
+#define CH_PVSYNC(id) BIT(1 + ((id) * 2))
+
+#define DRIVER_NAME "imx8qm-ldb"
+
+struct imx8qm_ldb_channel {
+ struct ldb_channel base;
+ struct phy *phy;
+};
+
+struct imx8qm_ldb {
+ struct ldb base;
+ struct device *dev;
+ struct imx8qm_ldb_channel channel[MAX_LDB_CHAN_NUM];
+ struct clk *clk_pixel;
+ struct clk *clk_bypass;
+ int active_chno;
+};
+
+static inline struct imx8qm_ldb_channel *
+base_to_imx8qm_ldb_channel(struct ldb_channel *base)
+{
+ return container_of(base, struct imx8qm_ldb_channel, base);
+}
+
+static inline struct imx8qm_ldb *base_to_imx8qm_ldb(struct ldb *base)
+{
+ return container_of(base, struct imx8qm_ldb, base);
+}
+
+static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb,
+ unsigned long di_clk,
+ bool is_split, bool is_slave,
+ struct phy_configure_opts_lvds *phy_cfg)
+{
+ phy_cfg->bits_per_lane_and_dclk_cycle = 7;
+ phy_cfg->lanes = 4;
+ phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk;
+ phy_cfg->is_slave = is_slave;
+}
+
+static int imx8qm_ldb_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct drm_display_mode *adj = &crtc_state->adjusted_mode;
+ unsigned long di_clk = adj->clock * 1000;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ union phy_configure_opts opts = { };
+ struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
+ int ret;
+
+ ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
+ crtc_state, conn_state);
+ if (ret)
+ return ret;
+
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
+ ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
+ if (ret < 0) {
+ DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev,
+ "failed to validate PHY: %d\n", ret);
+ return ret;
+ }
+
+ if (is_split) {
+ imx8qm_ldb_ch =
+ &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1];
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true,
+ phy_cfg);
+ ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
+ if (ret < 0) {
+ DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev,
+ "failed to validate slave PHY: %d\n", ret);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static void
+imx8qm_ldb_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct device *dev = imx8qm_ldb->dev;
+ unsigned long di_clk = adjusted_mode->clock * 1000;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ union phy_configure_opts opts = { };
+ struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
+ u32 chno = ldb_ch->chno;
+ int ret;
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret);
+
+ ret = phy_init(imx8qm_ldb_ch->phy);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret);
+
+ clk_set_rate(imx8qm_ldb->clk_bypass, di_clk);
+ clk_set_rate(imx8qm_ldb->clk_pixel, di_clk);
+
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
+ ret = phy_configure(imx8qm_ldb_ch->phy, &opts);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret);
+
+ if (is_split) {
+ imx8qm_ldb_ch =
+ &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1];
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true,
+ phy_cfg);
+ ret = phy_configure(imx8qm_ldb_ch->phy, &opts);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to configure slave PHY: %d\n",
+ ret);
+ }
+
+ /* input VSYNC signal from pixel link is active low */
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
+
+ switch (ldb_ch->out_bus_format) {
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT;
+ break;
+ }
+
+ ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode);
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0);
+ else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL,
+ CH_VSYNC_M(chno), CH_PVSYNC(chno));
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0);
+ else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL,
+ CH_HSYNC_M(chno), CH_PHSYNC(chno));
+}
+
+static void
+imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct device *dev = imx8qm_ldb->dev;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ int ret;
+
+ clk_prepare_enable(imx8qm_ldb->clk_pixel);
+ clk_prepare_enable(imx8qm_ldb->clk_bypass);
+
+ /* both DI0 and DI1 connect with pixel link, so ok to use DI0 only */
+ if (ldb_ch->chno == 0 || is_split) {
+ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+ ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
+ }
+ if (ldb_ch->chno == 1 || is_split) {
+ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+ ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
+ }
+
+ if (is_split) {
+ ret = phy_power_on(imx8qm_ldb->channel[0].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power on channel0 PHY: %d\n",
+ ret);
+
+ ret = phy_power_on(imx8qm_ldb->channel[1].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power on channel1 PHY: %d\n",
+ ret);
+ } else {
+ ret = phy_power_on(imx8qm_ldb_ch->phy);
+ if (ret)
+ DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret);
+ }
+
+ ldb_bridge_enable_helper(bridge);
+}
+
+static void
+imx8qm_ldb_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct device *dev = imx8qm_ldb->dev;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ int ret;
+
+ ldb_bridge_disable_helper(bridge);
+
+ if (is_split) {
+ ret = phy_power_off(imx8qm_ldb->channel[0].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power off channel0 PHY: %d\n",
+ ret);
+ ret = phy_power_off(imx8qm_ldb->channel[1].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power off channel1 PHY: %d\n",
+ ret);
+ } else {
+ ret = phy_power_off(imx8qm_ldb_ch->phy);
+ if (ret)
+ DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret);
+ }
+
+ clk_disable_unprepare(imx8qm_ldb->clk_bypass);
+ clk_disable_unprepare(imx8qm_ldb->clk_pixel);
+
+ ret = pm_runtime_put(dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret);
+}
+
+static const u32 imx8qm_ldb_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
+ MEDIA_BUS_FMT_FIXED,
+};
+
+static bool imx8qm_ldb_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); i++) {
+ if (imx8qm_ldb_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qm_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ struct drm_display_info *di;
+ const struct drm_format_info *finfo;
+ u32 *input_fmts;
+
+ if (!imx8qm_ldb_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_FIXED:
+ di = &conn_state->connector->display_info;
+
+ /*
+ * Look at the first bus format to determine input format.
+ * Default to MEDIA_BUS_FMT_RGB888_1X36_CPADLO, if no match.
+ */
+ if (di->num_bus_formats) {
+ finfo = drm_format_info(di->bus_formats[0]);
+
+ input_fmts[0] = finfo->depth == 18 ?
+ MEDIA_BUS_FMT_RGB666_1X36_CPADLO :
+ MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ } else {
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ }
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ break;
+ default:
+ kfree(input_fmts);
+ input_fmts = NULL;
+ break;
+ }
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qm_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qm_ldb_bus_output_fmts);
+ return kmemdup(imx8qm_ldb_bus_output_fmts,
+ sizeof(imx8qm_ldb_bus_output_fmts), GFP_KERNEL);
+}
+
+static enum drm_mode_status
+imx8qm_ldb_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ bool is_single = ldb_channel_is_single_link(ldb_ch);
+
+ if (mode->clock > 300000)
+ return MODE_CLOCK_HIGH;
+
+ if (mode->clock > 150000 && is_single)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static const struct drm_bridge_funcs imx8qm_ldb_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .mode_valid = imx8qm_ldb_bridge_mode_valid,
+ .attach = ldb_bridge_attach_helper,
+ .atomic_check = imx8qm_ldb_bridge_atomic_check,
+ .mode_set = imx8qm_ldb_bridge_mode_set,
+ .atomic_enable = imx8qm_ldb_bridge_atomic_enable,
+ .atomic_disable = imx8qm_ldb_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qm_ldb_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qm_ldb_bridge_atomic_get_output_bus_fmts,
+};
+
+static int imx8qm_ldb_get_phy(struct imx8qm_ldb *imx8qm_ldb)
+{
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch;
+ struct ldb_channel *ldb_ch;
+ struct device *dev = imx8qm_ldb->dev;
+ int i, ret;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
+ ldb_ch = &imx8qm_ldb_ch->base;
+
+ if (!ldb_ch->is_available)
+ continue;
+
+ imx8qm_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np,
+ "lvds_phy");
+ if (IS_ERR(imx8qm_ldb_ch->phy)) {
+ ret = PTR_ERR(imx8qm_ldb_ch->phy);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get channel%d PHY: %d\n",
+ i, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int imx8qm_ldb_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct imx8qm_ldb *imx8qm_ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch;
+ struct ldb *ldb;
+ struct ldb_channel *ldb_ch;
+ struct device_node *port1, *port2;
+ int pixel_order;
+ int ret, i;
+
+ imx8qm_ldb = devm_kzalloc(dev, sizeof(*imx8qm_ldb), GFP_KERNEL);
+ if (!imx8qm_ldb)
+ return -ENOMEM;
+
+ imx8qm_ldb->clk_pixel = devm_clk_get(dev, "pixel");
+ if (IS_ERR(imx8qm_ldb->clk_pixel)) {
+ ret = PTR_ERR(imx8qm_ldb->clk_pixel);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get pixel clock: %d\n", ret);
+ return ret;
+ }
+
+ imx8qm_ldb->clk_bypass = devm_clk_get(dev, "bypass");
+ if (IS_ERR(imx8qm_ldb->clk_bypass)) {
+ ret = PTR_ERR(imx8qm_ldb->clk_bypass);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get bypass clock: %d\n", ret);
+ return ret;
+ }
+
+ imx8qm_ldb->dev = dev;
+
+ ldb = &imx8qm_ldb->base;
+ ldb->dev = dev;
+ ldb->ctrl_reg = 0xe0;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++)
+ ldb->channel[i] = &imx8qm_ldb->channel[i].base;
+
+ ret = ldb_init_helper(ldb);
+ if (ret)
+ return ret;
+
+ if (ldb->available_ch_cnt == 0) {
+ DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n");
+ return 0;
+ }
+
+ if (ldb->available_ch_cnt == 2) {
+ port1 = of_graph_get_port_by_id(ldb->channel[0]->np, 1);
+ port2 = of_graph_get_port_by_id(ldb->channel[1]->np, 1);
+ pixel_order =
+ drm_of_lvds_get_dual_link_pixel_order(port1, port2);
+ of_node_put(port1);
+ of_node_put(port2);
+
+ if (pixel_order != DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
+ DRM_DEV_ERROR(dev, "invalid dual link pixel order: %d\n",
+ pixel_order);
+ return -EINVAL;
+ }
+
+ imx8qm_ldb->active_chno = 0;
+ imx8qm_ldb_ch = &imx8qm_ldb->channel[0];
+ ldb_ch = &imx8qm_ldb_ch->base;
+ ldb_ch->link_type = pixel_order;
+ } else {
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
+ ldb_ch = &imx8qm_ldb_ch->base;
+
+ if (ldb_ch->is_available) {
+ imx8qm_ldb->active_chno = ldb_ch->chno;
+ break;
+ }
+ }
+ }
+
+ ret = imx8qm_ldb_get_phy(imx8qm_ldb);
+ if (ret)
+ return ret;
+
+ ret = ldb_find_next_bridge_helper(ldb);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, imx8qm_ldb);
+ pm_runtime_enable(dev);
+
+ ldb_add_bridge_helper(ldb, &imx8qm_ldb_bridge_funcs);
+
+ return ret;
+}
+
+static int imx8qm_ldb_remove(struct platform_device *pdev)
+{
+ struct imx8qm_ldb *imx8qm_ldb = platform_get_drvdata(pdev);
+ struct ldb *ldb = &imx8qm_ldb->base;
+
+ ldb_remove_bridge_helper(ldb);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static int __maybe_unused imx8qm_ldb_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int __maybe_unused imx8qm_ldb_runtime_resume(struct device *dev)
+{
+ struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev);
+ struct ldb *ldb = &imx8qm_ldb->base;
+
+ /* disable LDB by resetting the control register to POR default */
+ regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
+
+ return 0;
+}
+
+static const struct dev_pm_ops imx8qm_ldb_pm_ops = {
+ SET_RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend,
+ imx8qm_ldb_runtime_resume, NULL)
+};
+
+static const struct of_device_id imx8qm_ldb_dt_ids[] = {
+ { .compatible = "fsl,imx8qm-ldb" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qm_ldb_dt_ids);
+
+static struct platform_driver imx8qm_ldb_driver = {
+ .probe = imx8qm_ldb_probe,
+ .remove = imx8qm_ldb_remove,
+ .driver = {
+ .pm = &imx8qm_ldb_pm_ops,
+ .name = DRIVER_NAME,
+ .of_match_table = imx8qm_ldb_dt_ids,
+ },
+};
+module_platform_driver(imx8qm_ldb_driver);
+
+MODULE_DESCRIPTION("i.MX8QM LVDS Display Bridge(LDB)/Pixel Mapper bridge driver");
+MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v5 14/14] MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
` (12 preceding siblings ...)
2021-03-10 9:55 ` [PATCH v5 13/14] drm/bridge: imx: Add LDB support for i.MX8qm Liu Ying
@ 2021-03-10 9:55 ` Liu Ying
13 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-10 9:55 UTC (permalink / raw)
To: dri-devel, devicetree, linux-arm-kernel, linux-kernel, linux-media
Cc: jernej.skrabec, narmstrong, airlied, s.hauer, jonas, robert.foss,
kishon, a.hajda, vkoul, robh+dt, linux-imx, kernel, lee.jones,
mchehab, shawnguo, Laurent.pinchart
Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 63bd69c..6e0c019 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5892,6 +5892,16 @@ F: Documentation/devicetree/bindings/display/imx/
F: drivers/gpu/drm/imx/
F: drivers/gpu/ipu-v3/
+DRM DRIVERS FOR FREESCALE IMX BRIDGE
+M: Liu Ying <victor.liu@nxp.com>
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
+F: drivers/gpu/drm/bridge/imx/
+
DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets)
M: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
L: dri-devel@lists.freedesktop.org
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v5 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp
2021-03-10 9:55 ` [PATCH v5 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp Liu Ying
@ 2021-03-10 12:16 ` kernel test robot
2021-03-10 19:38 ` kernel test robot
1 sibling, 0 replies; 24+ messages in thread
From: kernel test robot @ 2021-03-10 12:16 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, linux-arm-kernel, linux-kernel,
linux-media
Cc: jernej.skrabec, kbuild-all, jonas, airlied, s.hauer, narmstrong
[-- Attachment #1: Type: text/plain, Size: 5222 bytes --]
Hi Liu,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on shawnguo/for-next]
[also build test WARNING on robh/for-next drm-intel/for-linux-next drm-tip/drm-tip tegra-drm/drm/tegra/for-next linus/master drm-exynos/exynos-drm-next v5.12-rc2 next-20210310]
[cannot apply to drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Liu-Ying/Add-some-DRM-bridge-drivers-support-for-i-MX8qm-qxp-SoCs/20210310-181047
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: mips-allyesconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/e621f277f533f302da23441f28b3fc02a152a7df
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Liu-Ying/Add-some-DRM-bridge-drivers-support-for-i-MX8qm-qxp-SoCs/20210310-181047
git checkout e621f277f533f302da23441f28b3fc02a152a7df
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:65:16: warning: 'struct phy_configure_opts_lvds' declared inside parameter list will not be visible outside of this definition or declaration
65 | struct phy_configure_opts_lvds *phy_cfg)
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c: In function 'imx8qxp_ldb_set_phy_cfg':
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:67:9: error: dereferencing pointer to incomplete type 'struct phy_configure_opts_lvds'
67 | phy_cfg->bits_per_lane_and_dclk_cycle = 7;
| ^~
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c: In function 'imx8qxp_ldb_bridge_atomic_check':
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:94:49: error: 'union phy_configure_opts' has no member named 'lvds'
94 | struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
| ^
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:102:57: error: passing argument 4 of 'imx8qxp_ldb_set_phy_cfg' from incompatible pointer type [-Werror=incompatible-pointer-types]
102 | imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
| ^~~~~~~
| |
| struct phy_configure_opts_lvds *
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:65:41: note: expected 'struct phy_configure_opts_lvds *' but argument is of type 'struct phy_configure_opts_lvds *'
65 | struct phy_configure_opts_lvds *phy_cfg)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c: In function 'imx8qxp_ldb_bridge_mode_set':
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:136:49: error: 'union phy_configure_opts' has no member named 'lvds'
136 | struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
| ^
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:162:57: error: passing argument 4 of 'imx8qxp_ldb_set_phy_cfg' from incompatible pointer type [-Werror=incompatible-pointer-types]
162 | imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
| ^~~~~~~
| |
| struct phy_configure_opts_lvds *
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:65:41: note: expected 'struct phy_configure_opts_lvds *' but argument is of type 'struct phy_configure_opts_lvds *'
65 | struct phy_configure_opts_lvds *phy_cfg)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
cc1: some warnings being treated as errors
vim +65 drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c
62
63 static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb,
64 unsigned long di_clk, bool is_split,
> 65 struct phy_configure_opts_lvds *phy_cfg)
66 {
67 phy_cfg->bits_per_lane_and_dclk_cycle = 7;
68 phy_cfg->lanes = 4;
69
70 if (is_split) {
71 phy_cfg->differential_clk_rate = di_clk / 2;
72 phy_cfg->is_slave = !imx8qxp_ldb->companion;
73 } else {
74 phy_cfg->differential_clk_rate = di_clk;
75 phy_cfg->is_slave = false;
76 }
77 }
78
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 70158 bytes --]
[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5 02/14] media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
2021-03-10 9:55 ` [PATCH v5 02/14] media: docs: " Liu Ying
@ 2021-03-10 13:24 ` Laurent Pinchart
2021-03-11 5:26 ` Liu Ying
0 siblings, 1 reply; 24+ messages in thread
From: Laurent Pinchart @ 2021-03-10 13:24 UTC (permalink / raw)
To: Liu Ying
Cc: narmstrong, airlied, dri-devel, a.hajda, lee.jones, kishon,
linux-imx, linux-media, devicetree, jonas, s.hauer, robh+dt,
mchehab, linux-arm-kernel, jernej.skrabec, linux-kernel,
robert.foss, vkoul, kernel, shawnguo
Hi Liu,
Thank you for the patch.
On Wed, Mar 10, 2021 at 05:55:26PM +0800, Liu Ying wrote:
> This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO,
> RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp
> pixel combiner. The RGB pixels with padding low per component are
> transmitted on a 30-bit input bus(10-bit per component) from a display
> controller or a 36-bit output bus(12-bit per component) to a pixel link.
>
> Reviewed-by: Robert Foss <robert.foss@linaro.org>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v4->v5:
> * Add Robert's R-b tag.
>
> v3->v4:
> * No change.
>
> v2->v3:
> * No change.
>
> v1->v2:
> * No change.
>
> .../userspace-api/media/v4l/subdev-formats.rst | 156 +++++++++++++++++++++
> 1 file changed, 156 insertions(+)
>
> diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst b/Documentation/userspace-api/media/v4l/subdev-formats.rst
> index 7f16cbe..201c16d 100644
> --- a/Documentation/userspace-api/media/v4l/subdev-formats.rst
> +++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst
> @@ -1488,6 +1488,80 @@ The following tables list existing packed RGB formats.
> - b\ :sub:`2`
> - b\ :sub:`1`
> - b\ :sub:`0`
> + * .. _MEDIA-BUS-FMT-RGB666-1X30-CPADLO:
> +
> + - MEDIA_BUS_FMT_RGB666_1X30-CPADLO
> + - 0x101e
> + -
> + - 0
> + - 0
I count 32 bits here. Should these two 0 be replaced by spaces ? Same
for MEDIA_BUS_FMT_RGB888_1X30-CPADLO.
With this fixed,
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> + - r\ :sub:`5`
> + - r\ :sub:`4`
> + - r\ :sub:`3`
> + - r\ :sub:`2`
> + - r\ :sub:`1`
> + - r\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> + - g\ :sub:`5`
> + - g\ :sub:`4`
> + - g\ :sub:`3`
> + - g\ :sub:`2`
> + - g\ :sub:`1`
> + - g\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> + - b\ :sub:`5`
> + - b\ :sub:`4`
> + - b\ :sub:`3`
> + - b\ :sub:`2`
> + - b\ :sub:`1`
> + - b\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> + * .. _MEDIA-BUS-FMT-RGB888-1X30-CPADLO:
> +
> + - MEDIA_BUS_FMT_RGB888_1X30-CPADLO
> + - 0x101f
> + -
> + - 0
> + - 0
> + - r\ :sub:`7`
> + - r\ :sub:`6`
> + - r\ :sub:`5`
> + - r\ :sub:`4`
> + - r\ :sub:`3`
> + - r\ :sub:`2`
> + - r\ :sub:`1`
> + - r\ :sub:`0`
> + - 0
> + - 0
> + - g\ :sub:`7`
> + - g\ :sub:`6`
> + - g\ :sub:`5`
> + - g\ :sub:`4`
> + - g\ :sub:`3`
> + - g\ :sub:`2`
> + - g\ :sub:`1`
> + - g\ :sub:`0`
> + - 0
> + - 0
> + - b\ :sub:`7`
> + - b\ :sub:`6`
> + - b\ :sub:`5`
> + - b\ :sub:`4`
> + - b\ :sub:`3`
> + - b\ :sub:`2`
> + - b\ :sub:`1`
> + - b\ :sub:`0`
> + - 0
> + - 0
> * .. _MEDIA-BUS-FMT-ARGB888-1X32:
>
> - MEDIA_BUS_FMT_ARGB888_1X32
> @@ -1665,6 +1739,88 @@ The following table list existing packed 36bit wide RGB formats.
> - 2
> - 1
> - 0
> + * .. _MEDIA-BUS-FMT-RGB666-1X36-CPADLO:
> +
> + - MEDIA_BUS_FMT_RGB666_1X36_CPADLO
> + - 0x1020
> + -
> + - r\ :sub:`5`
> + - r\ :sub:`4`
> + - r\ :sub:`3`
> + - r\ :sub:`2`
> + - r\ :sub:`1`
> + - r\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> + - 0
> + - 0
> + - g\ :sub:`5`
> + - g\ :sub:`4`
> + - g\ :sub:`3`
> + - g\ :sub:`2`
> + - g\ :sub:`1`
> + - g\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> + - 0
> + - 0
> + - b\ :sub:`5`
> + - b\ :sub:`4`
> + - b\ :sub:`3`
> + - b\ :sub:`2`
> + - b\ :sub:`1`
> + - b\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> + - 0
> + - 0
> + * .. _MEDIA-BUS-FMT-RGB888-1X36-CPADLO:
> +
> + - MEDIA_BUS_FMT_RGB888_1X36_CPADLO
> + - 0x1021
> + -
> + - r\ :sub:`7`
> + - r\ :sub:`6`
> + - r\ :sub:`5`
> + - r\ :sub:`4`
> + - r\ :sub:`3`
> + - r\ :sub:`2`
> + - r\ :sub:`1`
> + - r\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> + - g\ :sub:`7`
> + - g\ :sub:`6`
> + - g\ :sub:`5`
> + - g\ :sub:`4`
> + - g\ :sub:`3`
> + - g\ :sub:`2`
> + - g\ :sub:`1`
> + - g\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> + - b\ :sub:`7`
> + - b\ :sub:`6`
> + - b\ :sub:`5`
> + - b\ :sub:`4`
> + - b\ :sub:`3`
> + - b\ :sub:`2`
> + - b\ :sub:`1`
> + - b\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> * .. _MEDIA-BUS-FMT-RGB121212-1X36:
>
> - MEDIA_BUS_FMT_RGB121212_1X36
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5 13/14] drm/bridge: imx: Add LDB support for i.MX8qm
2021-03-10 9:55 ` [PATCH v5 13/14] drm/bridge: imx: Add LDB support for i.MX8qm Liu Ying
@ 2021-03-10 13:25 ` kernel test robot
0 siblings, 0 replies; 24+ messages in thread
From: kernel test robot @ 2021-03-10 13:25 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, linux-arm-kernel, linux-kernel,
linux-media
Cc: jernej.skrabec, kbuild-all, jonas, airlied, s.hauer, narmstrong
[-- Attachment #1: Type: text/plain, Size: 6300 bytes --]
Hi Liu,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on shawnguo/for-next]
[also build test WARNING on robh/for-next drm-intel/for-linux-next drm-tip/drm-tip tegra-drm/drm/tegra/for-next linus/master drm-exynos/exynos-drm-next v5.12-rc2 next-20210310]
[cannot apply to drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Liu-Ying/Add-some-DRM-bridge-drivers-support-for-i-MX8qm-qxp-SoCs/20210310-181047
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: mips-allyesconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/2018fd6af385c7cad1ce9510fca71cc87d6d151b
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Liu-Ying/Add-some-DRM-bridge-drivers-support-for-i-MX8qm-qxp-SoCs/20210310-181047
git checkout 2018fd6af385c7cad1ce9510fca71cc87d6d151b
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:69:15: warning: 'struct phy_configure_opts_lvds' declared inside parameter list will not be visible outside of this definition or declaration
69 | struct phy_configure_opts_lvds *phy_cfg)
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c: In function 'imx8qm_ldb_set_phy_cfg':
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:71:9: error: dereferencing pointer to incomplete type 'struct phy_configure_opts_lvds'
71 | phy_cfg->bits_per_lane_and_dclk_cycle = 7;
| ^~
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c: In function 'imx8qm_ldb_bridge_atomic_check':
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:91:49: error: 'union phy_configure_opts' has no member named 'lvds'
91 | struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
| ^
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:99:62: error: passing argument 5 of 'imx8qm_ldb_set_phy_cfg' from incompatible pointer type [-Werror=incompatible-pointer-types]
99 | imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
| ^~~~~~~
| |
| struct phy_configure_opts_lvds *
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:69:40: note: expected 'struct phy_configure_opts_lvds *' but argument is of type 'struct phy_configure_opts_lvds *'
69 | struct phy_configure_opts_lvds *phy_cfg)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:111:10: error: passing argument 5 of 'imx8qm_ldb_set_phy_cfg' from incompatible pointer type [-Werror=incompatible-pointer-types]
111 | phy_cfg);
| ^~~~~~~
| |
| struct phy_configure_opts_lvds *
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:69:40: note: expected 'struct phy_configure_opts_lvds *' but argument is of type 'struct phy_configure_opts_lvds *'
69 | struct phy_configure_opts_lvds *phy_cfg)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c: In function 'imx8qm_ldb_bridge_mode_set':
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:137:49: error: 'union phy_configure_opts' has no member named 'lvds'
137 | struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
| ^
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:152:62: error: passing argument 5 of 'imx8qm_ldb_set_phy_cfg' from incompatible pointer type [-Werror=incompatible-pointer-types]
152 | imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
| ^~~~~~~
| |
| struct phy_configure_opts_lvds *
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:69:40: note: expected 'struct phy_configure_opts_lvds *' but argument is of type 'struct phy_configure_opts_lvds *'
69 | struct phy_configure_opts_lvds *phy_cfg)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:161:10: error: passing argument 5 of 'imx8qm_ldb_set_phy_cfg' from incompatible pointer type [-Werror=incompatible-pointer-types]
161 | phy_cfg);
| ^~~~~~~
| |
| struct phy_configure_opts_lvds *
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c:69:40: note: expected 'struct phy_configure_opts_lvds *' but argument is of type 'struct phy_configure_opts_lvds *'
69 | struct phy_configure_opts_lvds *phy_cfg)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
cc1: some warnings being treated as errors
vim +69 drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
65
66 static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb,
67 unsigned long di_clk,
68 bool is_split, bool is_slave,
> 69 struct phy_configure_opts_lvds *phy_cfg)
70 {
71 phy_cfg->bits_per_lane_and_dclk_cycle = 7;
72 phy_cfg->lanes = 4;
73 phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk;
74 phy_cfg->is_slave = is_slave;
75 }
76
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 70161 bytes --]
[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5 01/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
2021-03-10 9:55 ` [PATCH v5 01/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner Liu Ying
@ 2021-03-10 13:45 ` Laurent Pinchart
0 siblings, 0 replies; 24+ messages in thread
From: Laurent Pinchart @ 2021-03-10 13:45 UTC (permalink / raw)
To: Liu Ying
Cc: narmstrong, airlied, dri-devel, a.hajda, lee.jones, kishon,
linux-imx, linux-media, devicetree, jonas, s.hauer, robh+dt,
mchehab, linux-arm-kernel, jernej.skrabec, linux-kernel,
robert.foss, vkoul, kernel, shawnguo
Hi Liu,
Thank you for the patch.
On Wed, Mar 10, 2021 at 05:55:25PM +0800, Liu Ying wrote:
> This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
> and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
> The RGB pixels with padding low per component are transmitted on a 30-bit
> input bus(10-bit per component) from a display controller or a 36-bit
> output bus(12-bit per component) to a pixel link.
>
> Reviewed-by: Robert Foss <robert.foss@linaro.org>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> v4->v5:
> * Add Robert's R-b tag.
>
> v3->v4:
> * No change.
>
> v2->v3:
> * No change.
>
> v1->v2:
> * No change.
>
> include/uapi/linux/media-bus-format.h | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h
> index 0dfc11e..ec3323d 100644
> --- a/include/uapi/linux/media-bus-format.h
> +++ b/include/uapi/linux/media-bus-format.h
> @@ -34,7 +34,7 @@
>
> #define MEDIA_BUS_FMT_FIXED 0x0001
>
> -/* RGB - next is 0x101e */
> +/* RGB - next is 0x1022 */
> #define MEDIA_BUS_FMT_RGB444_1X12 0x1016
> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
> @@ -59,9 +59,13 @@
> #define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d
> #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
> #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
> +#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO 0x101e
> +#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO 0x101f
> #define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
> #define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
> #define MEDIA_BUS_FMT_RGB101010_1X30 0x1018
> +#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020
> +#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021
> #define MEDIA_BUS_FMT_RGB121212_1X36 0x1019
> #define MEDIA_BUS_FMT_RGB161616_1X48 0x101a
>
--
Regards,
Laurent Pinchart
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp
2021-03-10 9:55 ` [PATCH v5 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp Liu Ying
2021-03-10 12:16 ` kernel test robot
@ 2021-03-10 19:38 ` kernel test robot
1 sibling, 0 replies; 24+ messages in thread
From: kernel test robot @ 2021-03-10 19:38 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, linux-arm-kernel, linux-kernel,
linux-media
Cc: jernej.skrabec, kbuild-all, jonas, airlied, s.hauer, narmstrong
[-- Attachment #1: Type: text/plain, Size: 6797 bytes --]
Hi Liu,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on shawnguo/for-next]
[also build test ERROR on robh/for-next drm-intel/for-linux-next drm-tip/drm-tip tegra-drm/drm/tegra/for-next linus/master drm-exynos/exynos-drm-next v5.12-rc2 next-20210310]
[cannot apply to drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Liu-Ying/Add-some-DRM-bridge-drivers-support-for-i-MX8qm-qxp-SoCs/20210310-181047
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: mips-allyesconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/e621f277f533f302da23441f28b3fc02a152a7df
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Liu-Ying/Add-some-DRM-bridge-drivers-support-for-i-MX8qm-qxp-SoCs/20210310-181047
git checkout e621f277f533f302da23441f28b3fc02a152a7df
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:65:16: warning: 'struct phy_configure_opts_lvds' declared inside parameter list will not be visible outside of this definition or declaration
65 | struct phy_configure_opts_lvds *phy_cfg)
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c: In function 'imx8qxp_ldb_set_phy_cfg':
>> drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:67:9: error: dereferencing pointer to incomplete type 'struct phy_configure_opts_lvds'
67 | phy_cfg->bits_per_lane_and_dclk_cycle = 7;
| ^~
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c: In function 'imx8qxp_ldb_bridge_atomic_check':
>> drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:94:49: error: 'union phy_configure_opts' has no member named 'lvds'
94 | struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
| ^
>> drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:102:57: error: passing argument 4 of 'imx8qxp_ldb_set_phy_cfg' from incompatible pointer type [-Werror=incompatible-pointer-types]
102 | imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
| ^~~~~~~
| |
| struct phy_configure_opts_lvds *
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:65:41: note: expected 'struct phy_configure_opts_lvds *' but argument is of type 'struct phy_configure_opts_lvds *'
65 | struct phy_configure_opts_lvds *phy_cfg)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c: In function 'imx8qxp_ldb_bridge_mode_set':
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:136:49: error: 'union phy_configure_opts' has no member named 'lvds'
136 | struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
| ^
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:162:57: error: passing argument 4 of 'imx8qxp_ldb_set_phy_cfg' from incompatible pointer type [-Werror=incompatible-pointer-types]
162 | imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
| ^~~~~~~
| |
| struct phy_configure_opts_lvds *
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:65:41: note: expected 'struct phy_configure_opts_lvds *' but argument is of type 'struct phy_configure_opts_lvds *'
65 | struct phy_configure_opts_lvds *phy_cfg)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
cc1: some warnings being treated as errors
vim +67 drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c
62
63 static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb,
64 unsigned long di_clk, bool is_split,
65 struct phy_configure_opts_lvds *phy_cfg)
66 {
> 67 phy_cfg->bits_per_lane_and_dclk_cycle = 7;
68 phy_cfg->lanes = 4;
69
70 if (is_split) {
71 phy_cfg->differential_clk_rate = di_clk / 2;
72 phy_cfg->is_slave = !imx8qxp_ldb->companion;
73 } else {
74 phy_cfg->differential_clk_rate = di_clk;
75 phy_cfg->is_slave = false;
76 }
77 }
78
79 static int imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge,
80 struct drm_bridge_state *bridge_state,
81 struct drm_crtc_state *crtc_state,
82 struct drm_connector_state *conn_state)
83 {
84 struct ldb_channel *ldb_ch = bridge->driver_private;
85 struct ldb *ldb = ldb_ch->ldb;
86 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
87 base_to_imx8qxp_ldb_channel(ldb_ch);
88 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
89 struct drm_bridge *companion = imx8qxp_ldb->companion;
90 struct drm_display_mode *adj = &crtc_state->adjusted_mode;
91 unsigned long di_clk = adj->clock * 1000;
92 bool is_split = ldb_channel_is_split_link(ldb_ch);
93 union phy_configure_opts opts = { };
> 94 struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
95 int ret;
96
97 ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
98 crtc_state, conn_state);
99 if (ret)
100 return ret;
101
> 102 imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
103 ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
104 if (ret < 0) {
105 DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev,
106 "failed to validate PHY: %d\n", ret);
107 return ret;
108 }
109
110 if (is_split && companion) {
111 ret = companion->funcs->atomic_check(companion,
112 bridge_state, crtc_state, conn_state);
113 if (ret)
114 return ret;
115 }
116
117 return ret;
118 }
119
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 70158 bytes --]
[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5 02/14] media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
2021-03-10 13:24 ` Laurent Pinchart
@ 2021-03-11 5:26 ` Liu Ying
0 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-11 5:26 UTC (permalink / raw)
To: Laurent Pinchart
Cc: narmstrong, airlied, dri-devel, a.hajda, lee.jones, kishon,
linux-imx, linux-media, devicetree, jonas, s.hauer, robh+dt,
mchehab, linux-arm-kernel, jernej.skrabec, linux-kernel,
robert.foss, vkoul, kernel, shawnguo
Hi Laurent,
On Wed, 2021-03-10 at 15:24 +0200, Laurent Pinchart wrote:
> Hi Liu,
>
> Thank you for the patch.
Thanks for your review.
>
> On Wed, Mar 10, 2021 at 05:55:26PM +0800, Liu Ying wrote:
> > This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO,
> > RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp
> > pixel combiner. The RGB pixels with padding low per component are
> > transmitted on a 30-bit input bus(10-bit per component) from a display
> > controller or a 36-bit output bus(12-bit per component) to a pixel link.
> >
> > Reviewed-by: Robert Foss <robert.foss@linaro.org>
> > Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > ---
> > v4->v5:
> > * Add Robert's R-b tag.
> >
> > v3->v4:
> > * No change.
> >
> > v2->v3:
> > * No change.
> >
> > v1->v2:
> > * No change.
> >
> > .../userspace-api/media/v4l/subdev-formats.rst | 156 +++++++++++++++++++++
> > 1 file changed, 156 insertions(+)
> >
> > diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst b/Documentation/userspace-api/media/v4l/subdev-formats.rst
> > index 7f16cbe..201c16d 100644
> > --- a/Documentation/userspace-api/media/v4l/subdev-formats.rst
> > +++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst
> > @@ -1488,6 +1488,80 @@ The following tables list existing packed RGB formats.
> > - b\ :sub:`2`
> > - b\ :sub:`1`
> > - b\ :sub:`0`
> > + * .. _MEDIA-BUS-FMT-RGB666-1X30-CPADLO:
> > +
> > + - MEDIA_BUS_FMT_RGB666_1X30-CPADLO
> > + - 0x101e
> > + -
> > + - 0
> > + - 0
>
> I count 32 bits here. Should these two 0 be replaced by spaces ? Same
> for MEDIA_BUS_FMT_RGB888_1X30-CPADLO.
Indeed, these two 0 should be spaces. Will fix them in next version.
I see the in-tree MEDIA_BUS_FMT_RGB101010_1X30 has the same issue.
I can send another patch to fix it.
Regards,
Liu Ying
>
> With this fixed,
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>
> > + - r\ :sub:`5`
> > + - r\ :sub:`4`
> > + - r\ :sub:`3`
> > + - r\ :sub:`2`
> > + - r\ :sub:`1`
> > + - r\ :sub:`0`
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - g\ :sub:`5`
> > + - g\ :sub:`4`
> > + - g\ :sub:`3`
> > + - g\ :sub:`2`
> > + - g\ :sub:`1`
> > + - g\ :sub:`0`
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - b\ :sub:`5`
> > + - b\ :sub:`4`
> > + - b\ :sub:`3`
> > + - b\ :sub:`2`
> > + - b\ :sub:`1`
> > + - b\ :sub:`0`
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + * .. _MEDIA-BUS-FMT-RGB888-1X30-CPADLO:
> > +
> > + - MEDIA_BUS_FMT_RGB888_1X30-CPADLO
> > + - 0x101f
> > + -
> > + - 0
> > + - 0
> > + - r\ :sub:`7`
> > + - r\ :sub:`6`
> > + - r\ :sub:`5`
> > + - r\ :sub:`4`
> > + - r\ :sub:`3`
> > + - r\ :sub:`2`
> > + - r\ :sub:`1`
> > + - r\ :sub:`0`
> > + - 0
> > + - 0
> > + - g\ :sub:`7`
> > + - g\ :sub:`6`
> > + - g\ :sub:`5`
> > + - g\ :sub:`4`
> > + - g\ :sub:`3`
> > + - g\ :sub:`2`
> > + - g\ :sub:`1`
> > + - g\ :sub:`0`
> > + - 0
> > + - 0
> > + - b\ :sub:`7`
> > + - b\ :sub:`6`
> > + - b\ :sub:`5`
> > + - b\ :sub:`4`
> > + - b\ :sub:`3`
> > + - b\ :sub:`2`
> > + - b\ :sub:`1`
> > + - b\ :sub:`0`
> > + - 0
> > + - 0
> > * .. _MEDIA-BUS-FMT-ARGB888-1X32:
> >
> > - MEDIA_BUS_FMT_ARGB888_1X32
> > @@ -1665,6 +1739,88 @@ The following table list existing packed 36bit wide RGB formats.
> > - 2
> > - 1
> > - 0
> > + * .. _MEDIA-BUS-FMT-RGB666-1X36-CPADLO:
> > +
> > + - MEDIA_BUS_FMT_RGB666_1X36_CPADLO
> > + - 0x1020
> > + -
> > + - r\ :sub:`5`
> > + - r\ :sub:`4`
> > + - r\ :sub:`3`
> > + - r\ :sub:`2`
> > + - r\ :sub:`1`
> > + - r\ :sub:`0`
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - g\ :sub:`5`
> > + - g\ :sub:`4`
> > + - g\ :sub:`3`
> > + - g\ :sub:`2`
> > + - g\ :sub:`1`
> > + - g\ :sub:`0`
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - b\ :sub:`5`
> > + - b\ :sub:`4`
> > + - b\ :sub:`3`
> > + - b\ :sub:`2`
> > + - b\ :sub:`1`
> > + - b\ :sub:`0`
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + * .. _MEDIA-BUS-FMT-RGB888-1X36-CPADLO:
> > +
> > + - MEDIA_BUS_FMT_RGB888_1X36_CPADLO
> > + - 0x1021
> > + -
> > + - r\ :sub:`7`
> > + - r\ :sub:`6`
> > + - r\ :sub:`5`
> > + - r\ :sub:`4`
> > + - r\ :sub:`3`
> > + - r\ :sub:`2`
> > + - r\ :sub:`1`
> > + - r\ :sub:`0`
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - g\ :sub:`7`
> > + - g\ :sub:`6`
> > + - g\ :sub:`5`
> > + - g\ :sub:`4`
> > + - g\ :sub:`3`
> > + - g\ :sub:`2`
> > + - g\ :sub:`1`
> > + - g\ :sub:`0`
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > + - b\ :sub:`7`
> > + - b\ :sub:`6`
> > + - b\ :sub:`5`
> > + - b\ :sub:`4`
> > + - b\ :sub:`3`
> > + - b\ :sub:`2`
> > + - b\ :sub:`1`
> > + - b\ :sub:`0`
> > + - 0
> > + - 0
> > + - 0
> > + - 0
> > * .. _MEDIA-BUS-FMT-RGB121212-1X36:
> >
> > - MEDIA_BUS_FMT_RGB121212_1X36
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5 07/14] dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding
2021-03-10 9:55 ` [PATCH v5 07/14] dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding Liu Ying
@ 2021-03-16 22:38 ` Rob Herring
2021-03-17 2:04 ` Liu Ying
0 siblings, 1 reply; 24+ messages in thread
From: Rob Herring @ 2021-03-16 22:38 UTC (permalink / raw)
To: Liu Ying
Cc: narmstrong, airlied, dri-devel, a.hajda, Laurent.pinchart,
lee.jones, kishon, linux-imx, linux-media, devicetree, jonas,
s.hauer, mchehab, linux-arm-kernel, jernej.skrabec, linux-kernel,
robert.foss, vkoul, kernel, shawnguo
On Wed, Mar 10, 2021 at 05:55:31PM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v4->v5:
> * Newly introduced in v5. (Rob)
>
> .../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml | 202 +++++++++++++++++++++
> 1 file changed, 202 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
> new file mode 100644
> index 00000000..0e724d9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
> @@ -0,0 +1,202 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
> +
> +maintainers:
> + - Liu Ying <victor.liu@nxp.com>
> +
> +description: |
> + As a system controller, the Freescale i.MX8qm/qxp Control and Status
> + Registers(CSR) module represents a set of miscellaneous registers of a
> + specific subsystem. It may provide control and/or status report interfaces
> + to a mix of standalone hardware devices within that subsystem. One typical
> + use-case is for some other nodes to acquire a reference to the syscon node
> + by phandle, and the other typical use-case is that the operating system
> + should consider all subnodes of the CSR module as separate child devices.
> +
> +select:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8qxp-mipi-lvds-csr
> + - fsl,imx8qm-lvds-csr
You shouldn't need this, we filter out 'syscon' and 'simple-mfd'.
> + required:
> + - compatible
> +
> +properties:
> + $nodename:
> + pattern: "^syscon@[0-9a-f]+$"
> +
> + compatible:
> + items:
> + - enum:
> + - fsl,imx8qxp-mipi-lvds-csr
> + - fsl,imx8qm-lvds-csr
> + - const: syscon
> + - const: simple-mfd
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: ipg
> +
> +patternProperties:
> + "^(ldb|phy|pxl2dpi)$":
> + type: object
> + description: The possible child devices of the CSR module.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,imx8qxp-mipi-lvds-csr
> + then:
> + required:
> + - pxl2dpi
> + - ldb
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,imx8qm-lvds-csr
> + then:
> + required:
> + - phy
> + - ldb
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8-lpcg.h>
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + mipi_lvds_0_csr: syscon@56221000 {
> + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
> + reg = <0x56221000 0x1000>;
> + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
> + clock-names = "ipg";
> +
> + mipi_lvds_0_pxl2dpi: pxl2dpi {
> + compatible = "fsl,imx8qxp-pxl2dpi";
> + fsl,sc-resource = <IMX_SC_R_MIPI_0>;
> + power-domains = <&pd IMX_SC_R_MIPI_0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
> + };
> +
> + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
> + };
> + };
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
> + };
> +
> + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
> + };
> + };
> + };
> + };
> +
> + mipi_lvds_0_ldb: ldb {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8qxp-ldb";
> + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
> + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
> + clock-names = "pixel", "bypass";
> + power-domains = <&pd IMX_SC_R_LVDS_0>;
> +
> + channel@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + phys = <&mipi_lvds_0_phy>;
> + phy-names = "lvds_phy";
> +
> + port@0 {
> + reg = <0>;
> +
> + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
> + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + /* ... */
> + };
> + };
> +
> + channel@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + phys = <&mipi_lvds_0_phy>;
> + phy-names = "lvds_phy";
> +
> + port@0 {
> + reg = <0>;
> +
> + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
> + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + /* ... */
> + };
> + };
> + };
> + };
> +
> + mipi_lvds_0_phy: phy@56228300 {
> + compatible = "fsl,imx8qxp-mipi-dphy";
> + reg = <0x56228300 0x100>;
> + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
> + clock-names = "phy_ref";
> + #phy-cells = <0>;
> + fsl,syscon = <&mipi_lvds_0_csr>;
> + power-domains = <&pd IMX_SC_R_MIPI_0>;
> + };
> --
> 2.7.4
>
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding
2021-03-10 9:55 ` [PATCH v5 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding Liu Ying
@ 2021-03-16 22:40 ` Rob Herring
0 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2021-03-16 22:40 UTC (permalink / raw)
To: Liu Ying
Cc: devicetree, jernej.skrabec, linux-media, narmstrong, airlied,
lee.jones, s.hauer, jonas, linux-kernel, dri-devel, kishon,
a.hajda, vkoul, robh+dt, robert.foss, kernel, linux-imx, mchehab,
shawnguo, linux-arm-kernel, Laurent.pinchart
On Wed, 10 Mar 2021 17:55:32 +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v4->v5:
> * No change.
>
> v3->v4:
> * Add 'fsl,sc-resource' property. (Rob)
>
> v2->v3:
> * Drop 'fsl,syscon' property. (Rob)
> * Mention the CSR module controls PXL2DPI.
>
> v1->v2:
> * Use graph schema. (Laurent)
>
> .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 108 +++++++++++++++++++++
> 1 file changed, 108 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5 07/14] dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding
2021-03-16 22:38 ` Rob Herring
@ 2021-03-17 2:04 ` Liu Ying
0 siblings, 0 replies; 24+ messages in thread
From: Liu Ying @ 2021-03-17 2:04 UTC (permalink / raw)
To: Rob Herring
Cc: narmstrong, airlied, dri-devel, a.hajda, Laurent.pinchart,
lee.jones, kishon, linux-imx, linux-media, devicetree, jonas,
s.hauer, mchehab, linux-arm-kernel, jernej.skrabec, linux-kernel,
robert.foss, vkoul, kernel, shawnguo
On Tue, 2021-03-16 at 16:38 -0600, Rob Herring wrote:
> On Wed, Mar 10, 2021 at 05:55:31PM +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.
> >
> > Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > ---
> > v4->v5:
> > * Newly introduced in v5. (Rob)
> >
> > .../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml | 202 +++++++++++++++++++++
> > 1 file changed, 202 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
> > new file mode 100644
> > index 00000000..0e724d9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
> > @@ -0,0 +1,202 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fmfd%2Ffsl%2Cimx8qxp-csr.yaml%23&data=04%7C01%7Cvictor.liu%40nxp.com%7C8ee75a0dde484a3d221608d8e8cc47f6%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637515311382184508%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=fkym85OLtd5cA%2FdwJkXUbiR0EwkZX4yP4INsAaCywUo%3D&reserved=0
> > +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cvictor.liu%40nxp.com%7C8ee75a0dde484a3d221608d8e8cc47f6%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637515311382184508%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=3n2mTxsUNF480D9xQQuXj7U0noiLCUBT3zneyWPr6ck%3D&reserved=0
> > +
> > +title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
> > +
> > +maintainers:
> > + - Liu Ying <victor.liu@nxp.com>
> > +
> > +description: |
> > + As a system controller, the Freescale i.MX8qm/qxp Control and Status
> > + Registers(CSR) module represents a set of miscellaneous registers of a
> > + specific subsystem. It may provide control and/or status report interfaces
> > + to a mix of standalone hardware devices within that subsystem. One typical
> > + use-case is for some other nodes to acquire a reference to the syscon node
> > + by phandle, and the other typical use-case is that the operating system
> > + should consider all subnodes of the CSR module as separate child devices.
> > +
> > +select:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - fsl,imx8qxp-mipi-lvds-csr
> > + - fsl,imx8qm-lvds-csr
>
> You shouldn't need this, we filter out 'syscon' and 'simple-mfd'.
Will drop this in next version. Thanks.
Liu Ying
>
> > + required:
> > + - compatible
> > +
> > +properties:
> > + $nodename:
> > + pattern: "^syscon@[0-9a-f]+$"
> > +
> > + compatible:
> > + items:
> > + - enum:
> > + - fsl,imx8qxp-mipi-lvds-csr
> > + - fsl,imx8qm-lvds-csr
> > + - const: syscon
> > + - const: simple-mfd
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + const: ipg
> > +
> > +patternProperties:
> > + "^(ldb|phy|pxl2dpi)$":
> > + type: object
> > + description: The possible child devices of the CSR module.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: fsl,imx8qxp-mipi-lvds-csr
> > + then:
> > + required:
> > + - pxl2dpi
> > + - ldb
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: fsl,imx8qm-lvds-csr
> > + then:
> > + required:
> > + - phy
> > + - ldb
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/imx8-lpcg.h>
> > + #include <dt-bindings/firmware/imx/rsrc.h>
> > + mipi_lvds_0_csr: syscon@56221000 {
> > + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
> > + reg = <0x56221000 0x1000>;
> > + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
> > + clock-names = "ipg";
> > +
> > + mipi_lvds_0_pxl2dpi: pxl2dpi {
> > + compatible = "fsl,imx8qxp-pxl2dpi";
> > + fsl,sc-resource = <IMX_SC_R_MIPI_0>;
> > + power-domains = <&pd IMX_SC_R_MIPI_0>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0>;
> > +
> > + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
> > + };
> > +
> > + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
> > + };
> > + };
> > +
> > + port@1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <1>;
> > +
> > + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
> > + };
> > +
> > + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + mipi_lvds_0_ldb: ldb {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx8qxp-ldb";
> > + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
> > + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
> > + clock-names = "pixel", "bypass";
> > + power-domains = <&pd IMX_SC_R_LVDS_0>;
> > +
> > + channel@0 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0>;
> > + phys = <&mipi_lvds_0_phy>;
> > + phy-names = "lvds_phy";
> > +
> > + port@0 {
> > + reg = <0>;
> > +
> > + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
> > + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > +
> > + /* ... */
> > + };
> > + };
> > +
> > + channel@1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <1>;
> > + phys = <&mipi_lvds_0_phy>;
> > + phy-names = "lvds_phy";
> > +
> > + port@0 {
> > + reg = <0>;
> > +
> > + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
> > + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > +
> > + /* ... */
> > + };
> > + };
> > + };
> > + };
> > +
> > + mipi_lvds_0_phy: phy@56228300 {
> > + compatible = "fsl,imx8qxp-mipi-dphy";
> > + reg = <0x56228300 0x100>;
> > + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
> > + clock-names = "phy_ref";
> > + #phy-cells = <0>;
> > + fsl,syscon = <&mipi_lvds_0_csr>;
> > + power-domains = <&pd IMX_SC_R_MIPI_0>;
> > + };
> > --
> > 2.7.4
> >
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^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2021-03-17 2:05 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-10 9:55 [PATCH v5 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs Liu Ying
2021-03-10 9:55 ` [PATCH v5 01/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner Liu Ying
2021-03-10 13:45 ` Laurent Pinchart
2021-03-10 9:55 ` [PATCH v5 02/14] media: docs: " Liu Ying
2021-03-10 13:24 ` Laurent Pinchart
2021-03-11 5:26 ` Liu Ying
2021-03-10 9:55 ` [PATCH v5 03/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding Liu Ying
2021-03-10 9:55 ` [PATCH v5 04/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support Liu Ying
2021-03-10 9:55 ` [PATCH v5 05/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding Liu Ying
2021-03-10 9:55 ` [PATCH v5 06/14] drm/bridge: imx: Add i.MX8qm/qxp display pixel link support Liu Ying
2021-03-10 9:55 ` [PATCH v5 07/14] dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding Liu Ying
2021-03-16 22:38 ` Rob Herring
2021-03-17 2:04 ` Liu Ying
2021-03-10 9:55 ` [PATCH v5 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding Liu Ying
2021-03-16 22:40 ` Rob Herring
2021-03-10 9:55 ` [PATCH v5 09/14] drm/bridge: imx: Add i.MX8qxp pixel link to DPI support Liu Ying
2021-03-10 9:55 ` [PATCH v5 10/14] drm/bridge: imx: Add LDB driver helper support Liu Ying
2021-03-10 9:55 ` [PATCH v5 11/14] dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding Liu Ying
2021-03-10 9:55 ` [PATCH v5 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp Liu Ying
2021-03-10 12:16 ` kernel test robot
2021-03-10 19:38 ` kernel test robot
2021-03-10 9:55 ` [PATCH v5 13/14] drm/bridge: imx: Add LDB support for i.MX8qm Liu Ying
2021-03-10 13:25 ` kernel test robot
2021-03-10 9:55 ` [PATCH v5 14/14] MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs Liu Ying
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