From: Vinod Polimera <quic_vpolimer@quicinc.com>
To: <dri-devel@lists.freedesktop.org>,
<linux-arm-msm@vger.kernel.org>,
<freedreno@lists.freedesktop.org>, <devicetree@vger.kernel.org>
Cc: quic_kalyant@quicinc.com, quic_sbillaka@quicinc.com,
quic_bjorande@quicinc.com, quic_abhinavk@quicinc.com,
quic_vproddut@quicinc.com, quic_khsieh@quicinc.com,
dianders@chromium.org, linux-kernel@vger.kernel.org,
dmitry.baryshkov@linaro.org, swboyd@chromium.org,
Vinod Polimera <quic_vpolimer@quicinc.com>
Subject: [PATCH v14 05/14] drm/msm/disp/dpu: get timing engine status from intf status register
Date: Thu, 2 Mar 2023 22:03:08 +0530 [thread overview]
Message-ID: <1677774797-31063-6-git-send-email-quic_vpolimer@quicinc.com> (raw)
In-Reply-To: <1677774797-31063-1-git-send-email-quic_vpolimer@quicinc.com>
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +++++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +++++++-
3 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index cf053e8..85b29d6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -78,7 +78,8 @@
#define INTF_SDM845_MASK (0)
-#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
+#define INTF_SC7180_MASK \
+ (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED))
#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index ddab9ca..08cd1a1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -213,17 +213,19 @@ enum {
/**
* INTF sub-blocks
- * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
- * pixel data arrives to this INTF
- * @DPU_INTF_TE INTF block has TE configuration support
- * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
- than video timing
+ * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
+ * pixel data arrives to this INTF
+ * @DPU_INTF_TE INTF block has TE configuration support
+ * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
+ * than video timing
+ * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
* @DPU_INTF_MAX
*/
enum {
DPU_INTF_INPUT_CTRL = 0x1,
DPU_INTF_TE,
DPU_DATA_HCTL_EN,
+ DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 7ce66bf..84ee2ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -62,6 +62,7 @@
#define INTF_LINE_COUNT 0x0B0
#define INTF_MUX 0x25C
+#define INTF_STATUS 0x26C
#define INTF_CFG_ACTIVE_H_EN BIT(29)
#define INTF_CFG_ACTIVE_V_EN BIT(30)
@@ -297,8 +298,13 @@ static void dpu_hw_intf_get_status(
struct intf_status *s)
{
struct dpu_hw_blk_reg_map *c = &intf->hw;
+ unsigned long cap = intf->cap->features;
+
+ if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))
+ s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);
+ else
+ s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
- s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31));
if (s->is_en) {
s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
--
2.7.4
next prev parent reply other threads:[~2023-03-02 16:34 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-02 16:33 [PATCH v14 00/14] Add PSR support for eDP Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 01/14] drm: add helper functions to retrieve old and new crtc Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 02/14] drm/bridge: use atomic enable/disable callbacks for panel bridge Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 03/14] drm/bridge: add psr support for panel bridge callbacks Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 04/14] drm/msm/disp/dpu: check for crtc enable rather than crtc active to release shared resources Vinod Polimera
2023-03-02 16:33 ` Vinod Polimera [this message]
2023-03-02 16:33 ` [PATCH v14 06/14] drm/msm/disp/dpu: wait for extra vsync till timing engine status is disabled Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 07/14] drm/msm/disp/dpu: reset the datapath after timing engine disable Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 08/14] drm/msm/dp: use atomic callbacks for DP bridge ops Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 09/14] drm/msm/dp: Add basic PSR support for eDP Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 10/14] drm/msm/dp: use the eDP bridge ops to validate eDP modes Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 11/14] drm/msm/disp/dpu: use atomic enable/disable callbacks for encoder functions Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 12/14] drm/msm/disp/dpu: add PSR support for eDP interface in dpu driver Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 13/14] drm/msm/disp/dpu: update dpu_enc crtc state on crtc enable/disable during self refresh Vinod Polimera
2023-03-14 10:32 ` Vinod Polimera
2023-03-02 16:33 ` [PATCH v14 14/14] drm/msm/dp: set self refresh aware based on PSR support Vinod Polimera
2023-03-02 16:40 ` Dmitry Baryshkov
2023-03-26 16:27 ` Bjorn Andersson
2023-03-26 16:35 ` Bjorn Andersson
2023-03-27 16:27 ` Stephen Boyd
2023-03-29 15:16 ` Vinod Polimera
2023-03-29 15:47 ` Doug Anderson
2023-03-30 14:23 ` Doug Anderson
2023-03-30 14:27 ` Vinod Polimera
2023-03-26 22:02 ` Dmitry Baryshkov
2023-03-06 17:35 ` [PATCH v14 00/14] Add PSR support for eDP Doug Anderson
2023-03-07 13:54 ` Dmitry Baryshkov
2023-03-16 0:44 ` Dmitry Baryshkov
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