[RFC 00/13] Add support for DP-HDMI2.1 PCON

[RFC 00/13] Add support for DP-HDMI2.1 PCON

[Ankit Nautiyal]

This patch series attempts to add support for a DP-HDMI2.1 Protocol
Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata
E5 to DisplayPort_v2.0:
https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299
The details are mentioned in DP to HDMI2.1 PCON Enum/Config
improvement slide decks:
https://groups.vesa.org/wg/DP/document/folder/1316

This RFC series starts with adding support for FRL (Fixed Rate Link)
Training between the PCON and HDMI2.1 sink.
As per HDMI2.1 specification, a new data-channel or lane is added in
FRL mode, by repurposing the TMDS clock Channel. Through FRL, higher
bit-rate can be supported, ie. up to 12 Gbps/lane (48 Gbps over 4
lanes).

With these patches, the HDMI2.1 PCON can be configured to achieve FRL
training based on the maximum FRL rate supported by the panel, source
and the PCON.
The approach is to add the support for FRL training between PCON and
HDMI2.1 sink and gradually add other blocks for supporting higher
resolutions and other HDMI2.1 features, that can be supported by pcon
for the sources that do not natively support HDMI2.1.

This is done before the DP Link training between the source and PCON
is started. In case of FRL training is not achieved, the PCON will
work in the regular TMDS mode, without HDMI2.1 feature support.
Any interruption in FRL training between the PCON and HDMI2.1 sink is
notified through IRQ_HPD. On receiving the IRQ_HPD the concerned DPCD
registers are read and FRL training is re-attempted.

Currently, we have tested the FRL training and are able to enable 4K
display with TGL Platform + Realtek PCON RTD2173 with HDMI2.1 supporting
panel.

v2: Added patch to capture the PCON FRL caps in downstream facing port
cap structure.

v3: Added patches for getting DSC capabilities of the PCON DSC encoder
and HDMI decoder. Added support to configure PCON for DSC1.1 decoding
and DSC1.2 encoding.

Ankit Nautiyal (9):
  drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON
  drm/i915: Capture max frl rate for PCON in dfp cap structure
  drm/i915: Add support for starting FRL training for HDMI2.1 via PCON
  drm/i915: Check for FRL training before DP Link training
  drm/edid: Parse DSC1.2 cap fields from HFVSDB block
  drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon
  drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder
  drm/i915: Add helper functions for calculating DSC parameters for
    HDMI2.1
  drm/i915: Configure PCON for DSC1.1 to DSC1.2 encoding

Swati Sharma (4):
  drm/edid: Add additional HFVSDB fields for HDMI2.1
  drm/edid: Parse MAX_FRL field from HFVSDB block
  drm/dp_helper: Add support for link status and link recovery
  drm/i915: Add support for enabling link status and recovery

 drivers/gpu/drm/drm_dp_helper.c               | 431 +++++++++++++
 drivers/gpu/drm/drm_edid.c                    |  70 +++
 drivers/gpu/drm/i915/display/intel_ddi.c      |   2 +
 .../drm/i915/display/intel_display_types.h    |  24 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 576 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   4 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 171 ++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h     |   7 +
 include/drm/drm_connector.h                   |  38 ++
 include/drm/drm_dp_helper.h                   | 205 +++++++
 include/drm/drm_edid.h                        |  30 +
 11 files changed, 1553 insertions(+), 5 deletions(-)

-- 
2.17.1

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[RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1

[Ankit Nautiyal]

From: Swati Sharma <swati2.sharma@intel.com>

The HDMI2.1 extends HFVSBD (HDMI Forum Vendor Specific
Data block) to have fields related to newly defined methods of FRL
(Fixed Rate Link) levels, number of lanes supported, DSC Color bit
depth, VRR min/max, FVA (Fast Vactive), ALLM etc.

This patch adds the new HFVSDB fields that are required for
HDMI2.1.

Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b27a0e2169c8..1cc5c2c73282 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -229,6 +229,36 @@ struct detailed_timing {
 				    DRM_EDID_YCBCR420_DC_36 | \
 				    DRM_EDID_YCBCR420_DC_30)
 
+/* HDMI 2.1 additional fields */
+#define DRM_EDID_MAX_FRL_RATE_MASK		0xf0
+#define DRM_EDID_FAPA_START_LOCATION		(1 << 0)
+#define DRM_EDID_ALLM				(1 << 1)
+#define DRM_EDID_FVA				(1 << 2)
+
+/* Deep Color specific */
+#define DRM_EDID_DC_30BIT_420			(1 << 0)
+#define DRM_EDID_DC_36BIT_420			(1 << 1)
+#define DRM_EDID_DC_48BIT_420			(1 << 2)
+
+/* VRR specific */
+#define DRM_EDID_CNMVRR				(1 << 3)
+#define DRM_EDID_CINEMA_VRR			(1 << 4)
+#define DRM_EDID_MDELTA				(1 << 5)
+#define DRM_EDID_VRR_MAX_UPPER_MASK		0xc0
+#define DRM_EDID_VRR_MAX_LOWER_MASK		0xff
+#define DRM_EDID_VRR_MIN_MASK			0x3f
+
+/* DSC specific */
+#define DRM_EDID_DSC_10BPC			(1 << 0)
+#define DRM_EDID_DSC_12BPC			(1 << 1)
+#define DRM_EDID_DSC_16BPC			(1 << 2)
+#define DRM_EDID_DSC_ALL_BPP			(1 << 3)
+#define DRM_EDID_DSC_NATIVE_420			(1 << 6)
+#define DRM_EDID_DSC_1P2			(1 << 7)
+#define DRM_EDID_DSC_MAX_FRL_RATE		0xf
+#define DRM_EDID_DSC_MAX_SLICES			0xf
+#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES		0x3f
+
 /* ELD Header Block */
 #define DRM_ELD_HEADER_BLOCK_SIZE	4
 
-- 
2.17.1

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[RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block

[Ankit Nautiyal]

From: Swati Sharma <swati2.sharma@intel.com>

This patch parses MAX_FRL field to get the MAX rate in Gbps that
the HDMI 2.1 panel can support in FRL mode. Source need this
field to determine the optimal rate between the source and sink
during FRL training.

Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/drm_edid.c  | 51 +++++++++++++++++++++++++++++++++++++
 include/drm/drm_connector.h |  6 +++++
 2 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 631125b46e04..8afb136e73f5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4849,6 +4849,52 @@ static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
 		info->rgb_quant_range_selectable = true;
 }
 
+static
+void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
+{
+	switch(max_frl_rate) {
+	case 1:
+		*max_lanes = 3;
+		*max_rate_per_lane = 3;
+		break;
+	case 2:
+		*max_lanes = 3;
+		*max_rate_per_lane = 6;
+		break;
+	case 3:
+		*max_lanes = 4;
+		*max_rate_per_lane = 6;
+		break;
+	case 4:
+		*max_lanes = 4;
+		*max_rate_per_lane = 8;
+		break;
+	case 5:
+		*max_lanes = 4;
+		*max_rate_per_lane = 10;
+		break;
+	case 6:
+		*max_lanes = 4;
+		*max_rate_per_lane = 12;
+		break;
+	case 0:
+	default:
+		*max_lanes = 0;
+		*max_rate_per_lane = 0;
+	}
+}
+
+static void drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,
+						const u8 *db)
+{
+	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
+	u8 max_frl_rate;
+
+	max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;
+	drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
+			     &hdmi->max_frl_rate_per_lane);
+}
+
 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
 					       const u8 *db)
 {
@@ -4902,6 +4948,11 @@ static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
 		}
 	}
 
+	if (hf_vsdb[7]) {
+		    DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
+		    drm_parse_hdmi_21_additional_fields(connector, hf_vsdb);
+	}
+
 	drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
 }
 
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 928136556174..f351bf10c076 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -207,6 +207,12 @@ struct drm_hdmi_info {
 
 	/** @y420_dc_modes: bitmap of deep color support index */
 	u8 y420_dc_modes;
+
+	/** @max_frl_rate_per_lane: support fixed rate link */
+	u8 max_frl_rate_per_lane;
+
+	/** @max_lanes: supported by sink */
+	u8 max_lanes;
 };
 
 /**
-- 
2.17.1

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[RFC 03/13] drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON

[Ankit Nautiyal]

This patch adds support for configuring a PCON device,
connected as a DP branched device to enable FRL Link training
with a HDMI2.1 + sink.

v2: Minor changes:
-removed unnecessary argument supplied to a drm helper function.
-fixed return value for max frl read from pcon.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 305 ++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     |  80 +++++++++
 2 files changed, 385 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 14ddf28ecac0..df858533dbf7 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -2591,3 +2591,308 @@ void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
 #undef DP_SDP_LOG
 }
 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
+
+/**
+ * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ *
+ * Returns maximum frl bandwidth supported by PCON in GBPS,
+ * returns 0 if not supported.
+ **/
+int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+			       const u8 port_cap[4])
+{
+	int bw;
+	u8 buf;
+
+	buf = port_cap[2];
+	bw = buf & DP_PCON_MAX_FRL_BW;
+
+	switch (bw) {
+	case DP_PCON_MAX_9GBPS:
+		return 9;
+	case DP_PCON_MAX_18GBPS:
+		return 18;
+	case DP_PCON_MAX_24GBPS:
+		return 24;
+	case DP_PCON_MAX_32GBPS:
+		return 32;
+	case DP_PCON_MAX_40GBPS:
+		return 40;
+	case DP_PCON_MAX_48GBPS:
+		return 48;
+	case DP_PCON_MAX_0GBPS:
+	default:
+		return 0;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
+
+/**
+ * drm_dp_get_hdmi_max_frl_bw() - maximum frl supported by HDMI Sink
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns maximum frl bandwidth supported by HDMI in Gbps on success,
+ * returns 0, if not supported.
+ **/
+int drm_dp_get_hdmi_max_frl_bw(struct drm_dp_aux *aux)
+{
+	u8 buf;
+	int bw, ret;
+
+	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_SINK, &buf);
+	if (ret < 0)
+		return 0;
+	bw = buf & DP_HDMI_SINK_LINK_BW;
+
+	switch (bw) {
+	case DP_HDMI_SINK_BW_9GBPS:
+		return 9;
+	case DP_HDMI_SINK_BW_18GBPS:
+		return 18;
+	case DP_HDMI_SINK_BW_24GBPS:
+		return 24;
+	case DP_HDMI_SINK_BW_32GBPS:
+		return 32;
+	case DP_HDMI_SINK_BW_40GBPS:
+		return 40;
+	case DP_HDMI_SINK_BW_48GBPS:
+		return 48;
+	case DP_HDMI_SINK_BW_0GBPS:
+	default:
+		return 0;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_hdmi_max_frl_bw);
+
+/**
+ * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns 0 if success, else returns negative error code.
+ **/
+int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
+{
+	int ret;
+	u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
+		 DP_PCON_ENABLE_LINK_FRL_MODE;
+
+	if (enable_frl_ready_hpd)
+		buf |= DP_PCON_ENABLE_HPD_READY;
+
+	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
+
+	return ret;
+}
+EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
+
+/**
+ * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns true if success, else returns false.
+ **/
+bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
+{
+	int ret;
+	u8 buf;
+
+	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
+	if (ret < 0)
+		return false;
+
+	if (buf & DP_PCON_FRL_READY)
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
+
+/**
+ * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
+ * @aux: DisplayPort AUX channel
+ * max_frl_mask: mask for selecting the bandwidths supported by source,
+ * to be tried by Pcon f/w.
+ * @concurrent_mode: true if concurrent mode or operation is required,
+ * false otherwise.
+ *
+ * Returns 0 if success, else returns negative error code.
+ **/
+
+int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
+				bool concurrent_mode)
+{
+	int ret;
+	u8 buf;
+
+	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
+	if (ret < 0)
+		return ret;
+
+	if (concurrent_mode)
+		buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
+	else
+		buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
+
+	switch (max_frl_gbps) {
+	case 9:
+		buf |=  DP_PCON_ENABLE_MAX_BW_9GBPS;
+		break;
+	case 18:
+		buf |=  DP_PCON_ENABLE_MAX_BW_18GBPS;
+		break;
+	case 24:
+		buf |=  DP_PCON_ENABLE_MAX_BW_24GBPS;
+		break;
+	case 32:
+		buf |=  DP_PCON_ENABLE_MAX_BW_32GBPS;
+		break;
+	case 40:
+		buf |=  DP_PCON_ENABLE_MAX_BW_40GBPS;
+		break;
+	case 48:
+		buf |=  DP_PCON_ENABLE_MAX_BW_48GBPS;
+		break;
+	case 0:
+		buf |=  DP_PCON_ENABLE_MAX_BW_0GBPS;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
+
+/**
+ * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
+ * @aux: DisplayPort AUX channel
+ * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
+ * @extended_train_mode : true for Extended Mode, false for Normal Mode.
+ * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
+ * from min, and stops when link training is successful. In Extended mode, all
+ * frl bw selected in the mask are trained by the PCON.
+ *
+ * Returns 0 if success, else returns negative error code.
+ **/
+int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
+				bool extended_train_mode)
+{
+	int ret;
+	u8 buf = 0;
+
+	buf |= max_frl_mask;
+
+	if (extended_train_mode)
+		buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
+
+	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
+
+/**
+ * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns 0 if success, else returns negative error code.
+ **/
+int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
+{
+	int ret;
+
+	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
+
+/**
+ * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns 0 if success, else returns negative error code.
+ **/
+int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
+{
+	int ret;
+	u8 buf = 0;
+
+	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
+	if (ret < 0)
+		return ret;
+	if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
+		DRM_DEBUG_KMS("PCON in Autonomous mode, can't enable FRL\n");
+		return -EINVAL;
+	}
+	buf |= DP_PCON_ENABLE_HDMI_LINK;
+	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
+
+/**
+ * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns true if link is active else returns false.
+ **/
+bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
+{
+	u8 buf;
+	int ret;
+
+	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
+	if (ret < 0)
+		return false;
+
+	return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
+}
+EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
+
+/**
+ * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
+ * @aux: DisplayPort AUX channel
+ * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
+ * Valid only if the MODE returned is FRL. For Normal Link training mode
+ * only 1 of the bits will be set, but in case of Extended mode, more than
+ * one bits can be set.
+ *
+ * Returns the link mode : TMDS or FRL on success, else retunes negative error
+ * code.
+ **/
+int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
+{
+	u8 buf;
+	int mode;
+	int ret;
+
+	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);
+	if (ret < 0)
+		return ret;
+
+	mode = buf & DP_PCON_HDMI_LINK_MODE;
+
+	if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
+		*frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
+
+	return mode;
+}
+EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f55a9d1320ca..d6f79b2d1287 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -411,6 +411,17 @@ struct drm_device;
 # define DP_DS_10BPC		            1
 # define DP_DS_12BPC		            2
 # define DP_DS_16BPC		            3
+/* HDMI2.1 PCON FRL CONFIGURATION */
+# define DP_PCON_MAX_FRL_BW                 (7 << 2)
+# define DP_PCON_MAX_0GBPS                  (0 << 2)
+# define DP_PCON_MAX_9GBPS                  (1 << 2)
+# define DP_PCON_MAX_18GBPS                 (2 << 2)
+# define DP_PCON_MAX_24GBPS                 (3 << 2)
+# define DP_PCON_MAX_32GBPS                 (4 << 2)
+# define DP_PCON_MAX_40GBPS                 (5 << 2)
+# define DP_PCON_MAX_48GBPS                 (6 << 2)
+# define DP_PCON_SOURCE_CTL_MODE            (1 << 5)
+
 /* offset 3 for DVI */
 # define DP_DS_DVI_DUAL_LINK		    (1 << 1)
 # define DP_DS_DVI_HIGH_COLOR_DEPTH	    (1 << 2)
@@ -1053,6 +1064,61 @@ struct drm_device;
 #define DP_CEC_RX_MESSAGE_BUFFER               0x3010
 #define DP_CEC_TX_MESSAGE_BUFFER               0x3020
 #define DP_CEC_MESSAGE_BUFFER_LENGTH             0x10
+/* PROTOCOL CONVERSION HDMI SINK */
+#define DP_PCON_HDMI_SINK                      0x3035
+# define DP_HDMI_SINK_LINK_BW                  (7 << 0)
+# define DP_HDMI_SINK_BW_0GBPS		       0
+# define DP_HDMI_SINK_BW_9GBPS		       1
+# define DP_HDMI_SINK_BW_18GBPS		       2
+# define DP_HDMI_SINK_BW_24GBPS		       3
+# define DP_HDMI_SINK_BW_32GBPS		       4
+# define DP_HDMI_SINK_BW_40GBPS		       5
+# define DP_HDMI_SINK_BW_48GBPS		       6
+
+/* PCON CONFIGURE-1 FRL FOR HDMI SINK */
+#define DP_PCON_HDMI_LINK_CONFIG_1             0x305A
+# define DP_PCON_ENABLE_MAX_FRL_BW             (7 << 0)
+# define DP_PCON_ENABLE_MAX_BW_0GBPS	       0
+# define DP_PCON_ENABLE_MAX_BW_9GBPS	       1
+# define DP_PCON_ENABLE_MAX_BW_18GBPS	       2
+# define DP_PCON_ENABLE_MAX_BW_24GBPS	       3
+# define DP_PCON_ENABLE_MAX_BW_32GBPS	       4
+# define DP_PCON_ENABLE_MAX_BW_40GBPS	       5
+# define DP_PCON_ENABLE_MAX_BW_48GBPS	       6
+# define DP_PCON_ENABLE_SOURCE_CTL_MODE       (1 << 3)
+# define DP_PCON_ENABLE_CONCURRENT_LINK       (1 << 4)
+# define DP_PCON_ENABLE_LINK_FRL_MODE         (1 << 5)
+# define DP_PCON_ENABLE_HPD_READY	      (1 << 6)
+# define DP_PCON_ENABLE_HDMI_LINK             (1 << 7)
+
+/* PCON CONFIGURE-2 FRL FOR HDMI SINK */
+#define DP_PCON_HDMI_LINK_CONFIG_2            0x305B
+# define DP_PCON_MAX_LINK_BW_MASK             (0x3F << 0)
+# define DP_PCON_FRL_BW_MASK_9GBPS            (1 << 0)
+# define DP_PCON_FRL_BW_MASK_18GBPS           (1 << 1)
+# define DP_PCON_FRL_BW_MASK_24GBPS           (1 << 2)
+# define DP_PCON_FRL_BW_MASK_32GBPS           (1 << 3)
+# define DP_PCON_FRL_BW_MASK_40GBPS           (1 << 4)
+# define DP_PCON_FRL_BW_MASK_48GBPS           (1 << 5)
+# define DP_PCON_FRL_LINK_TRAIN_EXTENDED      (1 << 6)
+
+/* PCON HDMI LINK STATUS */
+#define DP_PCON_HDMI_TX_LINK_STATUS           0x303B
+# define DP_PCON_HDMI_TX_LINK_ACTIVE          (1 << 0)
+# define DP_PCON_FRL_READY		      (1 << 1)
+
+/* PCON HDMI POST FRL STATUS */
+#define DP_PCON_HDMI_POST_FRL_STATUS          0x3036
+# define DP_PCON_HDMI_LINK_MODE               (1 << 0)
+# define DP_PCON_HDMI_MODE_TMDS               0
+# define DP_PCON_HDMI_MODE_FRL                1
+# define DP_PCON_HDMI_FRL_TRAINED_BW          (0x3F << 1)
+# define DP_PCON_FRL_TRAINED_BW_9GBPS	      (1 << 1)
+# define DP_PCON_FRL_TRAINED_BW_18GBPS	      (1 << 2)
+# define DP_PCON_FRL_TRAINED_BW_24GBPS	      (1 << 3)
+# define DP_PCON_FRL_TRAINED_BW_32GBPS	      (1 << 4)
+# define DP_PCON_FRL_TRAINED_BW_40GBPS	      (1 << 5)
+# define DP_PCON_FRL_TRAINED_BW_48GBPS	      (1 << 6)
 
 #define DP_PROTOCOL_CONVERTER_CONTROL_0		0x3050 /* DP 1.3 */
 # define DP_HDMI_DVI_OUTPUT_CONFIG		(1 << 0) /* DP 1.3 */
@@ -1967,4 +2033,18 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
 				struct drm_dp_phy_test_params *data);
 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
 				struct drm_dp_phy_test_params *data, u8 dp_rev);
+int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+			       const u8 port_cap[4]);
+int drm_dp_get_hdmi_max_frl_bw(struct drm_dp_aux *aux);
+int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
+bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
+int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
+				bool concurrent_mode);
+int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
+				bool extended_train_mode);
+int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
+int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
+
+bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
+int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
 #endif /* _DRM_DP_HELPER_H_ */
-- 
2.17.1

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[RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure

[Ankit Nautiyal]

HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and
by the sink.

This patch captures these in dfp cap structure in intel_dp and uses
these to prune connector modes that cannot be supported by the PCON
and sink FRL bandwidth.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 33 +++++++++++++++++--
 2 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0b5df8e44966..e2f58d0575a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1398,6 +1398,7 @@ struct intel_dp {
 	struct {
 		int min_tmds_clock, max_tmds_clock;
 		int max_dotclock;
+		int pcon_max_frl, sink_max_frl;
 		u8 max_bpc;
 		bool ycbcr_444_to_420;
 	} dfp;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0902a9aeeda1..cd6934f28f32 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -683,6 +683,24 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 	const struct drm_display_info *info = &connector->base.display_info;
 	int tmds_clock;
 
+	/* If PCON and HDMI2.1 sink both support FRL MODE, check FRL
+	 * bandwidth constraints.
+	 */
+	if (intel_dp->dfp.pcon_max_frl) {
+		int target_bw;
+		int max_frl_bw;
+		int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
+
+		target_bw = bpp * DIV_ROUND_UP(target_clock, 1000000);
+
+		max_frl_bw = min(intel_dp->dfp.pcon_max_frl,
+				 intel_dp->dfp.sink_max_frl);
+		if (target_bw > max_frl_bw)
+			return MODE_CLOCK_HIGH;
+
+		return MODE_OK;
+	}
+
 	if (intel_dp->dfp.max_dotclock &&
 	    target_clock > intel_dp->dfp.max_dotclock)
 		return MODE_CLOCK_HIGH;
@@ -6383,13 +6401,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
 						 intel_dp->downstream_ports,
 						 edid);
 
+	intel_dp->dfp.pcon_max_frl =
+		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
+					   intel_dp->downstream_ports);
+
+	intel_dp->dfp.sink_max_frl = drm_dp_get_hdmi_max_frl_bw(&intel_dp->aux);
+
 	drm_dbg_kms(&i915->drm,
-		    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d\n",
+		    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n",
 		    connector->base.base.id, connector->base.name,
 		    intel_dp->dfp.max_bpc,
 		    intel_dp->dfp.max_dotclock,
 		    intel_dp->dfp.min_tmds_clock,
-		    intel_dp->dfp.max_tmds_clock);
+		    intel_dp->dfp.max_tmds_clock,
+		    intel_dp->dfp.pcon_max_frl,
+		    intel_dp->dfp.sink_max_frl);
 }
 
 static void
@@ -6479,6 +6505,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
 	intel_dp->dfp.min_tmds_clock = 0;
 	intel_dp->dfp.max_tmds_clock = 0;
 
+	intel_dp->dfp.pcon_max_frl = 0;
+	intel_dp->dfp.sink_max_frl = 0;
+
 	intel_dp->dfp.ycbcr_444_to_420 = false;
 	connector->base.ycbcr_420_allowed = false;
 }
-- 
2.17.1

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[RFC 05/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON

[Ankit Nautiyal]

This patch adds functions to start FRL training for an HDMI2.1 sink,
connected via a PCON as a DP branch device.
This patch also adds a new structure for storing frl training related
data, when FRL training is completed.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |   7 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 200 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +
 3 files changed, 209 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2f58d0575a2..6c69922313d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1287,6 +1287,11 @@ struct intel_dp_compliance {
 	u8 test_lane_count;
 };
 
+struct intel_dp_pcon_frl {
+	bool is_trained;
+	int trained_rate_gbps;
+};
+
 struct intel_dp {
 	i915_reg_t output_reg;
 	u32 DP;
@@ -1408,6 +1413,8 @@ struct intel_dp {
 
 	bool hobl_failed;
 	bool hobl_active;
+
+	struct intel_dp_pcon_frl frl;
 };
 
 enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cd6934f28f32..c1342b5e7781 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2885,6 +2885,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 			intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
 		else
 			intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
+
+		intel_dp->frl.is_trained = false;
+		intel_dp->frl.trained_rate_gbps = 0;
 	}
 }
 
@@ -3781,6 +3784,9 @@ static void intel_disable_dp(struct intel_atomic_state *state,
 	intel_edp_backlight_off(old_conn_state);
 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 	intel_edp_panel_off(intel_dp);
+
+	intel_dp->frl.is_trained = false;
+	intel_dp->frl.trained_rate_gbps = 0;
 }
 
 static void g4x_disable_dp(struct intel_atomic_state *state,
@@ -3876,6 +3882,200 @@ cpt_set_link_train(struct intel_dp *intel_dp,
 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
 }
 
+static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp)
+{
+	int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps;
+
+	max_link_clock = intel_dp_max_link_rate(intel_dp);
+	max_lanes = intel_dp_max_lane_count(intel_dp);
+	max_rate_khz = intel_dp_max_data_rate(max_link_clock, max_lanes);
+	max_rate_gbps = 8 * DIV_ROUND_UP(max_rate_khz, 1000000);
+
+	return max_rate_gbps;
+}
+
+static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
+{
+	int bw_gbps[] = {9, 18, 24, 32, 40, 48};
+	int i;
+
+	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
+		if (frl_bw_mask & (1 << i))
+			return bw_gbps[i];
+	}
+	return 0;
+}
+
+static int intel_dp_pcon_set_frl_mask(int max_frl)
+{
+	int max_frl_mask = 0;
+
+	switch (max_frl) {
+	case 48:
+		max_frl_mask |= DP_PCON_FRL_BW_MASK_48GBPS;
+		break;
+	case 40:
+		max_frl_mask |= DP_PCON_FRL_BW_MASK_40GBPS;
+		break;
+	case 32:
+		max_frl_mask |= DP_PCON_FRL_BW_MASK_32GBPS;
+		break;
+	case 24:
+		max_frl_mask |= DP_PCON_FRL_BW_MASK_24GBPS;
+		break;
+	case 18:
+		max_frl_mask |= DP_PCON_FRL_BW_MASK_18GBPS;
+		break;
+	case 9:
+		max_frl_mask |= DP_PCON_FRL_BW_MASK_9GBPS;
+		break;
+	default:
+		max_frl_mask = 0;
+	}
+
+	return max_frl_mask;
+}
+
+static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
+{
+	struct intel_connector *intel_connector = intel_dp->attached_connector;
+	struct drm_connector *connector = &intel_connector->base;
+
+	return (connector->display_info.hdmi.max_frl_rate_per_lane *
+		connector->display_info.hdmi.max_lanes);
+}
+
+static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
+{
+#define PCON_EXTENDED_TRAIN_MODE true
+#define PCON_CONCURRENT_MODE true
+#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
+#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
+#define TIMEOUT_FRL_READY_MS 500
+#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
+
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	int max_frl, max_pcon_frl, max_sink_frl, max_rate_gbps, max_frl_edid, ret;
+	u8 max_frl_mask = 0, frl_trained_mask;
+	bool is_active;
+
+	ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
+	if (ret < 0)
+		return ret;
+
+	max_rate_gbps = intel_dp_get_max_rate_gbps(intel_dp);
+	drm_dbg(&i915->drm, "Source max rate = %d Gbps\n", max_rate_gbps);
+
+	max_pcon_frl = intel_dp->dfp.pcon_max_frl;
+	drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl);
+
+	/* Double Check from HDMI SINK EDID */
+	max_frl_edid = intel_dp_hdmi_sink_max_frl(intel_dp);
+	drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_frl_edid);
+
+	max_sink_frl = intel_dp->dfp.sink_max_frl;
+	drm_dbg(&i915->drm, "Sink max rate from PCON = %d Gbps\n", max_sink_frl);
+
+	/* TODO MAX SINK FRL from PCON is not enumerated. Using MAX FRL value
+	 * directly from EDID. Need to confirm from Spec.
+	 */
+	max_frl = min(max_rate_gbps, min(max_frl_edid, max_pcon_frl));
+
+	if (max_frl <= 0)
+		return -EINVAL;
+
+	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
+	if (ret < 0)
+		return ret;
+	/* Wait for PCON to be FRL Ready */
+	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
+
+	if (!is_active)
+		return -ETIMEDOUT;
+
+	max_frl_mask = intel_dp_pcon_set_frl_mask(max_frl);
+	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl, PCON_SEQUENTIAL_MODE);
+	if (ret < 0)
+		return ret;
+	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_mask, PCON_NORMAL_TRAIN_MODE);
+	if (ret < 0)
+		return ret;
+	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
+	if (ret < 0)
+		return ret;
+	/*
+	 * Wait for FRL to be completed
+	 * Check if the HDMI Link is up and active.
+	 */
+	wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
+
+	if (!is_active)
+		return -ETIMEDOUT;
+	/*
+	 * Verify HDMI Link configuration shows FRL Mode.
+	 */
+	if (DP_PCON_HDMI_MODE_FRL != drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask)) {
+		drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
+		return -EINVAL;
+	}
+	drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_mask, frl_trained_mask);
+
+	/*
+	 * Read HDMI_LINK_STATUS_TRAINED 0x2005 bit 5
+	 * TODO: Details not mentioned in spec. Need to check.
+	 */
+
+	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
+	intel_dp->frl.is_trained = true;
+	drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
+
+	return 0;
+}
+
+static bool intel_dp_is_frl_required(struct intel_dp *intel_dp)
+{
+	if (!intel_dp->frl.is_trained)
+		return true;
+	/*
+	 * #TODO check if the mode really required FRL or can work
+	 * with TMDS mode.
+	 */
+
+	return false;
+}
+
+static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
+{
+	if (drm_dp_is_branch(intel_dp->dpcd) &&
+	    intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
+		return true;
+
+	return false;
+}
+
+void intel_dp_check_frl_training(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
+	    !intel_dp_is_frl_required(intel_dp))
+		return;
+
+	if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
+		int ret, mode;
+
+		drm_dbg(&dev_priv->drm, "Couldnt set FRL mode, continuing with TMDS mode\n");
+		ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
+		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
+
+		if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
+			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
+	}
+
+	else
+		drm_dbg(&dev_priv->drm, "FRL training Completed\n");
+}
+
 static void
 g4x_set_link_train(struct intel_dp *intel_dp,
 		   const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index fcc28eb242f2..81d83d88cd41 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -143,4 +143,6 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
 void intel_dp_sync_state(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state);
 
+void intel_dp_check_frl_training(struct intel_dp *intel_dp);
+
 #endif /* __INTEL_DP_H__ */
-- 
2.17.1

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[RFC 06/13] drm/i915: Check for FRL training before DP Link training

[Ankit Nautiyal]

This patch calls functions to check FRL training requirements
for an HDMI2.1 sink, when connected through PCON.
The call is made before the DP link training. In case FRL is not
required or failure during FRL training, the TMDS mode is selected
for the pcon.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
 drivers/gpu/drm/i915/display/intel_dp.c  | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bb0b9930958f..1834e5de60a7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3484,6 +3484,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 
+	intel_dp_check_frl_training(intel_dp);
+
 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
 	/*
 	 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c1342b5e7781..668165dd2b1a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4206,6 +4206,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 
 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_configure_protocol_converter(intel_dp);
+	intel_dp_check_frl_training(intel_dp);
 	intel_dp_start_link_train(intel_dp, pipe_config);
 	intel_dp_stop_link_train(intel_dp, pipe_config);
 
@@ -6127,6 +6128,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
 		    !intel_dp_mst_is_master_trans(crtc_state))
 			continue;
 
+		intel_dp_check_frl_training(intel_dp);
 		intel_dp_start_link_train(intel_dp, crtc_state);
 		intel_dp_stop_link_train(intel_dp, crtc_state);
 		break;
-- 
2.17.1

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[RFC 07/13] drm/dp_helper: Add support for link status and link recovery

[Ankit Nautiyal]

From: Swati Sharma <swati2.sharma@intel.com>

This patch adds support for link status and link recovery. There
are specific DPCD’s defined for link status check and recovery in
case of any issues. PCON will communicate the same using an IRQ_HPD
to source. HDMI sink would have indicated the same to PCON using
SCDC interrupt mechanism. While source can always read final HDMI
sink’s status using I2C over AUX, it’s easier and faster to read
the PCON’s already read HDMI sink’s status registers.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 33 +++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     | 16 ++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index df858533dbf7..33a4ac2fb225 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -2896,3 +2896,36 @@ int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
 	return mode;
 }
 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
+
+void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
+					   struct drm_connector *connector)
+{
+	u8 buf, error_count;
+	int i, num_error;
+	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
+
+	for (i = 0; i < hdmi->max_lanes; i++)
+	{
+		if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i , &buf) < 0)
+			return;
+
+		error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
+
+	switch(error_count) {
+	case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
+		num_error = 100;
+		break;
+	case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
+		num_error = 10;
+		break;
+	case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
+		num_error = 3;
+		break;
+	default:
+		num_error = 0;
+	}
+
+		DRM_ERROR("More than %d errors since the last read for lane %d", num_error, i);
+	}
+}
+EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d6f79b2d1287..eb26c86dc8ca 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -946,6 +946,11 @@ struct drm_device;
 # define DP_CEC_IRQ                          (1 << 2)
 
 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
+# define RX_CAP_CHANGED                      (1 << 0)
+# define LINK_STATUS_CHANGED                 (1 << 1)
+# define STREAM_STATUS_CHANGED               (1 << 2)
+# define HDMI_LINK_STATUS_CHANGED            (1 << 3)
+# define CONNECTED_OFF_ENTRY_REQUESTED       (1 << 4)
 
 #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
 # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
@@ -1130,6 +1135,16 @@ struct drm_device;
 #define DP_PROTOCOL_CONVERTER_CONTROL_2		0x3052 /* DP 1.3 */
 # define DP_CONVERSION_TO_YCBCR422_ENABLE	(1 << 0) /* DP 1.3 */
 
+/* PCON Downstream HDMI ERROR Status per Lane */
+#define DP_PCON_HDMI_ERROR_STATUS_LN0          0x3037
+#define DP_PCON_HDMI_ERROR_STATUS_LN1          0x3038
+#define DP_PCON_HDMI_ERROR_STATUS_LN2          0x3039
+#define DP_PCON_HDMI_ERROR_STATUS_LN3          0x303A
+# define DP_PCON_HDMI_ERROR_COUNT_MASK         (0x7 << 0)
+# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS   (1 << 0)
+# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS     (1 << 1)
+# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
+
 /* HDCP 1.3 and HDCP 2.2 */
 #define DP_AUX_HDCP_BKSV		0x68000
 #define DP_AUX_HDCP_RI_PRIME		0x68005
@@ -2047,4 +2062,5 @@ int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
 
 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
+void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, struct drm_connector *connector);
 #endif /* _DRM_DP_HELPER_H_ */
-- 
2.17.1

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[RFC 08/13] drm/i915: Add support for enabling link status and recovery

[Ankit Nautiyal]

From: Swati Sharma <swati2.sharma@intel.com>

In this patch enabled support for link status and recovery in i915
driver. HDMI link loss indication to upstream DP source is indicated
via IRQ_HPD. This is followed by reading of HDMI link configuration
status (HDMI_TX_LINK_ACTIVE_STATUS). If the PCON → HDMI 2.1 link status
is off; reinitiate frl link training to recover.
Also, HDMI FRL link error count range for each individual FRL
active lane is indicated by DOWNSTREAM_HDMI_ERROR_STATUS_LN registers.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 668165dd2b1a..e6c4cb844e37 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5955,6 +5955,29 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
 	return link_ok;
 }
 
+static void
+intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
+{
+	bool is_active;
+	u8 buf = 0;
+
+	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
+	if (intel_dp->frl.is_trained && !is_active) {
+		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
+			return;
+
+		buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
+		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
+			return;
+
+		intel_dp->frl.is_trained = false;
+		intel_dp->frl.trained_rate_gbps = 0;
+
+		intel_dp_check_frl_training(intel_dp);
+		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
+	}
+}
+
 static bool
 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
 {
@@ -6320,7 +6343,7 @@ intel_dp_hotplug(struct intel_encoder *encoder,
 	return state;
 }
 
-static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
+static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	u8 val;
@@ -6344,6 +6367,23 @@ static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
 		drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
 }
 
+static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
+{
+	u8 val;
+
+	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
+		return;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux,
+			      DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
+		return;
+
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val);
+
+	if (val & HDMI_LINK_STATUS_CHANGED)
+		intel_dp_handle_hdmi_link_status_change(intel_dp);
+}
+
 /*
  * According to DP spec
  * 5.1.2:
@@ -6383,7 +6423,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 		return false;
 	}
 
-	intel_dp_check_service_irq(intel_dp);
+	intel_dp_check_device_service_irq(intel_dp);
+	intel_dp_check_link_service_irq(intel_dp);
 
 	/* Handle CEC interrupts, if any */
 	drm_dp_cec_irq(&intel_dp->aux);
@@ -6815,7 +6856,7 @@ intel_dp_detect(struct drm_connector *connector,
 	    to_intel_connector(connector)->detect_edid)
 		status = connector_status_connected;
 
-	intel_dp_check_service_irq(intel_dp);
+	intel_dp_check_device_service_irq(intel_dp);
 
 out:
 	if (status != connector_status_connected && !intel_dp->is_mst)
-- 
2.17.1

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[RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block

[Ankit Nautiyal]

This patch parses HFVSDB fields for DSC1.2 capabilities of an
HDMI2.1 sink. These fields are required by a source to understand the
DSC capability of the sink, to set appropriate PPS parameters,
before transmitting compressed data stream.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/drm_edid.c  | 19 +++++++++++++++++++
 include/drm/drm_connector.h | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 8afb136e73f5..feee19657a7a 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4889,10 +4889,29 @@ static void drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,
 {
 	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
 	u8 max_frl_rate;
+	u8 dsc_max_frl_rate;
 
 	max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;
 	drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
 			     &hdmi->max_frl_rate_per_lane);
+
+	hdmi->dsc_1p2 = db[11] & DRM_EDID_DSC_1P2;
+        hdmi->dsc_native_420 = db[11] & DRM_EDID_DSC_NATIVE_420;
+	hdmi->dsc_all_bpp = db[11] & DRM_EDID_DSC_ALL_BPP;
+
+	if (db[11] & DRM_EDID_DSC_16BPC)
+		hdmi->dsc_bpc_supported = 16;
+	else if (db[11] & DRM_EDID_DSC_12BPC)
+		hdmi->dsc_bpc_supported = 12;
+	else if (db[11] & DRM_EDID_DSC_10BPC)
+		hdmi->dsc_bpc_supported = 10;
+	else
+		hdmi->dsc_bpc_supported = 0;
+
+	dsc_max_frl_rate = db[12] & DRM_EDID_DSC_MAX_FRL_RATE;
+	drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi->dsc_max_lanes,
+			     &hdmi->dsc_max_frl_rate_per_lane);
+	hdmi->dsc_total_chunk_kbytes = db[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
 }
 
 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index f351bf10c076..7100012f9c0f 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -213,6 +213,38 @@ struct drm_hdmi_info {
 
 	/** @max_lanes: supported by sink */
 	u8 max_lanes;
+
+	/** @dsc_1p2: flag for dsc1.2 support by sink */
+	bool dsc_1p2;
+
+	/** @dsc_native_420: Does sink support DSC with 4:2:0 compression */
+	bool dsc_native_420;
+
+	/**
+	 * @dsc_all_bpp: Does sink support all bpp with 4:4:4: or 4:2:2
+	 * compressed formats
+	 */
+	bool dsc_all_bpp;
+
+	/**
+	 * @dsc_bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc
+	 */
+	u8 dsc_bpc_supported;
+
+	/** @dsc_max_slices: maximum number of Horizontal slices supported by */
+	u8 dsc_max_slices;
+
+	/** @dsc_clk_per_slice : max pixel clock in MHz supported per slice */
+	u8 dsc_clk_per_slice;
+
+	/** @dsc_max_lanes : dsc max lanes supported for Fixed rate Link training */
+	u8 dsc_max_lanes;
+
+	/** @dsc_max_frl_rate_per_lane : maximum frl rate with DSC per lane */
+	u8 dsc_max_frl_rate_per_lane;
+
+	/** @dsc_total_chunk_kbytes: max size of chunks in KBs supported per line*/
+	u8 dsc_total_chunk_kbytes;
 };
 
 /**
-- 
2.17.1

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[RFC 10/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon

[Ankit Nautiyal]

This patch adds registers for getting DSC encoder capability for
a HDMI2.1 PCon. It also addes helper functions to configure
DSC between the PCON and HDMI2.1 sink.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c |  93 +++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     | 109 ++++++++++++++++++++++++++++++++
 2 files changed, 202 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 33a4ac2fb225..f10a9c2d6f04 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -2929,3 +2929,96 @@ void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
 	}
 }
 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
+
+static
+int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
+{
+	u8 buf = 0;
+	int ret;
+
+	buf |= DP_PCON_ENABLE_DSC_ENCODER;
+	if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
+		buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
+		buf |= pps_buf_config << 2;
+	}
+
+	ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+/**
+ * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
+ * for DSC1.2 between PCON & HDMI2.1 sink
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns 0 on success, else returns negative error code.
+ * */
+int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
+{
+	int ret;
+
+	ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_pcon_pps_default);
+
+/**
+ * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
+ * HDMI sink
+ * @aux: DisplayPort AUX channel
+ * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
+ *
+ * Returns 0 on success, else returns negative error code.
+ * */
+int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
+{
+	int ret;
+
+	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
+	if (ret < 0)
+		return ret;
+
+	ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
+
+/*
+ * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
+ * override registers
+ * @aux: DisplayPort AUX channel
+ * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
+ * bits_per_pixel.
+ *
+ * Returns 0 on success, else returns negative error code.
+ * */
+int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
+{
+	int ret;
+
+	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
+	if (ret < 0)
+		return ret;
+	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[1], 2);
+	if (ret < 0)
+		return ret;
+	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[2], 2);
+	if (ret < 0)
+		return ret;
+
+	ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index eb26c86dc8ca..3de022d4a65e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -441,6 +441,83 @@ struct drm_device;
 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP    (1 << 2)
 # define DP_FEC_BIT_ERROR_COUNT_CAP	    (1 << 3)
 
+/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
+#define DP_PCON_DSC_ENCODER                 0x092
+# define DP_PCON_DSC_ENCODER_SUPPORTED      (1 << 0)
+# define DP_PCON_DSC_PPS_ENC_OVERRIDE       (1 << 1)
+
+/* DP-HDMI2.1 PCON DSC Version */
+#define DP_PCON_DSC_VERSION                 0x093
+# define DP_PCON_DSC_MAJOR_MASK		    (0xF << 0)
+# define DP_PCON_DSC_MINOR_MASK		    (0xF << 4)
+# define DP_PCON_DSC_MAJOR_SHIFT	    0
+# define DP_PCON_DSC_MINOR_SHIFT	    4
+
+/* DP-HDMI2.1 PCON DSC RC Buffer block size */
+#define DP_PCON_DSC_RC_BUF_BLK_INFO	    0x094
+# define DP_PCON_DSC_RC_BUF_BLK_SIZE	    (0x3 << 0)
+# define DP_PCON_DSC_RC_BUF_BLK_1KB	    0
+# define DP_PCON_DSC_RC_BUF_BLK_4KB	    1
+# define DP_PCON_DSC_RC_BUF_BLK_16KB	    2
+# define DP_PCON_DSC_RC_BUF_BLK_64KB	    3
+
+/* DP-HDMI2.1 PCON DSC RC Buffer size */
+#define DP_PCON_DSC_RC_BUF_SIZE		    0x095
+
+/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
+#define DP_PCON_DSC_SLICE_CAP_1		    0x096
+# define DP_PCON_DSC_1_PER_DSC_ENC     (0x1 << 0)
+# define DP_PCON_DSC_2_PER_DSC_ENC     (0x1 << 1)
+# define DP_PCON_DSC_4_PER_DSC_ENC     (0x1 << 3)
+# define DP_PCON_DSC_6_PER_DSC_ENC     (0x1 << 4)
+# define DP_PCON_DSC_8_PER_DSC_ENC     (0x1 << 5)
+# define DP_PCON_DSC_10_PER_DSC_ENC    (0x1 << 6)
+# define DP_PCON_DSC_12_PER_DSC_ENC    (0x1 << 7)
+
+#define DP_PCON_DSC_BUF_BIT_DEPTH	    0x097
+# define DP_PCON_DSC_BIT_DEPTH_MASK	    (0xF << 0)
+# define DP_PCON_DSC_DEPTH_9_BITS	    0
+# define DP_PCON_DSC_DEPTH_10_BITS	    1
+# define DP_PCON_DSC_DEPTH_11_BITS	    2
+# define DP_PCON_DSC_DEPTH_12_BITS	    3
+# define DP_PCON_DSC_DEPTH_13_BITS	    4
+# define DP_PCON_DSC_DEPTH_14_BITS	    5
+# define DP_PCON_DSC_DEPTH_15_BITS	    6
+# define DP_PCON_DSC_DEPTH_16_BITS	    7
+# define DP_PCON_DSC_DEPTH_8_BITS	    8
+
+#define DP_PCON_DSC_BLOCK_PREDICTION	    0x098
+# define DP_PCON_DSC_BLOCK_PRED_SUPPORT	    (0x1 << 0)
+
+#define DP_PCON_DSC_ENC_COLOR_FMT_CAP	    0x099
+# define DP_PCON_DSC_ENC_RGB		    (0x1 << 0)
+# define DP_PCON_DSC_ENC_YUV444		    (0x1 << 1)
+# define DP_PCON_DSC_ENC_YUV422_S	    (0x1 << 2)
+# define DP_PCON_DSC_ENC_YUV422_N	    (0x1 << 3)
+# define DP_PCON_DSC_ENC_YUV420_N	    (0x1 << 4)
+
+#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP	    0x09A
+# define DP_PCON_DSC_ENC_8BPC		    (0x1 << 0)
+# define DP_PCON_DSC_ENC_10BPC		    (0x1 << 0)
+# define DP_PCON_DSC_ENC_12BPC		    (0x1 << 0)
+
+#define DP_PCON_DSC_MAX_SLICE_WIDTH	    0x09B
+
+/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
+#define DP_PCON_DSC_SLICE_CAP_2             0x09C
+# define DP_PCON_DSC_16_PER_DSC_ENC	    (0x1 << 0)
+# define DP_PCON_DSC_20_PER_DSC_ENC         (0x1 << 1)
+# define DP_PCON_DSC_24_PER_DSC_ENC         (0x1 << 2)
+
+/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
+#define DP_PCON_DSC_BPP_INCR		    0x09E
+# define DP_PCON_DSC_BPP_INCR_MASK	    (0x7 << 0)
+# define DP_PCON_DSC_ONE_16TH_BPP	    0
+# define DP_PCON_DSC_ONE_8TH_BPP	    1
+# define DP_PCON_DSC_ONE_4TH_BPP	    2
+# define DP_PCON_DSC_ONE_HALF_BPP	    3
+# define DP_PCON_DSC_ONE_BPP		    4
+
 /* DP Extended DSC Capabilities */
 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0  0x0a0   /* DP 1.4a SCR */
 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
@@ -1134,6 +1211,12 @@ struct drm_device;
 # define DP_HDMI_FORCE_SCRAMBLING		(1 << 3) /* DP 1.4 */
 #define DP_PROTOCOL_CONVERTER_CONTROL_2		0x3052 /* DP 1.3 */
 # define DP_CONVERSION_TO_YCBCR422_ENABLE	(1 << 0) /* DP 1.3 */
+# define DP_PCON_ENABLE_DSC_ENCODER	        (1 << 1)
+# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK	(0x3 << 2)
+# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED      0
+# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS     1
+# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER     2
+
 
 /* PCON Downstream HDMI ERROR Status per Lane */
 #define DP_PCON_HDMI_ERROR_STATUS_LN0          0x3037
@@ -1145,6 +1228,29 @@ struct drm_device;
 # define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS     (1 << 1)
 # define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
 
+/* PCON HDMI CONFIG PPS Override Buffer
+ * Valid Offsets to be added to Base : 0-127
+ */
+#define DP_PCON_HDMI_PPS_OVERRIDE_BASE        0x3100
+
+/* PCON HDMI CONFIG PPS Override Parameter: Slice height
+ * Offset-0 8LSBs of the Slice height.
+ * Offset-1 8MSBs of the Slice height.
+ */
+#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT    0x3180
+
+/* PCON HDMI CONFIG PPS Override Parameter: Slice width
+ * Offset-0 8LSBs of the Slice width.
+ * Offset-1 8MSBs of the Slice width.
+ */
+#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH    0x3182
+
+/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
+ * Offset-0 8LSBs of the bits_per_pixel.
+ * Offset-1 2MSBs of the bits_per_pixel.
+ */
+#define DP_PCON_HDMI_PPS_OVRD_BPP	     0x3184
+
 /* HDCP 1.3 and HDCP 2.2 */
 #define DP_AUX_HDCP_BKSV		0x68000
 #define DP_AUX_HDCP_RI_PRIME		0x68005
@@ -2063,4 +2169,7 @@ int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, struct drm_connector *connector);
+int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
+int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
+int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
 #endif /* _DRM_DP_HELPER_H_ */
-- 
2.17.1

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[RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder

[Ankit Nautiyal]

This patch adds a helper function to read the DSC capabilities of the
HDMI2.1 PCon encoder. It also adds a new structure to store these caps,
which can then be used to get the PPS parameters for PCON-HDMI2.1 sink
pair. Which inturn will be used to take a call to override the existing
PPS-metadata, by either writing the entire new PPS metadata, or by
writing only the PPS override parameters.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  16 ++
 drivers/gpu/drm/i915/display/intel_dp.c       | 178 ++++++++++++++++++
 2 files changed, 194 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6c69922313d6..23282695a47f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1292,6 +1292,21 @@ struct intel_dp_pcon_frl {
 	int trained_rate_gbps;
 };
 
+struct intel_dp_pcon_dsc {
+	bool enc_support;
+	bool pps_override_support;
+	bool blk_prediction_support;
+	u8 version_major;
+	u8 version_minor;
+	u8 color_fmt_mask;
+	u8 color_depth_mask;
+	u8 max_slices;;
+	u8 max_slice_width;
+	u8 line_buf_bit_depth;
+	u8 bpp_precision_incr;
+	int rc_buf_size;
+};
+
 struct intel_dp {
 	i915_reg_t output_reg;
 	u32 DP;
@@ -1415,6 +1430,7 @@ struct intel_dp {
 	bool hobl_active;
 
 	struct intel_dp_pcon_frl frl;
+	struct intel_dp_pcon_dsc pcon_dsc;
 };
 
 enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e6c4cb844e37..b4f8abaea607 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3882,6 +3882,182 @@ cpt_set_link_train(struct intel_dp *intel_dp,
 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
 }
 
+void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
+{
+	u8 buf;
+	u8 rc_buf_blk_size;
+	u8 max_slices = 0;
+
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct intel_dp_pcon_dsc *pcon_dsc = &intel_dp->pcon_dsc;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENCODER, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_ENCODER\n");
+		return;
+	}
+	pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED;
+	pcon_dsc->pps_override_support = buf & DP_PCON_DSC_PPS_ENC_OVERRIDE;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_VERSION, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_VERSION\n");
+		return;
+	}
+	pcon_dsc->version_major = (buf & DP_PCON_DSC_MAJOR_MASK) >>
+				  DP_PCON_DSC_MAJOR_SHIFT;
+	pcon_dsc->version_minor = (buf & DP_PCON_DSC_MINOR_MASK) >>
+				  DP_PCON_DSC_MINOR_SHIFT;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_RC_BUF_BLK_INFO, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_RC_BUF_BLK_INFO\n");
+		return;
+	}
+
+	switch (buf & DP_PCON_DSC_RC_BUF_BLK_SIZE) {
+	case DP_PCON_DSC_RC_BUF_BLK_1KB :
+		rc_buf_blk_size = 1;
+		break;
+	case DP_PCON_DSC_RC_BUF_BLK_4KB :
+		rc_buf_blk_size = 4;
+		break;
+	case DP_PCON_DSC_RC_BUF_BLK_16KB :
+		rc_buf_blk_size = 16;
+		break;
+	case DP_PCON_DSC_RC_BUF_BLK_64KB :
+		rc_buf_blk_size = 64;
+		break;
+	default :
+		rc_buf_blk_size = 0;
+	}
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_RC_BUF_SIZE, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_RC_BUF_SIZE\n");
+		return;
+	}
+	/* storing rc_buf_size in bytes */
+	pcon_dsc->rc_buf_size = (buf + 1) * rc_buf_blk_size * 1024;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_SLICE_CAP_2, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_SLICE_CAP_2\n");
+		return;
+	}
+	if (buf & DP_PCON_DSC_24_PER_DSC_ENC)
+	       max_slices = 24;
+	else if (buf & DP_PCON_DSC_20_PER_DSC_ENC)
+		max_slices = 20;
+	else if (buf & DP_PCON_DSC_16_PER_DSC_ENC)
+		max_slices = 16;
+
+	if (max_slices == 0) {
+		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_SLICE_CAP_1,
+				      &buf) < 0) {
+			drm_err(&i915->drm, "Failed to read DP_PCON_DSC_SLICE_CAP_2\n");
+			return;
+		}
+
+		if (buf & DP_PCON_DSC_12_PER_DSC_ENC)
+			max_slices = 12;
+		else if (buf & DP_PCON_DSC_10_PER_DSC_ENC)
+			max_slices = 10;
+		else if (buf & DP_PCON_DSC_8_PER_DSC_ENC)
+			max_slices = 8;
+		else if (buf & DP_PCON_DSC_6_PER_DSC_ENC)
+			max_slices = 6;
+		else if (buf & DP_PCON_DSC_4_PER_DSC_ENC)
+			max_slices = 4;
+		else if (buf & DP_PCON_DSC_2_PER_DSC_ENC)
+			max_slices = 2;
+		else if (buf & DP_PCON_DSC_1_PER_DSC_ENC)
+			max_slices = 1;
+	}
+
+	pcon_dsc->max_slices = max_slices;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BUF_BIT_DEPTH, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_BUF_BIT_DEPTH\n");
+		return;
+	}
+	switch (buf & DP_PCON_DSC_BIT_DEPTH_MASK) {
+	case DP_PCON_DSC_DEPTH_8_BITS :
+		pcon_dsc->line_buf_bit_depth = 8;
+		break;
+	case DP_PCON_DSC_DEPTH_9_BITS :
+		pcon_dsc->line_buf_bit_depth = 9;
+		break;
+	case DP_PCON_DSC_DEPTH_10_BITS :
+		pcon_dsc->line_buf_bit_depth = 10;
+		break;
+	case DP_PCON_DSC_DEPTH_11_BITS :
+		pcon_dsc->line_buf_bit_depth = 11;
+		break;
+	case DP_PCON_DSC_DEPTH_12_BITS :
+		pcon_dsc->line_buf_bit_depth = 12;
+		break;
+	case DP_PCON_DSC_DEPTH_13_BITS :
+		pcon_dsc->line_buf_bit_depth = 13;
+		break;
+	case DP_PCON_DSC_DEPTH_14_BITS :
+		pcon_dsc->line_buf_bit_depth = 14;
+		break;
+	case DP_PCON_DSC_DEPTH_15_BITS :
+		pcon_dsc->line_buf_bit_depth = 15;
+		break;
+	case DP_PCON_DSC_DEPTH_16_BITS :
+		pcon_dsc->line_buf_bit_depth = 16;
+		break;
+	default :
+		pcon_dsc->line_buf_bit_depth = 0;
+	}
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BLOCK_PREDICTION, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_BLOCK_PREDICTION\n");
+		return;
+	}
+	if (buf && DP_PCON_DSC_BLOCK_PRED_SUPPORT)
+		pcon_dsc->blk_prediction_support = true;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENC_COLOR_FMT_CAP, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_ENC_COLOR_FMT_CAP\n");
+		return;
+	}
+	pcon_dsc->color_fmt_mask = buf;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENC_COLOR_DEPTH_CAP, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_ENC_COLOR_DEPTH_CAP\n");
+		return;
+	}
+	pcon_dsc->color_depth_mask = buf;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_MAX_SLICE_WIDTH, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_MAX_SLICE_WIDTH\n");
+		return;
+	}
+	pcon_dsc->max_slice_width = buf;;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BPP_INCR, &buf) < 0) {
+		drm_err(&i915->drm, "Failed to read DP_PCON_DSC_BPP_INCR\n");
+		return;
+	}
+	switch(buf & DP_PCON_DSC_BPP_INCR_MASK) {
+	case DP_PCON_DSC_ONE_16TH_BPP:
+		pcon_dsc->bpp_precision_incr = 16;
+		break;
+	case DP_PCON_DSC_ONE_8TH_BPP:
+		pcon_dsc->bpp_precision_incr = 8;
+		break;
+	case DP_PCON_DSC_ONE_4TH_BPP:
+		pcon_dsc->bpp_precision_incr = 4;
+		break;
+	case DP_PCON_DSC_ONE_HALF_BPP:
+		pcon_dsc->bpp_precision_incr = 2;
+		break;
+	case DP_PCON_DSC_ONE_BPP:
+		pcon_dsc->bpp_precision_incr = 1;
+		break;
+	default :
+		pcon_dsc->bpp_precision_incr = 0;
+	}
+}
+
 static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp)
 {
 	int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps;
@@ -6659,6 +6835,8 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
 		    intel_dp->dfp.max_tmds_clock,
 		    intel_dp->dfp.pcon_max_frl,
 		    intel_dp->dfp.sink_max_frl);
+
+	intel_dp_get_pcon_dsc_cap(intel_dp);
 }
 
 static void
-- 
2.17.1

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[RFC 12/13] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1

[Ankit Nautiyal]

The DP-HDMI2.1 PCON spec provides way for a source to set PPS
parameters: slice height, slice width and bits_per_pixel, based on
the HDMI2.1 sink capabilities. The DSC encoder of the PCON will
respect these parameters, while preparing the 128 byte PPS.

This patch adds helper functions to calculate these PPS paremeters as
per the HDMI2.1 specification.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 171 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |   7 +
 2 files changed, 178 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..3c1df2c78438 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3438,3 +3438,174 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv,
 	dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
 	intel_hdmi_init_connector(dig_port, intel_connector);
 }
+
+int intel_hdmi_dsc_get_slice_height(int vactive)
+{
+	int slice_height;
+
+	/*
+	 * Slice Height determination : HDMI2.1 Section 7.7.5.2
+	 * Select smallest slice height >=96, that results in a valid PPS and
+	 * requires minimum padding lines required for final slice.
+	 *
+	 * Assumption : Vactive is even.
+	 */
+	for (slice_height = 96; slice_height <= vactive; slice_height+=2)
+		if (vactive % slice_height == 0)
+			return slice_height;
+
+	return 0;
+}
+
+int
+intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
+			      int src_max_slices, int src_max_slice_width,
+			      int hdmi_max_slices, int hdmi_throughput)
+{
+/* Pixel rates in KPixels/sec */
+#define HDMI_DSC_PEAK_PIXEL_RATE		2720000
+#define HDMI_DSC_MAX_ENC_THROUGHPUT_0		340000
+#define HDMI_DSC_MAX_ENC_THROUGHPUT_1		400000
+#define MAX_HDMI_SLICE_WIDTH			2720
+	int kslice_adjust;
+	int adjusted_clk_khz;
+	int min_slices;
+	int target_slices;
+	int max_throughput; //max clock freq. in khz per slice
+	int max_slice_width;
+	int slice_width;
+	int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
+
+	/*
+	 * Slice Width determination : HDMI2.1 Section 7.7.5.1
+	 * kslice_adjust factor for 4:2:0 formats is 0.5, where as
+	 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
+	 * dividing adjusted clock value by 10.
+	 */
+	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		kslice_adjust = 5;
+	else
+		kslice_adjust = 10;
+
+	adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
+
+	if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
+		max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
+	else
+		max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
+
+	/*
+	 * Taking into account the sink's capability for maximum
+	 * clock per slice (in MHz) as read from HF-VSDB.
+	 */
+	max_throughput = min(max_throughput, hdmi_throughput * 1000);
+
+	min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
+	max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
+
+	/*
+	 * Keep on increasing the num of slices/line, starting from min_slices
+	 * per line till we get such a number, for which the slice_width is
+	 * just less than max_slice_width. The slices/line selected should be
+	 * less than or equal to the max horizontal slices that the combination
+	 * of PCON encoder and HDMI decoder can support.
+	 */
+	slice_width = max_slice_width;
+
+	while (slice_width >= max_slice_width) {
+		if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
+		       target_slices = 1;
+		else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
+		       target_slices = 2;
+		else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
+		       target_slices = 4;
+		else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
+		       target_slices = 8;
+		else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
+		       target_slices = 12;
+		else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
+		       target_slices = 16;
+		else
+			return 0;
+
+		slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
+	}
+
+	return target_slices;
+}
+
+int
+intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
+		       int output_format, bool hdmi_all_bpp,
+		       int hdmi_max_chunk_bytes)
+{
+	int max_dsc_bpp, min_dsc_bpp;
+	int target_bytes;
+	bool bpp_found = false;
+	int bpp_decrement_x16;
+	int bpp_target;
+	int bpp_target_x16;
+
+	/*
+	 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
+	 * Start with the max bpp and keep on decrementing with
+	 * fractional bpp, if supported by PCON DSC encoder
+	 *
+	 * for each bpp we check if no of bytes can be supported by HDMI sink
+	 */
+
+	/* Assuming: bpc as 8*/
+	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+		min_dsc_bpp = 6;
+		max_dsc_bpp = 3 * 4; // 3 * bpc / 2
+	} else {
+		min_dsc_bpp = 8;
+		max_dsc_bpp = 3 * 8; // 3 * bpc
+	}
+
+	/*
+	 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
+	 * Section 7.7.34 : Source shall not enable compressed Video
+	 * Transport with bpp_target settings above 12 bpp unless
+	 * DSC_all_bpp is set to 1.
+	 */
+	if (!hdmi_all_bpp)
+		max_dsc_bpp = min(max_dsc_bpp, 12);
+
+	/*
+	 * The Sink has a limit of compressed data in bytes for a scanline,
+	 * as described in max_chunk_bytes field in HFVSDB block of edid.
+	 * The no. of bytes depend on the target bits per pixel that the
+	 * source configures. So we start with the max_bpp and calculate
+	 * the target_chunk_bytes. We keep on decrementing the target_bpp,
+	 * till we get the target_chunk_bytes just less than what the sink's
+	 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
+	 *
+	 * The decrement is according to the fractional support from PCON DSC
+	 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
+	 *
+	 * bpp_target_x16 = bpp_target * 16
+	 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
+	 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
+	 */
+
+	bpp_target = max_dsc_bpp;
+	bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
+	bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
+
+	while (bpp_target_x16 > (min_dsc_bpp * 16)) {
+		int bpp;
+
+		bpp = DIV_ROUND_UP(bpp_target_x16, 16);
+		target_bytes = num_slices * slice_width * DIV_ROUND_UP(bpp, 8);
+		if (target_bytes <= hdmi_max_chunk_bytes) {
+			bpp_found = true;
+			break;
+		}
+		bpp_target_x16 -= bpp_decrement_x16;
+	}
+	if (bpp_found)
+		return bpp_target_x16;
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 15eb0ccde76e..fa1a9b030850 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -50,5 +50,12 @@ bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state);
 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, int bpc,
 				    bool has_hdmi_sink, bool ycbcr420_output);
+int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
+			   int num_slices, int output_format, bool hdmi_all_bpp,
+			   int hdmi_max_chunk_bytes);
+int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
+				  int src_max_slices, int src_max_slice_width,
+				  int hdmi_max_slices, int hdmi_throughput);
+int intel_hdmi_dsc_get_slice_height(int vactive);
 
 #endif /* __INTEL_HDMI_H__ */
-- 
2.17.1

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[RFC 13/13] drm/i915: Configure PCON for DSC1.1 to DSC1.2 encoding

[Ankit Nautiyal]

When a source supporting DSC1.1 is connected to DSC1.2 HDMI2.1 sink
via DP HDMI2.1 PCON, the PCON can be configured to decode the
DSC1.1 compressed stream and encode to DSC1.2. It then sends the
DSC1.2 compressed stream to the HDMI2.1 sink.

This patch configures the PCON for DSC1.1 to DSC1.2 encoding, based
on the PCON's DSC encoder capablities and HDMI2.1 sink's DSC decoder
capabilities.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |   2 +-
 drivers/gpu/drm/i915/display/intel_dp.c  | 120 ++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h  |   2 +
 3 files changed, 121 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1834e5de60a7..f8fc2de7ad95 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3485,7 +3485,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 
 	intel_dp_check_frl_training(intel_dp);
-
+	intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
 	/*
 	 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b4f8abaea607..2c7f6d04085e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -782,6 +782,16 @@ intel_dp_mode_valid(struct drm_connector *connector,
 							     target_clock,
 							     mode->hdisplay);
 		}
+
+		/*
+		 * TODO: If its a PCON with HDMI sink:
+		 * Assumption : Source only supports DSC1.1
+		 *
+		 * If HDMI supports DSC 1.2 but PCON does not support
+		 * DSC1.1->DSC1.2 encoding Then return MODE_CLOCK_HIGH.
+		 * Otherwise check if the mode can be applied according to
+		 * DSC capablities of the PCON and HDMI Sink combine.
+		 */
 	}
 
 	if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
@@ -4116,9 +4126,21 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
 {
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	struct drm_connector *connector = &intel_connector->base;
+	int max_frl_rate;
+	int max_lanes, rate_per_lane;
+	int max_dsc_lanes, dsc_rate_per_lane;
+
+	max_lanes = connector->display_info.hdmi.max_lanes;
+	rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
+	max_frl_rate = max_lanes * rate_per_lane;
+
+	if (connector->display_info.hdmi.dsc_1p2) {
+		max_dsc_lanes = connector->display_info.hdmi.dsc_max_lanes;
+		dsc_rate_per_lane = connector->display_info.hdmi.dsc_max_frl_rate_per_lane;
+		max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
+	}
 
-	return (connector->display_info.hdmi.max_frl_rate_per_lane *
-		connector->display_info.hdmi.max_lanes);
+	return max_frl_rate;
 }
 
 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
@@ -4252,6 +4274,98 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp)
 		drm_dbg(&dev_priv->drm, "FRL training Completed\n");
 }
 
+static int
+intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
+{
+
+	int vactive = crtc_state->hw.adjusted_mode.vdisplay;
+
+	return intel_hdmi_dsc_get_slice_height(vactive);
+}
+
+static int
+intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
+			     const struct intel_crtc_state *crtc_state)
+{
+	struct intel_connector *intel_connector = intel_dp->attached_connector;
+	struct drm_connector *connector = &intel_connector->base;
+	int hdmi_throughput = connector->display_info.hdmi.dsc_clk_per_slice;
+	int hdmi_max_slices = connector->display_info.hdmi.dsc_max_slices;
+	int pcon_max_slices = intel_dp->pcon_dsc.max_slices;
+	int pcon_max_slice_width = intel_dp->pcon_dsc.max_slice_width;
+
+
+	return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
+					     pcon_max_slice_width,
+					     hdmi_max_slices, hdmi_throughput);
+}
+
+static int
+intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
+			  const struct intel_crtc_state *crtc_state,
+			  int num_slices, int slice_width)
+{
+	struct intel_connector *intel_connector = intel_dp->attached_connector;
+	struct drm_connector *connector = &intel_connector->base;
+	int output_format = crtc_state->output_format;
+	bool hdmi_all_bpp = connector->display_info.hdmi.dsc_all_bpp;
+	int pcon_fractional_bpp = intel_dp->pcon_dsc.bpp_precision_incr;
+	int hdmi_max_chunk_bytes =
+		connector->display_info.hdmi.dsc_total_chunk_kbytes * 1024;
+
+	return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
+				      num_slices, output_format, hdmi_all_bpp,
+				      hdmi_max_chunk_bytes);
+}
+
+void
+intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
+			    const struct intel_crtc_state *crtc_state)
+{
+	u8 pps_param[6];
+	int slice_height;
+	int slice_width;
+	int num_slices;
+	int bits_per_pixel;
+	int ret;
+	struct intel_connector *intel_connector = intel_dp->attached_connector;
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct drm_connector *connector = &intel_connector->base;
+	bool hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_1p2;
+
+	/* If DSC Not required, return */
+
+	if (!hdmi_is_dsc_1_2)
+		return;
+
+	slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
+	if (!slice_height)
+		return;
+
+	num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
+	if (!num_slices)
+		return;
+
+	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
+				   num_slices);
+
+	bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
+						  num_slices, slice_width);
+	if (!bits_per_pixel)
+		return;
+
+	pps_param[0] = slice_height >> 8;
+	pps_param[1] = slice_height & 0xFF;
+	pps_param[2] = slice_width >> 8;
+	pps_param[3] = slice_width & 0xFF;
+	pps_param[4] = bits_per_pixel >> 8;
+	pps_param[5] = bits_per_pixel & 0xFF;
+
+	ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
+	if (ret < 0)
+		drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
+}
+
 static void
 g4x_set_link_train(struct intel_dp *intel_dp,
 		   const struct intel_crtc_state *crtc_state,
@@ -4383,6 +4497,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_configure_protocol_converter(intel_dp);
 	intel_dp_check_frl_training(intel_dp);
+	intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
 	intel_dp_start_link_train(intel_dp, pipe_config);
 	intel_dp_stop_link_train(intel_dp, pipe_config);
 
@@ -6328,6 +6443,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
 			continue;
 
 		intel_dp_check_frl_training(intel_dp);
+		intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
 		intel_dp_start_link_train(intel_dp, crtc_state);
 		intel_dp_stop_link_train(intel_dp, crtc_state);
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 81d83d88cd41..2f377334b17d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -144,5 +144,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state);
 
 void intel_dp_check_frl_training(struct intel_dp *intel_dp);
+void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.17.1

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RE: [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1
> 
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> The HDMI2.1 extends HFVSBD (HDMI Forum Vendor Specific Data block) to have

Typo in HFVSDB

> fields related to newly defined methods of FRL (Fixed Rate Link) levels, number
> of lanes supported, DSC Color bit depth, VRR min/max, FVA (Fast Vactive), ALLM
> etc.
> 
> This patch adds the new HFVSDB fields that are required for HDMI2.1.
> 
> Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index
> b27a0e2169c8..1cc5c2c73282 100644
> --- a/include/drm/drm_edid.h
> +++ b/include/drm/drm_edid.h
> @@ -229,6 +229,36 @@ struct detailed_timing {
>  				    DRM_EDID_YCBCR420_DC_36 | \
>  				    DRM_EDID_YCBCR420_DC_30)
> 
> +/* HDMI 2.1 additional fields */
> +#define DRM_EDID_MAX_FRL_RATE_MASK		0xf0
> +#define DRM_EDID_FAPA_START_LOCATION		(1 << 0)
> +#define DRM_EDID_ALLM				(1 << 1)
> +#define DRM_EDID_FVA				(1 << 2)
> +
> +/* Deep Color specific */
> +#define DRM_EDID_DC_30BIT_420			(1 << 0)
> +#define DRM_EDID_DC_36BIT_420			(1 << 1)
> +#define DRM_EDID_DC_48BIT_420			(1 << 2)
> +
> +/* VRR specific */
> +#define DRM_EDID_CNMVRR				(1 << 3)
> +#define DRM_EDID_CINEMA_VRR			(1 << 4)
> +#define DRM_EDID_MDELTA				(1 << 5)
> +#define DRM_EDID_VRR_MAX_UPPER_MASK		0xc0
> +#define DRM_EDID_VRR_MAX_LOWER_MASK		0xff
> +#define DRM_EDID_VRR_MIN_MASK			0x3f
> +
> +/* DSC specific */
> +#define DRM_EDID_DSC_10BPC			(1 << 0)
> +#define DRM_EDID_DSC_12BPC			(1 << 1)
> +#define DRM_EDID_DSC_16BPC			(1 << 2)
> +#define DRM_EDID_DSC_ALL_BPP			(1 << 3)
> +#define DRM_EDID_DSC_NATIVE_420			(1 << 6)
> +#define DRM_EDID_DSC_1P2			(1 << 7)
> +#define DRM_EDID_DSC_MAX_FRL_RATE		0xf

This should be set as mask and made it as 0xf0

> +#define DRM_EDID_DSC_MAX_SLICES			0xf
> +#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES		0x3f
> +
>  /* ELD Header Block */
>  #define DRM_ELD_HEADER_BLOCK_SIZE	4
> 
> --
> 2.17.1

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RE: [RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block
> 
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> This patch parses MAX_FRL field to get the MAX rate in Gbps that the HDMI 2.1
> panel can support in FRL mode. Source need this field to determine the optimal
> rate between the source and sink during FRL training.
> 
> Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c  | 51 +++++++++++++++++++++++++++++++++++++
>  include/drm/drm_connector.h |  6 +++++
>  2 files changed, 57 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 631125b46e04..8afb136e73f5 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4849,6 +4849,52 @@ static void drm_parse_vcdb(struct drm_connector
> *connector, const u8 *db)
>  		info->rgb_quant_range_selectable = true;  }
> 
> +static
> +void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8
> +*max_rate_per_lane) {
> +	switch(max_frl_rate) {
> +	case 1:
> +		*max_lanes = 3;
> +		*max_rate_per_lane = 3;
> +		break;
> +	case 2:
> +		*max_lanes = 3;
> +		*max_rate_per_lane = 6;
> +		break;
> +	case 3:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 6;
> +		break;
> +	case 4:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 8;
> +		break;
> +	case 5:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 10;
> +		break;
> +	case 6:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 12;
> +		break;
> +	case 0:
> +	default:
> +		*max_lanes = 0;
> +		*max_rate_per_lane = 0;
> +	}
> +}
> +
> +static void drm_parse_hdmi_21_additional_fields(struct drm_connector
> *connector,
> +						const u8 *db)
> +{
> +	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
> +	u8 max_frl_rate;
> +
> +	max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;

This seems wrong,  we need to right shift this by 4 to get the max_frl_rate.

> +	drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
> +			     &hdmi->max_frl_rate_per_lane);

We can just pass the connecter and drm_get_max_frl_rate can fill the respective fields.

> +}
> +
>  static void drm_parse_ycbcr420_deep_color_info(struct drm_connector
> *connector,
>  					       const u8 *db)
>  {
> @@ -4902,6 +4948,11 @@ static void drm_parse_hdmi_forum_vsdb(struct
> drm_connector *connector,
>  		}
>  	}
> 
> +	if (hf_vsdb[7]) {
> +		    DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
> +		    drm_parse_hdmi_21_additional_fields(connector, hf_vsdb);

We can get rid of this extra wrapper.

> +	}
> +
>  	drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);  }
> 
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index
> 928136556174..f351bf10c076 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -207,6 +207,12 @@ struct drm_hdmi_info {
> 
>  	/** @y420_dc_modes: bitmap of deep color support index */
>  	u8 y420_dc_modes;
> +
> +	/** @max_frl_rate_per_lane: support fixed rate link */
> +	u8 max_frl_rate_per_lane;
> +
> +	/** @max_lanes: supported by sink */
> +	u8 max_lanes;
>  };
> 
>  /**
> --
> 2.17.1

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RE: [RFC 03/13] drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 03/13] drm/dp_helper: Add FRL training support for a DP-HDMI2.1
> PCON

You can name this patch as "Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON"

> This patch adds support for configuring a PCON device, connected as a DP
> branched device to enable FRL Link training with a HDMI2.1 + sink.
> 
> v2: Minor changes:
> -removed unnecessary argument supplied to a drm helper function.
> -fixed return value for max frl read from pcon.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 305 ++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     |  80 +++++++++
>  2 files changed, 385 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c index 14ddf28ecac0..df858533dbf7 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -2591,3 +2591,308 @@ void drm_dp_vsc_sdp_log(const char *level, struct
> device *dev,  #undef DP_SDP_LOG  }  EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
> +
> +/**
> + * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
> + * @dpcd: DisplayPort configuration data
> + * @port_cap: port capabilities
> + *
> + * Returns maximum frl bandwidth supported by PCON in GBPS,
> + * returns 0 if not supported.
> + **/
> +int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +			       const u8 port_cap[4])
> +{
> +	int bw;
> +	u8 buf;
> +
> +	buf = port_cap[2];
> +	bw = buf & DP_PCON_MAX_FRL_BW;
> +
> +	switch (bw) {
> +	case DP_PCON_MAX_9GBPS:
> +		return 9;
> +	case DP_PCON_MAX_18GBPS:
> +		return 18;
> +	case DP_PCON_MAX_24GBPS:
> +		return 24;
> +	case DP_PCON_MAX_32GBPS:
> +		return 32;
> +	case DP_PCON_MAX_40GBPS:
> +		return 40;
> +	case DP_PCON_MAX_48GBPS:
> +		return 48;
> +	case DP_PCON_MAX_0GBPS:
> +	default:
> +		return 0;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
> +
> +/**
> + * drm_dp_get_hdmi_max_frl_bw() - maximum frl supported by HDMI Sink
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns maximum frl bandwidth supported by HDMI in Gbps on success,
> + * returns 0, if not supported.
> + **/
> +int drm_dp_get_hdmi_max_frl_bw(struct drm_dp_aux *aux) {

s/hdmi/hdmi_sink/ will make it clear that we are referring to sink here.

> +	u8 buf;
> +	int bw, ret;
> +
> +	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_SINK, &buf);
> +	if (ret < 0)
> +		return 0;
> +	bw = buf & DP_HDMI_SINK_LINK_BW;
> +
> +	switch (bw) {
> +	case DP_HDMI_SINK_BW_9GBPS:
> +		return 9;
> +	case DP_HDMI_SINK_BW_18GBPS:
> +		return 18;
> +	case DP_HDMI_SINK_BW_24GBPS:
> +		return 24;
> +	case DP_HDMI_SINK_BW_32GBPS:
> +		return 32;
> +	case DP_HDMI_SINK_BW_40GBPS:
> +		return 40;
> +	case DP_HDMI_SINK_BW_48GBPS:
> +		return 48;
> +	case DP_HDMI_SINK_BW_0GBPS:
> +	default:
> +		return 0;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_get_hdmi_max_frl_bw);
> +
> +/**
> + * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns 0 if success, else returns negative error code.
> + **/
> +int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool
> +enable_frl_ready_hpd) {
> +	int ret;
> +	u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
> +		 DP_PCON_ENABLE_LINK_FRL_MODE;
> +
> +	if (enable_frl_ready_hpd)
> +		buf |= DP_PCON_ENABLE_HPD_READY;
> +
> +	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
> +
> +/**
> + * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns true if success, else returns false.
> + **/
> +bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) {
> +	int ret;
> +	u8 buf;
> +
> +	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
> +	if (ret < 0)
> +		return false;
> +
> +	if (buf & DP_PCON_FRL_READY)
> +		return true;
> +
> +	return false;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
> +
> +/**
> + * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
> + * @aux: DisplayPort AUX channel
> + * max_frl_mask: mask for selecting the bandwidths supported by source,

@missing from variable and its not a mask here but an absolute value.

> + * to be tried by Pcon f/w.
> + * @concurrent_mode: true if concurrent mode or operation is required,
> + * false otherwise.
> + *
> + * Returns 0 if success, else returns negative error code.
> + **/
> +
> +int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
> +				bool concurrent_mode)
> +{
> +	int ret;
> +	u8 buf;
> +
> +	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
> +	if (ret < 0)
> +		return ret;
> +
> +	if (concurrent_mode)
> +		buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
> +	else
> +		buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
> +
> +	switch (max_frl_gbps) {
> +	case 9:
> +		buf |=  DP_PCON_ENABLE_MAX_BW_9GBPS;
> +		break;
> +	case 18:
> +		buf |=  DP_PCON_ENABLE_MAX_BW_18GBPS;
> +		break;
> +	case 24:
> +		buf |=  DP_PCON_ENABLE_MAX_BW_24GBPS;
> +		break;
> +	case 32:
> +		buf |=  DP_PCON_ENABLE_MAX_BW_32GBPS;
> +		break;
> +	case 40:
> +		buf |=  DP_PCON_ENABLE_MAX_BW_40GBPS;
> +		break;
> +	case 48:
> +		buf |=  DP_PCON_ENABLE_MAX_BW_48GBPS;
> +		break;
> +	case 0:
> +		buf |=  DP_PCON_ENABLE_MAX_BW_0GBPS;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
> +
> +/**
> + * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
> + * @aux: DisplayPort AUX channel
> + * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
> + * @extended_train_mode : true for Extended Mode, false for Normal Mode.
> + * In Normal mode, the PCON tries each frl bw from the max_frl_mask
> +starting
> + * from min, and stops when link training is successful. In Extended
> +mode, all
> + * frl bw selected in the mask are trained by the PCON.
> + *
> + * Returns 0 if success, else returns negative error code.
> + **/
> +int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
> +				bool extended_train_mode)
> +{
> +	int ret;
> +	u8 buf = 0;
> +
> +	buf |= max_frl_mask;

Can just initialize buf to max _frl_mask.

> +
> +	if (extended_train_mode)
> +		buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
> +
> +	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
> +
> +/**
> + * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns 0 if success, else returns negative error code.
> + **/
> +int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) {
> +	int ret;
> +
> +	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
> +
> +/**
> + * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns 0 if success, else returns negative error code.
> + **/
> +int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) {
> +	int ret;
> +	u8 buf = 0;
> +
> +	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
> +	if (ret < 0)
> +		return ret;
> +	if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
> +		DRM_DEBUG_KMS("PCON in Autonomous mode, can't enable
> FRL\n");
> +		return -EINVAL;
> +	}
> +	buf |= DP_PCON_ENABLE_HDMI_LINK;
> +	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
> +
> +/**
> + * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is
> active.
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns true if link is active else returns false.
> + **/
> +bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) {
> +	u8 buf;
> +	int ret;
> +
> +	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
> +	if (ret < 0)
> +		return false;
> +
> +	return buf & DP_PCON_HDMI_TX_LINK_ACTIVE; }
> +EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
> +
> +/**
> + * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
> + * @aux: DisplayPort AUX channel
> + * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
> + * Valid only if the MODE returned is FRL. For Normal Link training
> +mode
> + * only 1 of the bits will be set, but in case of Extended mode, more
> +than
> + * one bits can be set.
> + *
> + * Returns the link mode : TMDS or FRL on success, else retunes

Typo in returns

> +negative error
> + * code.
> + **/
> +int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8
> +*frl_trained_mask) {
> +	u8 buf;
> +	int mode;
> +	int ret;
> +
> +	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS,
> &buf);
> +	if (ret < 0)
> +		return ret;
> +
> +	mode = buf & DP_PCON_HDMI_LINK_MODE;
> +
> +	if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)

Should be bitwise and not logical and right ?. Also this mask is a bit ambigious,
we could just use absolute bandwidth which would be more clear.

> +		*frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW)
> >> 1;
> +
> +	return mode;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> f55a9d1320ca..d6f79b2d1287 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -411,6 +411,17 @@ struct drm_device;
>  # define DP_DS_10BPC		            1
>  # define DP_DS_12BPC		            2
>  # define DP_DS_16BPC		            3
> +/* HDMI2.1 PCON FRL CONFIGURATION */
> +# define DP_PCON_MAX_FRL_BW                 (7 << 2)
> +# define DP_PCON_MAX_0GBPS                  (0 << 2)
> +# define DP_PCON_MAX_9GBPS                  (1 << 2)
> +# define DP_PCON_MAX_18GBPS                 (2 << 2)
> +# define DP_PCON_MAX_24GBPS                 (3 << 2)
> +# define DP_PCON_MAX_32GBPS                 (4 << 2)
> +# define DP_PCON_MAX_40GBPS                 (5 << 2)
> +# define DP_PCON_MAX_48GBPS                 (6 << 2)
> +# define DP_PCON_SOURCE_CTL_MODE            (1 << 5)
> +
>  /* offset 3 for DVI */
>  # define DP_DS_DVI_DUAL_LINK		    (1 << 1)
>  # define DP_DS_DVI_HIGH_COLOR_DEPTH	    (1 << 2)
> @@ -1053,6 +1064,61 @@ struct drm_device;
>  #define DP_CEC_RX_MESSAGE_BUFFER               0x3010
>  #define DP_CEC_TX_MESSAGE_BUFFER               0x3020
>  #define DP_CEC_MESSAGE_BUFFER_LENGTH             0x10
> +/* PROTOCOL CONVERSION HDMI SINK */
> +#define DP_PCON_HDMI_SINK                      0x3035
> +# define DP_HDMI_SINK_LINK_BW                  (7 << 0)
> +# define DP_HDMI_SINK_BW_0GBPS		       0
> +# define DP_HDMI_SINK_BW_9GBPS		       1
> +# define DP_HDMI_SINK_BW_18GBPS		       2
> +# define DP_HDMI_SINK_BW_24GBPS		       3
> +# define DP_HDMI_SINK_BW_32GBPS		       4
> +# define DP_HDMI_SINK_BW_40GBPS		       5
> +# define DP_HDMI_SINK_BW_48GBPS		       6
> +
> +/* PCON CONFIGURE-1 FRL FOR HDMI SINK */
> +#define DP_PCON_HDMI_LINK_CONFIG_1             0x305A
> +# define DP_PCON_ENABLE_MAX_FRL_BW             (7 << 0)
> +# define DP_PCON_ENABLE_MAX_BW_0GBPS	       0
> +# define DP_PCON_ENABLE_MAX_BW_9GBPS	       1
> +# define DP_PCON_ENABLE_MAX_BW_18GBPS	       2
> +# define DP_PCON_ENABLE_MAX_BW_24GBPS	       3
> +# define DP_PCON_ENABLE_MAX_BW_32GBPS	       4
> +# define DP_PCON_ENABLE_MAX_BW_40GBPS	       5
> +# define DP_PCON_ENABLE_MAX_BW_48GBPS	       6
> +# define DP_PCON_ENABLE_SOURCE_CTL_MODE       (1 << 3)
> +# define DP_PCON_ENABLE_CONCURRENT_LINK       (1 << 4)
> +# define DP_PCON_ENABLE_LINK_FRL_MODE         (1 << 5)
> +# define DP_PCON_ENABLE_HPD_READY	      (1 << 6)
> +# define DP_PCON_ENABLE_HDMI_LINK             (1 << 7)
> +
> +/* PCON CONFIGURE-2 FRL FOR HDMI SINK */
> +#define DP_PCON_HDMI_LINK_CONFIG_2            0x305B
> +# define DP_PCON_MAX_LINK_BW_MASK             (0x3F << 0)
> +# define DP_PCON_FRL_BW_MASK_9GBPS            (1 << 0)
> +# define DP_PCON_FRL_BW_MASK_18GBPS           (1 << 1)
> +# define DP_PCON_FRL_BW_MASK_24GBPS           (1 << 2)
> +# define DP_PCON_FRL_BW_MASK_32GBPS           (1 << 3)
> +# define DP_PCON_FRL_BW_MASK_40GBPS           (1 << 4)
> +# define DP_PCON_FRL_BW_MASK_48GBPS           (1 << 5)
> +# define DP_PCON_FRL_LINK_TRAIN_EXTENDED      (1 << 6)
> +
> +/* PCON HDMI LINK STATUS */
> +#define DP_PCON_HDMI_TX_LINK_STATUS           0x303B
> +# define DP_PCON_HDMI_TX_LINK_ACTIVE          (1 << 0)
> +# define DP_PCON_FRL_READY		      (1 << 1)
> +
> +/* PCON HDMI POST FRL STATUS */
> +#define DP_PCON_HDMI_POST_FRL_STATUS          0x3036
> +# define DP_PCON_HDMI_LINK_MODE               (1 << 0)
> +# define DP_PCON_HDMI_MODE_TMDS               0
> +# define DP_PCON_HDMI_MODE_FRL                1
> +# define DP_PCON_HDMI_FRL_TRAINED_BW          (0x3F << 1)

This should be 0x3 < 1

> +# define DP_PCON_FRL_TRAINED_BW_9GBPS	      (1 << 1)
> +# define DP_PCON_FRL_TRAINED_BW_18GBPS	      (1 << 2)
> +# define DP_PCON_FRL_TRAINED_BW_24GBPS	      (1 << 3)
> +# define DP_PCON_FRL_TRAINED_BW_32GBPS	      (1 << 4)
> +# define DP_PCON_FRL_TRAINED_BW_40GBPS	      (1 << 5)
> +# define DP_PCON_FRL_TRAINED_BW_48GBPS	      (1 << 6)
> 
>  #define DP_PROTOCOL_CONVERTER_CONTROL_0		0x3050 /* DP 1.3
> */
>  # define DP_HDMI_DVI_OUTPUT_CONFIG		(1 << 0) /* DP 1.3 */
> @@ -1967,4 +2033,18 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux
> *aux,
>  				struct drm_dp_phy_test_params *data);  int
> drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>  				struct drm_dp_phy_test_params *data, u8
> dp_rev);
> +int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +			       const u8 port_cap[4]);
> +int drm_dp_get_hdmi_max_frl_bw(struct drm_dp_aux *aux); int
> +drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool
> +enable_frl_ready_hpd); bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux
> +*aux); int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int
> max_frl_gbps,
> +				bool concurrent_mode);
> +int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
> +				bool extended_train_mode);
> +int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); int
> +drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
> +
> +bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); int
> +drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8
> +*frl_trained_mask);

Leave a blank line here.

>  #endif /* _DRM_DP_HELPER_H_ */
> --
> 2.17.1

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RE: [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure
> 
> HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and by the
> sink.
> 
> This patch captures these in dfp cap structure in intel_dp and uses these to
> prune connector modes that cannot be supported by the PCON and sink FRL
> bandwidth.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 33 +++++++++++++++++--
>  2 files changed, 32 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0b5df8e44966..e2f58d0575a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1398,6 +1398,7 @@ struct intel_dp {
>  	struct {
>  		int min_tmds_clock, max_tmds_clock;
>  		int max_dotclock;
> +		int pcon_max_frl, sink_max_frl;

Append it with bw or rate.

>  		u8 max_bpc;
>  		bool ycbcr_444_to_420;
>  	} dfp;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0902a9aeeda1..cd6934f28f32 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -683,6 +683,24 @@ intel_dp_mode_valid_downstream(struct
> intel_connector *connector,
>  	const struct drm_display_info *info = &connector->base.display_info;
>  	int tmds_clock;
> 
> +	/* If PCON and HDMI2.1 sink both support FRL MODE, check FRL

Use multi line comment style.

> +	 * bandwidth constraints.
> +	 */
> +	if (intel_dp->dfp.pcon_max_frl) {
> +		int target_bw;
> +		int max_frl_bw;
> +		int bpp = intel_dp_mode_min_output_bpp(&connector->base,
> mode);
> +
> +		target_bw = bpp * DIV_ROUND_UP(target_clock, 1000000);

To avoid any roundup errors, it would be good to multiple max_frl_bw by 1000000 than dividing target_clock

> +
> +		max_frl_bw = min(intel_dp->dfp.pcon_max_frl,
> +				 intel_dp->dfp.sink_max_frl);
> +		if (target_bw > max_frl_bw)
> +			return MODE_CLOCK_HIGH;
> +
> +		return MODE_OK;
> +	}
> +
>  	if (intel_dp->dfp.max_dotclock &&
>  	    target_clock > intel_dp->dfp.max_dotclock)
>  		return MODE_CLOCK_HIGH;
> @@ -6383,13 +6401,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
>  						 intel_dp->downstream_ports,
>  						 edid);
> 
> +	intel_dp->dfp.pcon_max_frl =
> +		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
> +					   intel_dp->downstream_ports);
> +
> +	intel_dp->dfp.sink_max_frl =
> +drm_dp_get_hdmi_max_frl_bw(&intel_dp->aux);
> +
>  	drm_dbg_kms(&i915->drm,
> -		    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d,
> TMDS clock %d-%d\n",
> +		    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d,
> TMDS clock
> +%d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n",
>  		    connector->base.base.id, connector->base.name,
>  		    intel_dp->dfp.max_bpc,
>  		    intel_dp->dfp.max_dotclock,
>  		    intel_dp->dfp.min_tmds_clock,
> -		    intel_dp->dfp.max_tmds_clock);
> +		    intel_dp->dfp.max_tmds_clock,
> +		    intel_dp->dfp.pcon_max_frl,
> +		    intel_dp->dfp.sink_max_frl);
>  }
> 
>  static void
> @@ -6479,6 +6505,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>  	intel_dp->dfp.min_tmds_clock = 0;
>  	intel_dp->dfp.max_tmds_clock = 0;
> 
> +	intel_dp->dfp.pcon_max_frl = 0;
> +	intel_dp->dfp.sink_max_frl = 0;
> +
>  	intel_dp->dfp.ycbcr_444_to_420 = false;
>  	connector->base.ycbcr_420_allowed = false;  }
> --
> 2.17.1

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RE: [RFC 05/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 05/13] drm/i915: Add support for starting FRL training for HDMI2.1
> via PCON
> 
> This patch adds functions to start FRL training for an HDMI2.1 sink, connected via
> a PCON as a DP branch device.
> This patch also adds a new structure for storing frl training related data, when
> FRL training is completed.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |   7 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 200 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h       |   2 +
>  3 files changed, 209 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e2f58d0575a2..6c69922313d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1287,6 +1287,11 @@ struct intel_dp_compliance {
>  	u8 test_lane_count;
>  };
> 
> +struct intel_dp_pcon_frl {
> +	bool is_trained;
> +	int trained_rate_gbps;
> +};
> +
>  struct intel_dp {
>  	i915_reg_t output_reg;
>  	u32 DP;
> @@ -1408,6 +1413,8 @@ struct intel_dp {
> 
>  	bool hobl_failed;
>  	bool hobl_active;
> +
> +	struct intel_dp_pcon_frl frl;
>  };
> 
>  enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index cd6934f28f32..c1342b5e7781 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2885,6 +2885,9 @@ static void intel_dp_prepare(struct intel_encoder
> *encoder,
>  			intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
>  		else
>  			intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
> +
> +		intel_dp->frl.is_trained = false;
> +		intel_dp->frl.trained_rate_gbps = 0;
>  	}
>  }
> 
> @@ -3781,6 +3784,9 @@ static void intel_disable_dp(struct intel_atomic_state
> *state,
>  	intel_edp_backlight_off(old_conn_state);
>  	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>  	intel_edp_panel_off(intel_dp);
> +
> +	intel_dp->frl.is_trained = false;
> +	intel_dp->frl.trained_rate_gbps = 0;
>  }
> 
>  static void g4x_disable_dp(struct intel_atomic_state *state, @@ -3876,6
> +3882,200 @@ cpt_set_link_train(struct intel_dp *intel_dp,
>  	intel_de_posting_read(dev_priv, intel_dp->output_reg);  }
> 
> +static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp) {
> +	int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps;
> +
> +	max_link_clock = intel_dp_max_link_rate(intel_dp);
> +	max_lanes = intel_dp_max_lane_count(intel_dp);
> +	max_rate_khz = intel_dp_max_data_rate(max_link_clock, max_lanes);
> +	max_rate_gbps = 8 * DIV_ROUND_UP(max_rate_khz, 1000000);
> +
> +	return max_rate_gbps;
> +}
> +
> +static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) {
> +	int bw_gbps[] = {9, 18, 24, 32, 40, 48};
> +	int i;
> +
> +	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
> +		if (frl_bw_mask & (1 << i))
> +			return bw_gbps[i];
> +	}
> +	return 0;
> +}
> +
> +static int intel_dp_pcon_set_frl_mask(int max_frl) {
> +	int max_frl_mask = 0;
> +
> +	switch (max_frl) {
> +	case 48:
> +		max_frl_mask |= DP_PCON_FRL_BW_MASK_48GBPS;

Just say it as return DP_PCON_FRL_BW_MASK_48GBPS. 
Do it universally.

> +		break;
> +	case 40:
> +		max_frl_mask |= DP_PCON_FRL_BW_MASK_40GBPS;
> +		break;
> +	case 32:
> +		max_frl_mask |= DP_PCON_FRL_BW_MASK_32GBPS;
> +		break;
> +	case 24:
> +		max_frl_mask |= DP_PCON_FRL_BW_MASK_24GBPS;
> +		break;
> +	case 18:
> +		max_frl_mask |= DP_PCON_FRL_BW_MASK_18GBPS;
> +		break;
> +	case 9:
> +		max_frl_mask |= DP_PCON_FRL_BW_MASK_9GBPS;
> +		break;
> +	default:
> +		max_frl_mask = 0;
> +	}
> +
> +	return max_frl_mask;
> +}
> +
> +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) {
> +	struct intel_connector *intel_connector = intel_dp->attached_connector;
> +	struct drm_connector *connector = &intel_connector->base;
> +
> +	return (connector->display_info.hdmi.max_frl_rate_per_lane *
> +		connector->display_info.hdmi.max_lanes);
> +}
> +
> +static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
> +{ #define PCON_EXTENDED_TRAIN_MODE true#define
> PCON_CONCURRENT_MODE
> +true #define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE #define
> +PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE #define

Don't use true instead 1 < 0 as true is not the right thing to be used here.

> +TIMEOUT_FRL_READY_MS 500 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
> +
> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +	int max_frl, max_pcon_frl, max_sink_frl, max_rate_gbps, max_frl_edid,
> ret;
> +	u8 max_frl_mask = 0, frl_trained_mask;
> +	bool is_active;
> +
> +	ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
> +	if (ret < 0)
> +		return ret;
> +
> +	max_rate_gbps = intel_dp_get_max_rate_gbps(intel_dp);
> +	drm_dbg(&i915->drm, "Source max rate = %d Gbps\n", max_rate_gbps);
> +
> +	max_pcon_frl = intel_dp->dfp.pcon_max_frl;

Append it with rate or bw.

> +	drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl);
> +
> +	/* Double Check from HDMI SINK EDID */
> +	max_frl_edid = intel_dp_hdmi_sink_max_frl(intel_dp);
> +	drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n",
> +max_frl_edid);
> +
> +	max_sink_frl = intel_dp->dfp.sink_max_frl;
> +	drm_dbg(&i915->drm, "Sink max rate from PCON = %d Gbps\n",
> +max_sink_frl);
> +
> +	/* TODO MAX SINK FRL from PCON is not enumerated. Using MAX FRL
> value

Use multi line comment style.

> +	 * directly from EDID. Need to confirm from Spec.
> +	 */
> +	max_frl = min(max_rate_gbps, min(max_frl_edid, max_pcon_frl));
> +
> +	if (max_frl <= 0)
> +		return -EINVAL;
> +
> +	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
> +	if (ret < 0)
> +		return ret;
> +	/* Wait for PCON to be FRL Ready */
> +	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true,
> +TIMEOUT_FRL_READY_MS);
> +
> +	if (!is_active)
> +		return -ETIMEDOUT;
> +
> +	max_frl_mask = intel_dp_pcon_set_frl_mask(max_frl);
> +	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl,
> PCON_SEQUENTIAL_MODE);
> +	if (ret < 0)
> +		return ret;
> +	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_mask,
> PCON_NORMAL_TRAIN_MODE);
> +	if (ret < 0)
> +		return ret;
> +	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
> +	if (ret < 0)
> +		return ret;
> +	/*
> +	 * Wait for FRL to be completed
> +	 * Check if the HDMI Link is up and active.
> +	 */
> +	wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) ==
> +true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
> +
> +	if (!is_active)
> +		return -ETIMEDOUT;
> +	/*
> +	 * Verify HDMI Link configuration shows FRL Mode.
> +	 */
> +	if (DP_PCON_HDMI_MODE_FRL !=
> drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask)) {
> +		drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL
> Mode\n");
> +		return -EINVAL;
> +	}
> +	drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK =
> %u\n",
> +max_frl_mask, frl_trained_mask);
> +
> +	/*
> +	 * Read HDMI_LINK_STATUS_TRAINED 0x2005 bit 5
> +	 * TODO: Details not mentioned in spec. Need to check.
> +	 */
> +
> +	intel_dp->frl.trained_rate_gbps =
> intel_dp_pcon_get_frl_mask(frl_trained_mask);
> +	intel_dp->frl.is_trained = true;
> +	drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n",
> +intel_dp->frl.trained_rate_gbps);
> +
> +	return 0;
> +}
> +
> +static bool intel_dp_is_frl_required(struct intel_dp *intel_dp) {
> +	if (!intel_dp->frl.is_trained)
> +		return true;
> +	/*
> +	 * #TODO check if the mode really required FRL or can work
> +	 * with TMDS mode.
> +	 */
> +
> +	return false;
> +}
> +
> +static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) {
> +	if (drm_dp_is_branch(intel_dp->dpcd) &&
> +	    intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
> +		return true;
> +
> +	return false;
> +}
> +
> +void intel_dp_check_frl_training(struct intel_dp *intel_dp) {
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
> +	    !intel_dp_is_frl_required(intel_dp))
> +		return;
> +
> +	if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
> +		int ret, mode;
> +
> +		drm_dbg(&dev_priv->drm, "Couldnt set FRL mode, continuing
> with TMDS mode\n");
> +		ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
> +		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
> +
> +		if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
> +			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set
> TMDS mode\n");
> +	}
> +
> +	else

Move it up and enclose in { to match the above if style.

> +		drm_dbg(&dev_priv->drm, "FRL training Completed\n"); }
> +
>  static void
>  g4x_set_link_train(struct intel_dp *intel_dp,
>  		   const struct intel_crtc_state *crtc_state, diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index fcc28eb242f2..81d83d88cd41 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -143,4 +143,6 @@ bool intel_dp_initial_fastset_check(struct intel_encoder
> *encoder,  void intel_dp_sync_state(struct intel_encoder *encoder,
>  			 const struct intel_crtc_state *crtc_state);
> 
> +void intel_dp_check_frl_training(struct intel_dp *intel_dp);
> +
>  #endif /* __INTEL_DP_H__ */
> --
> 2.17.1

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RE: [RFC 06/13] drm/i915: Check for FRL training before DP Link training

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 06/13] drm/i915: Check for FRL training before DP Link training
> 
> This patch calls functions to check FRL training requirements for an HDMI2.1 sink,
> when connected through PCON.
> The call is made before the DP link training. In case FRL is not required or failure
> during FRL training, the TMDS mode is selected for the pcon.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/display/intel_dp.c  | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bb0b9930958f..1834e5de60a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3484,6 +3484,8 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
>  	if (!is_mst)
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> 
> +	intel_dp_check_frl_training(intel_dp);

Good to move it near start_link_training to stay consistent with rest of the calls.

> +
>  	intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
>  	/*
>  	 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index c1342b5e7781..668165dd2b1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4206,6 +4206,7 @@ static void intel_enable_dp(struct intel_atomic_state
> *state,
> 
>  	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>  	intel_dp_configure_protocol_converter(intel_dp);
> +	intel_dp_check_frl_training(intel_dp);
>  	intel_dp_start_link_train(intel_dp, pipe_config);
>  	intel_dp_stop_link_train(intel_dp, pipe_config);
> 
> @@ -6127,6 +6128,7 @@ int intel_dp_retrain_link(struct intel_encoder
> *encoder,
>  		    !intel_dp_mst_is_master_trans(crtc_state))
>  			continue;
> 
> +		intel_dp_check_frl_training(intel_dp);
>  		intel_dp_start_link_train(intel_dp, crtc_state);
>  		intel_dp_stop_link_train(intel_dp, crtc_state);
>  		break;
> --
> 2.17.1

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RE: [RFC 07/13] drm/dp_helper: Add support for link status and link recovery

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 07/13] drm/dp_helper: Add support for link status and link
> recovery

Move this in the start of the series along with rest of the generic DRM helpers.

> From: Swati Sharma <swati2.sharma@intel.com>
> 
> This patch adds support for link status and link recovery. There are specific
> DPCD’s defined for link status check and recovery in case of any issues. PCON will
> communicate the same using an IRQ_HPD to source. HDMI sink would have
> indicated the same to PCON using SCDC interrupt mechanism. While source can
> always read final HDMI sink’s status using I2C over AUX, it’s easier and faster to
> read the PCON’s already read HDMI sink’s status registers.
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 33 +++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     | 16 ++++++++++++++++
>  2 files changed, 49 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c index df858533dbf7..33a4ac2fb225 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -2896,3 +2896,36 @@ int drm_dp_pcon_hdmi_link_mode(struct
> drm_dp_aux *aux, u8 *frl_trained_mask)
>  	return mode;
>  }
>  EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
> +
> +void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
> +					   struct drm_connector *connector) {

This just prints a message if error counts are detected. There isn't any recovery here.
May be you should re-phrase the patch header and description to reflect the same.

Also what will be the usage of this just prints a message, may be return the error to caller
to plan a recovery or link reset .

> +	u8 buf, error_count;
> +	int i, num_error;
> +	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
> +
> +	for (i = 0; i < hdmi->max_lanes; i++)
> +	{
> +		if (drm_dp_dpcd_readb(aux,
> DP_PCON_HDMI_ERROR_STATUS_LN0 + i , &buf) < 0)
> +			return;
> +
> +		error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
> +
> +	switch(error_count) {

Alignment is off.

> +	case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
> +		num_error = 100;
> +		break;
> +	case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
> +		num_error = 10;
> +		break;
> +	case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
> +		num_error = 3;
> +		break;
> +	default:
> +		num_error = 0;
> +	}
> +
> +		DRM_ERROR("More than %d errors since the last read for lane
> %d", num_error, i);
> +	}
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> d6f79b2d1287..eb26c86dc8ca 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -946,6 +946,11 @@ struct drm_device;
>  # define DP_CEC_IRQ                          (1 << 2)
> 
>  #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
> +# define RX_CAP_CHANGED                      (1 << 0)
> +# define LINK_STATUS_CHANGED                 (1 << 1)
> +# define STREAM_STATUS_CHANGED               (1 << 2)
> +# define HDMI_LINK_STATUS_CHANGED            (1 << 3)
> +# define CONNECTED_OFF_ENTRY_REQUESTED       (1 << 4)
> 
>  #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
>  # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
> @@ -1130,6 +1135,16 @@ struct drm_device;
>  #define DP_PROTOCOL_CONVERTER_CONTROL_2		0x3052 /* DP 1.3
> */
>  # define DP_CONVERSION_TO_YCBCR422_ENABLE	(1 << 0) /* DP 1.3 */
> 
> +/* PCON Downstream HDMI ERROR Status per Lane */
> +#define DP_PCON_HDMI_ERROR_STATUS_LN0          0x3037
> +#define DP_PCON_HDMI_ERROR_STATUS_LN1          0x3038
> +#define DP_PCON_HDMI_ERROR_STATUS_LN2          0x3039
> +#define DP_PCON_HDMI_ERROR_STATUS_LN3          0x303A
> +# define DP_PCON_HDMI_ERROR_COUNT_MASK         (0x7 << 0)
> +# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS   (1 << 0)
> +# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS     (1 << 1)
> +# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
> +
>  /* HDCP 1.3 and HDCP 2.2 */
>  #define DP_AUX_HDCP_BKSV		0x68000
>  #define DP_AUX_HDCP_RI_PRIME		0x68005
> @@ -2047,4 +2062,5 @@ int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
> 
>  bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);  int
> drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
> +void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
> +struct drm_connector *connector);

Leave a blank line.

>  #endif /* _DRM_DP_HELPER_H_ */
> --
> 2.17.1

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RE: [RFC 08/13] drm/i915: Add support for enabling link status and recovery

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 08/13] drm/i915: Add support for enabling link status and recovery
> 
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> In this patch enabled support for link status and recovery in i915 driver. HDMI
> link loss indication to upstream DP source is indicated via IRQ_HPD. This is
> followed by reading of HDMI link configuration status
> (HDMI_TX_LINK_ACTIVE_STATUS). If the PCON → HDMI 2.1 link status is off;
> reinitiate frl link training to recover.
> Also, HDMI FRL link error count range for each individual FRL active lane is
> indicated by DOWNSTREAM_HDMI_ERROR_STATUS_LN registers.
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++++--
>  1 file changed, 44 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 668165dd2b1a..e6c4cb844e37 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5955,6 +5955,29 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
>  	return link_ok;
>  }
> 
> +static void
> +intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) {
> +	bool is_active;
> +	u8 buf = 0;
> +
> +	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
> +	if (intel_dp->frl.is_trained && !is_active) {
> +		if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
> +			return;
> +
> +		buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
> +		if (drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
> +			return;
> +
> +		intel_dp->frl.is_trained = false;
> +		intel_dp->frl.trained_rate_gbps = 0;
> +
> +		intel_dp_check_frl_training(intel_dp);
> +		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux,
> &intel_dp->attached_connector->base);

Just printing the error here may not help in recovery. If FRL is failing may be a TMDS fallback should be
attempted. Also error count should be returned instead of just a print.

> +	}
> +}
> +
>  static bool
>  intel_dp_needs_link_retrain(struct intel_dp *intel_dp)  { @@ -6320,7 +6343,7
> @@ intel_dp_hotplug(struct intel_encoder *encoder,
>  	return state;
>  }
> 
> -static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
> +static void intel_dp_check_device_service_irq(struct intel_dp
> +*intel_dp)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	u8 val;
> @@ -6344,6 +6367,23 @@ static void intel_dp_check_service_irq(struct intel_dp
> *intel_dp)
>  		drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");  }
> 
> +static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
> +{
> +	u8 val;
> +
> +	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
> +		return;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> +			      DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 ||
> !val)

An error message would be handy here.

> +		return;
> +
> +	drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_LINK_SERVICE_IRQ_VECTOR_ESI0,
> +val);

Check for error message here.

> +
> +	if (val & HDMI_LINK_STATUS_CHANGED)
> +		intel_dp_handle_hdmi_link_status_change(intel_dp);
> +}
> +
>  /*
>   * According to DP spec
>   * 5.1.2:
> @@ -6383,7 +6423,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
>  		return false;
>  	}
> 
> -	intel_dp_check_service_irq(intel_dp);
> +	intel_dp_check_device_service_irq(intel_dp);
> +	intel_dp_check_link_service_irq(intel_dp);
> 
>  	/* Handle CEC interrupts, if any */
>  	drm_dp_cec_irq(&intel_dp->aux);
> @@ -6815,7 +6856,7 @@ intel_dp_detect(struct drm_connector *connector,
>  	    to_intel_connector(connector)->detect_edid)
>  		status = connector_status_connected;
> 
> -	intel_dp_check_service_irq(intel_dp);
> +	intel_dp_check_device_service_irq(intel_dp);
> 
>  out:
>  	if (status != connector_status_connected && !intel_dp->is_mst)
> --
> 2.17.1

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RE: [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block

Move this also to beginning of series along with all DRM helpers.

> This patch parses HFVSDB fields for DSC1.2 capabilities of an
> HDMI2.1 sink. These fields are required by a source to understand the DSC
> capability of the sink, to set appropriate PPS parameters, before transmitting
> compressed data stream.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c  | 19 +++++++++++++++++++
> include/drm/drm_connector.h | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 51 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 8afb136e73f5..feee19657a7a 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4889,10 +4889,29 @@ static void
> drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,  {
>  	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
>  	u8 max_frl_rate;
> +	u8 dsc_max_frl_rate;
> 
>  	max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;
>  	drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
>  			     &hdmi->max_frl_rate_per_lane);
> +
> +	hdmi->dsc_1p2 = db[11] & DRM_EDID_DSC_1P2;

We should right shift them as well to get right values.

> +        hdmi->dsc_native_420 = db[11] & DRM_EDID_DSC_NATIVE_420;

Same here. Also Alignment is off.

> +	hdmi->dsc_all_bpp = db[11] & DRM_EDID_DSC_ALL_BPP;
> +
> +	if (db[11] & DRM_EDID_DSC_16BPC)
> +		hdmi->dsc_bpc_supported = 16;
> +	else if (db[11] & DRM_EDID_DSC_12BPC)
> +		hdmi->dsc_bpc_supported = 12;
> +	else if (db[11] & DRM_EDID_DSC_10BPC)
> +		hdmi->dsc_bpc_supported = 10;
> +	else
> +		hdmi->dsc_bpc_supported = 0;
> +
> +	dsc_max_frl_rate = db[12] & DRM_EDID_DSC_MAX_FRL_RATE;

This will not give correct value. Fix it.

> +	drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi->dsc_max_lanes,
> +			     &hdmi->dsc_max_frl_rate_per_lane);
> +	hdmi->dsc_total_chunk_kbytes = db[13] &
> +DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
>  }
> 
>  static void drm_parse_ycbcr420_deep_color_info(struct drm_connector
> *connector, diff --git a/include/drm/drm_connector.h
> b/include/drm/drm_connector.h index f351bf10c076..7100012f9c0f 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -213,6 +213,38 @@ struct drm_hdmi_info {
> 
>  	/** @max_lanes: supported by sink */
>  	u8 max_lanes;
> +
> +	/** @dsc_1p2: flag for dsc1.2 support by sink */
> +	bool dsc_1p2;

Add a struct for all these HDMI dsc params.

> +
> +	/** @dsc_native_420: Does sink support DSC with 4:2:0 compression */
> +	bool dsc_native_420;
> +
> +	/**
> +	 * @dsc_all_bpp: Does sink support all bpp with 4:4:4: or 4:2:2
> +	 * compressed formats
> +	 */
> +	bool dsc_all_bpp;
> +
> +	/**
> +	 * @dsc_bpc_supported: compressed bpc supported by sink : 10, 12 or 16
> bpc
> +	 */
> +	u8 dsc_bpc_supported;
> +
> +	/** @dsc_max_slices: maximum number of Horizontal slices supported
> by */
> +	u8 dsc_max_slices;
> +
> +	/** @dsc_clk_per_slice : max pixel clock in MHz supported per slice */
> +	u8 dsc_clk_per_slice;
> +
> +	/** @dsc_max_lanes : dsc max lanes supported for Fixed rate Link
> training */
> +	u8 dsc_max_lanes;
> +
> +	/** @dsc_max_frl_rate_per_lane : maximum frl rate with DSC per lane */
> +	u8 dsc_max_frl_rate_per_lane;
> +
> +	/** @dsc_total_chunk_kbytes: max size of chunks in KBs supported per
> line*/
> +	u8 dsc_total_chunk_kbytes;
>  };
> 
>  /**
> --
> 2.17.1

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RE: [RFC 10/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 10/13] drm/dp_helper: Add support for Configuring DSC for
> HDMI2.1 Pcon
> 
> This patch adds registers for getting DSC encoder capability for a HDMI2.1 PCon.
> It also addes helper functions to configure DSC between the PCON and HDMI2.1
> sink.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c |  93 +++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     | 109 ++++++++++++++++++++++++++++++++
>  2 files changed, 202 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c index 33a4ac2fb225..f10a9c2d6f04 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -2929,3 +2929,96 @@ void drm_dp_pcon_hdmi_frl_link_error_count(struct
> drm_dp_aux *aux,
>  	}
>  }
>  EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
> +
> +static
> +int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8
> +pps_buf_config) {
> +	u8 buf = 0;
> +	int ret;
> +
> +	buf |= DP_PCON_ENABLE_DSC_ENCODER;

Directly assign it.

> +	if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
> +		buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
> +		buf |= pps_buf_config << 2;
> +	}
> +
> +	ret = drm_dp_dpcd_writeb(aux,
> DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +/**
> + * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
> + * for DSC1.2 between PCON & HDMI2.1 sink
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns 0 on success, else returns negative error code.
> + * */
> +int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) {
> +	int ret;
> +
> +	ret = drm_dp_pcon_configure_dsc_enc(aux,
> DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_pps_default);
> +
> +/**
> + * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override
> +buffer for
> + * HDMI sink
> + * @aux: DisplayPort AUX channel
> + * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
> + *
> + * Returns 0 on success, else returns negative error code.
> + * */
> +int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8
> +pps_buf[128]) {
> +	int ret;
> +
> +	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE,
> &pps_buf, 128);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = drm_dp_pcon_configure_dsc_enc(aux,
> DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
> +
> +/*
> + * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC
> +encoder
> + * override registers
> + * @aux: DisplayPort AUX channel
> + * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
> + * bits_per_pixel.
> + *
> + * Returns 0 on success, else returns negative error code.
> + * */
> +int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8
> +pps_param[6]) {
> +	int ret;
> +
> +	ret = drm_dp_dpcd_write(aux,
> DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
> +	if (ret < 0)
> +		return ret;
> +	ret = drm_dp_dpcd_write(aux,
> DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[1], 2);
> +	if (ret < 0)
> +		return ret;
> +	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP,
> &pps_param[2], 2);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = drm_dp_pcon_configure_dsc_enc(aux,
> DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> eb26c86dc8ca..3de022d4a65e 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -441,6 +441,83 @@ struct drm_device;
>  # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP    (1 << 2)
>  # define DP_FEC_BIT_ERROR_COUNT_CAP	    (1 << 3)
> 
> +/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
> +#define DP_PCON_DSC_ENCODER                 0x092
> +# define DP_PCON_DSC_ENCODER_SUPPORTED      (1 << 0)
> +# define DP_PCON_DSC_PPS_ENC_OVERRIDE       (1 << 1)
> +
> +/* DP-HDMI2.1 PCON DSC Version */
> +#define DP_PCON_DSC_VERSION                 0x093
> +# define DP_PCON_DSC_MAJOR_MASK		    (0xF << 0)
> +# define DP_PCON_DSC_MINOR_MASK		    (0xF << 4)
> +# define DP_PCON_DSC_MAJOR_SHIFT	    0
> +# define DP_PCON_DSC_MINOR_SHIFT	    4
> +
> +/* DP-HDMI2.1 PCON DSC RC Buffer block size */
> +#define DP_PCON_DSC_RC_BUF_BLK_INFO	    0x094
> +# define DP_PCON_DSC_RC_BUF_BLK_SIZE	    (0x3 << 0)
> +# define DP_PCON_DSC_RC_BUF_BLK_1KB	    0
> +# define DP_PCON_DSC_RC_BUF_BLK_4KB	    1
> +# define DP_PCON_DSC_RC_BUF_BLK_16KB	    2
> +# define DP_PCON_DSC_RC_BUF_BLK_64KB	    3
> +
> +/* DP-HDMI2.1 PCON DSC RC Buffer size */
> +#define DP_PCON_DSC_RC_BUF_SIZE		    0x095
> +
> +/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
> +#define DP_PCON_DSC_SLICE_CAP_1		    0x096
> +# define DP_PCON_DSC_1_PER_DSC_ENC     (0x1 << 0)
> +# define DP_PCON_DSC_2_PER_DSC_ENC     (0x1 << 1)
> +# define DP_PCON_DSC_4_PER_DSC_ENC     (0x1 << 3)
> +# define DP_PCON_DSC_6_PER_DSC_ENC     (0x1 << 4)
> +# define DP_PCON_DSC_8_PER_DSC_ENC     (0x1 << 5)
> +# define DP_PCON_DSC_10_PER_DSC_ENC    (0x1 << 6)
> +# define DP_PCON_DSC_12_PER_DSC_ENC    (0x1 << 7)
> +
> +#define DP_PCON_DSC_BUF_BIT_DEPTH	    0x097
> +# define DP_PCON_DSC_BIT_DEPTH_MASK	    (0xF << 0)
> +# define DP_PCON_DSC_DEPTH_9_BITS	    0
> +# define DP_PCON_DSC_DEPTH_10_BITS	    1
> +# define DP_PCON_DSC_DEPTH_11_BITS	    2
> +# define DP_PCON_DSC_DEPTH_12_BITS	    3
> +# define DP_PCON_DSC_DEPTH_13_BITS	    4
> +# define DP_PCON_DSC_DEPTH_14_BITS	    5
> +# define DP_PCON_DSC_DEPTH_15_BITS	    6
> +# define DP_PCON_DSC_DEPTH_16_BITS	    7
> +# define DP_PCON_DSC_DEPTH_8_BITS	    8
> +
> +#define DP_PCON_DSC_BLOCK_PREDICTION	    0x098
> +# define DP_PCON_DSC_BLOCK_PRED_SUPPORT	    (0x1 << 0)
> +
> +#define DP_PCON_DSC_ENC_COLOR_FMT_CAP	    0x099
> +# define DP_PCON_DSC_ENC_RGB		    (0x1 << 0)
> +# define DP_PCON_DSC_ENC_YUV444		    (0x1 << 1)
> +# define DP_PCON_DSC_ENC_YUV422_S	    (0x1 << 2)
> +# define DP_PCON_DSC_ENC_YUV422_N	    (0x1 << 3)
> +# define DP_PCON_DSC_ENC_YUV420_N	    (0x1 << 4)
> +
> +#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP	    0x09A
> +# define DP_PCON_DSC_ENC_8BPC		    (0x1 << 0)
> +# define DP_PCON_DSC_ENC_10BPC		    (0x1 << 0)
> +# define DP_PCON_DSC_ENC_12BPC		    (0x1 << 0)

These offsets are wrong, should be 0x1 < (1, 2 and 3)

> +
> +#define DP_PCON_DSC_MAX_SLICE_WIDTH	    0x09B
> +
> +/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
> +#define DP_PCON_DSC_SLICE_CAP_2             0x09C
> +# define DP_PCON_DSC_16_PER_DSC_ENC	    (0x1 << 0)
> +# define DP_PCON_DSC_20_PER_DSC_ENC         (0x1 << 1)
> +# define DP_PCON_DSC_24_PER_DSC_ENC         (0x1 << 2)
> +
> +/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
> +#define DP_PCON_DSC_BPP_INCR		    0x09E
> +# define DP_PCON_DSC_BPP_INCR_MASK	    (0x7 << 0)
> +# define DP_PCON_DSC_ONE_16TH_BPP	    0
> +# define DP_PCON_DSC_ONE_8TH_BPP	    1
> +# define DP_PCON_DSC_ONE_4TH_BPP	    2
> +# define DP_PCON_DSC_ONE_HALF_BPP	    3
> +# define DP_PCON_DSC_ONE_BPP		    4
> +
>  /* DP Extended DSC Capabilities */
>  #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0  0x0a0   /* DP 1.4a SCR */
>  #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1 @@ -1134,6
> +1211,12 @@ struct drm_device;
>  # define DP_HDMI_FORCE_SCRAMBLING		(1 << 3) /* DP 1.4 */
>  #define DP_PROTOCOL_CONVERTER_CONTROL_2		0x3052 /* DP 1.3
> */
>  # define DP_CONVERSION_TO_YCBCR422_ENABLE	(1 << 0) /* DP 1.3 */
> +# define DP_PCON_ENABLE_DSC_ENCODER	        (1 << 1)
> +# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK	(0x3 << 2)
> +# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED      0
> +# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS     1
> +# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER     2
> +
> 
>  /* PCON Downstream HDMI ERROR Status per Lane */
>  #define DP_PCON_HDMI_ERROR_STATUS_LN0          0x3037
> @@ -1145,6 +1228,29 @@ struct drm_device;
>  # define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS     (1 << 1)
>  # define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
> 
> +/* PCON HDMI CONFIG PPS Override Buffer
> + * Valid Offsets to be added to Base : 0-127  */
> +#define DP_PCON_HDMI_PPS_OVERRIDE_BASE        0x3100
> +
> +/* PCON HDMI CONFIG PPS Override Parameter: Slice height
> + * Offset-0 8LSBs of the Slice height.
> + * Offset-1 8MSBs of the Slice height.
> + */
> +#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT    0x3180
> +
> +/* PCON HDMI CONFIG PPS Override Parameter: Slice width
> + * Offset-0 8LSBs of the Slice width.
> + * Offset-1 8MSBs of the Slice width.
> + */
> +#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH    0x3182
> +
> +/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
> + * Offset-0 8LSBs of the bits_per_pixel.
> + * Offset-1 2MSBs of the bits_per_pixel.
> + */
> +#define DP_PCON_HDMI_PPS_OVRD_BPP	     0x3184
> +
>  /* HDCP 1.3 and HDCP 2.2 */
>  #define DP_AUX_HDCP_BKSV		0x68000
>  #define DP_AUX_HDCP_RI_PRIME		0x68005
> @@ -2063,4 +2169,7 @@ int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
> bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);  int
> drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
> void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, struct
> drm_connector *connector);
> +int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); int
> +drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
> +int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8
> +pps_param[6]);
>  #endif /* _DRM_DP_HELPER_H_ */
> --
> 2.17.1

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RE: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
> Sharma, Swati2 <swati2.sharma@intel.com>
> Subject: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON
> encoder
> 
> This patch adds a helper function to read the DSC capabilities of the
> HDMI2.1 PCon encoder. It also adds a new structure to store these caps, which
> can then be used to get the PPS parameters for PCON-HDMI2.1 sink pair. Which
> inturn will be used to take a call to override the existing PPS-metadata, by either
> writing the entire new PPS metadata, or by writing only the PPS override
> parameters.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  16 ++
>  drivers/gpu/drm/i915/display/intel_dp.c       | 178 ++++++++++++++++++
>  2 files changed, 194 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6c69922313d6..23282695a47f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1292,6 +1292,21 @@ struct intel_dp_pcon_frl {
>  	int trained_rate_gbps;
>  };
> 
> +struct intel_dp_pcon_dsc {
> +	bool enc_support;
> +	bool pps_override_support;
> +	bool blk_prediction_support;
> +	u8 version_major;
> +	u8 version_minor;
> +	u8 color_fmt_mask;
> +	u8 color_depth_mask;
> +	u8 max_slices;;
> +	u8 max_slice_width;
> +	u8 line_buf_bit_depth;
> +	u8 bpp_precision_incr;
> +	int rc_buf_size;
> +};
> +
>  struct intel_dp {
>  	i915_reg_t output_reg;
>  	u32 DP;
> @@ -1415,6 +1430,7 @@ struct intel_dp {
>  	bool hobl_active;
> 
>  	struct intel_dp_pcon_frl frl;
> +	struct intel_dp_pcon_dsc pcon_dsc;
>  };
> 
>  enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e6c4cb844e37..b4f8abaea607 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3882,6 +3882,182 @@ cpt_set_link_train(struct intel_dp *intel_dp,
>  	intel_de_posting_read(dev_priv, intel_dp->output_reg);  }
> 
> +void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) {
> +	u8 buf;
> +	u8 rc_buf_blk_size;
> +	u8 max_slices = 0;
> +
> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +	struct intel_dp_pcon_dsc *pcon_dsc = &intel_dp->pcon_dsc;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENCODER, &buf)
> < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_ENCODER\n");
> +		return;
> +	}
> +	pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED;
> +	pcon_dsc->pps_override_support = buf &
> DP_PCON_DSC_PPS_ENC_OVERRIDE;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_VERSION, &buf)
> < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_VERSION\n");
> +		return;

If we fail here or in any of the subsequent calls below shouldn't we reset the dsc params saying DSC not
supported. Else we may return with ex.
pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED
which would ideally not be right.

> +	}
> +	pcon_dsc->version_major = (buf & DP_PCON_DSC_MAJOR_MASK) >>
> +				  DP_PCON_DSC_MAJOR_SHIFT;
> +	pcon_dsc->version_minor = (buf & DP_PCON_DSC_MINOR_MASK) >>
> +				  DP_PCON_DSC_MINOR_SHIFT;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_PCON_DSC_RC_BUF_BLK_INFO, &buf) < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_RC_BUF_BLK_INFO\n");
> +		return;
> +	}
> +
> +	switch (buf & DP_PCON_DSC_RC_BUF_BLK_SIZE) {
> +	case DP_PCON_DSC_RC_BUF_BLK_1KB :
> +		rc_buf_blk_size = 1;
> +		break;
> +	case DP_PCON_DSC_RC_BUF_BLK_4KB :
> +		rc_buf_blk_size = 4;
> +		break;
> +	case DP_PCON_DSC_RC_BUF_BLK_16KB :
> +		rc_buf_blk_size = 16;
> +		break;
> +	case DP_PCON_DSC_RC_BUF_BLK_64KB :
> +		rc_buf_blk_size = 64;
> +		break;
> +	default :
> +		rc_buf_blk_size = 0;
> +	}

It would be good if you create sub-functions for each of these aspects to make it more readable.

> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_RC_BUF_SIZE,
> &buf) < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_RC_BUF_SIZE\n");
> +		return;
> +	}
> +	/* storing rc_buf_size in bytes */
> +	pcon_dsc->rc_buf_size = (buf + 1) * rc_buf_blk_size * 1024;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_SLICE_CAP_2,
> &buf) < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_SLICE_CAP_2\n");
> +		return;
> +	}
> +	if (buf & DP_PCON_DSC_24_PER_DSC_ENC)
> +	       max_slices = 24;
> +	else if (buf & DP_PCON_DSC_20_PER_DSC_ENC)
> +		max_slices = 20;
> +	else if (buf & DP_PCON_DSC_16_PER_DSC_ENC)
> +		max_slices = 16;
> +
> +	if (max_slices == 0) {
> +		if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_PCON_DSC_SLICE_CAP_1,
> +				      &buf) < 0) {
> +			drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_SLICE_CAP_2\n");

Its SLICE_CAP_1.

> +			return;
> +		}
> +
> +		if (buf & DP_PCON_DSC_12_PER_DSC_ENC)
> +			max_slices = 12;
> +		else if (buf & DP_PCON_DSC_10_PER_DSC_ENC)
> +			max_slices = 10;
> +		else if (buf & DP_PCON_DSC_8_PER_DSC_ENC)
> +			max_slices = 8;
> +		else if (buf & DP_PCON_DSC_6_PER_DSC_ENC)
> +			max_slices = 6;
> +		else if (buf & DP_PCON_DSC_4_PER_DSC_ENC)
> +			max_slices = 4;
> +		else if (buf & DP_PCON_DSC_2_PER_DSC_ENC)
> +			max_slices = 2;
> +		else if (buf & DP_PCON_DSC_1_PER_DSC_ENC)
> +			max_slices = 1;

Use switch here as well.

> +	}
> +
> +	pcon_dsc->max_slices = max_slices;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BUF_BIT_DEPTH,
> &buf) < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_BUF_BIT_DEPTH\n");
> +		return;
> +	}
> +	switch (buf & DP_PCON_DSC_BIT_DEPTH_MASK) {
> +	case DP_PCON_DSC_DEPTH_8_BITS :
> +		pcon_dsc->line_buf_bit_depth = 8;
> +		break;
> +	case DP_PCON_DSC_DEPTH_9_BITS :
> +		pcon_dsc->line_buf_bit_depth = 9;
> +		break;
> +	case DP_PCON_DSC_DEPTH_10_BITS :
> +		pcon_dsc->line_buf_bit_depth = 10;
> +		break;
> +	case DP_PCON_DSC_DEPTH_11_BITS :
> +		pcon_dsc->line_buf_bit_depth = 11;
> +		break;
> +	case DP_PCON_DSC_DEPTH_12_BITS :
> +		pcon_dsc->line_buf_bit_depth = 12;
> +		break;
> +	case DP_PCON_DSC_DEPTH_13_BITS :
> +		pcon_dsc->line_buf_bit_depth = 13;
> +		break;
> +	case DP_PCON_DSC_DEPTH_14_BITS :
> +		pcon_dsc->line_buf_bit_depth = 14;
> +		break;
> +	case DP_PCON_DSC_DEPTH_15_BITS :
> +		pcon_dsc->line_buf_bit_depth = 15;
> +		break;
> +	case DP_PCON_DSC_DEPTH_16_BITS :
> +		pcon_dsc->line_buf_bit_depth = 16;
> +		break;
> +	default :
> +		pcon_dsc->line_buf_bit_depth = 0;
> +	}
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_PCON_DSC_BLOCK_PREDICTION, &buf) < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_BLOCK_PREDICTION\n");
> +		return;
> +	}
> +	if (buf && DP_PCON_DSC_BLOCK_PRED_SUPPORT)
> +		pcon_dsc->blk_prediction_support = true;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_PCON_DSC_ENC_COLOR_FMT_CAP, &buf) < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_ENC_COLOR_FMT_CAP\n");
> +		return;
> +	}
> +	pcon_dsc->color_fmt_mask = buf;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_PCON_DSC_ENC_COLOR_DEPTH_CAP, &buf) < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_ENC_COLOR_DEPTH_CAP\n");
> +		return;
> +	}
> +	pcon_dsc->color_depth_mask = buf;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_PCON_DSC_MAX_SLICE_WIDTH, &buf) < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_MAX_SLICE_WIDTH\n");
> +		return;
> +	}
> +	pcon_dsc->max_slice_width = buf;;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BPP_INCR, &buf)
> < 0) {
> +		drm_err(&i915->drm, "Failed to read
> DP_PCON_DSC_BPP_INCR\n");
> +		return;
> +	}
> +	switch(buf & DP_PCON_DSC_BPP_INCR_MASK) {
> +	case DP_PCON_DSC_ONE_16TH_BPP:
> +		pcon_dsc->bpp_precision_incr = 16;
> +		break;
> +	case DP_PCON_DSC_ONE_8TH_BPP:
> +		pcon_dsc->bpp_precision_incr = 8;
> +		break;
> +	case DP_PCON_DSC_ONE_4TH_BPP:
> +		pcon_dsc->bpp_precision_incr = 4;
> +		break;
> +	case DP_PCON_DSC_ONE_HALF_BPP:
> +		pcon_dsc->bpp_precision_incr = 2;
> +		break;
> +	case DP_PCON_DSC_ONE_BPP:
> +		pcon_dsc->bpp_precision_incr = 1;
> +		break;
> +	default :
> +		pcon_dsc->bpp_precision_incr = 0;
> +	}
> +}
> +
>  static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp)  {
>  	int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps; @@ -
> 6659,6 +6835,8 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
>  		    intel_dp->dfp.max_tmds_clock,
>  		    intel_dp->dfp.pcon_max_frl,
>  		    intel_dp->dfp.sink_max_frl);
> +
> +	intel_dp_get_pcon_dsc_cap(intel_dp);
>  }
> 
>  static void
> --
> 2.17.1

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RE: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder

[Shankar, Uma]

> -----Original Message-----
> From: Shankar, Uma
> Sent: Monday, October 19, 2020 5:02 AM
> To: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; Sharma, Swati2
> <swati2.sharma@intel.com>
> Subject: RE: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON
> encoder

Also it would be good to move to DRM Core.

> 
> 
> > -----Original Message-----
> > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> > Sent: Thursday, October 15, 2020 4:23 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma
> > <uma.shankar@intel.com>; Kulkarni, Vandita
> > <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; Sharma,
> > Swati2 <swati2.sharma@intel.com>
> > Subject: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1
> > PCON encoder
> >
> > This patch adds a helper function to read the DSC capabilities of the
> > HDMI2.1 PCon encoder. It also adds a new structure to store these
> > caps, which can then be used to get the PPS parameters for
> > PCON-HDMI2.1 sink pair. Which inturn will be used to take a call to
> > override the existing PPS-metadata, by either writing the entire new
> > PPS metadata, or by writing only the PPS override parameters.
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  16 ++
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 178 ++++++++++++++++++
> >  2 files changed, 194 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 6c69922313d6..23282695a47f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1292,6 +1292,21 @@ struct intel_dp_pcon_frl {
> >  	int trained_rate_gbps;
> >  };
> >
> > +struct intel_dp_pcon_dsc {
> > +	bool enc_support;
> > +	bool pps_override_support;
> > +	bool blk_prediction_support;
> > +	u8 version_major;
> > +	u8 version_minor;
> > +	u8 color_fmt_mask;
> > +	u8 color_depth_mask;
> > +	u8 max_slices;;
> > +	u8 max_slice_width;
> > +	u8 line_buf_bit_depth;
> > +	u8 bpp_precision_incr;
> > +	int rc_buf_size;
> > +};
> > +
> >  struct intel_dp {
> >  	i915_reg_t output_reg;
> >  	u32 DP;
> > @@ -1415,6 +1430,7 @@ struct intel_dp {
> >  	bool hobl_active;
> >
> >  	struct intel_dp_pcon_frl frl;
> > +	struct intel_dp_pcon_dsc pcon_dsc;
> >  };
> >
> >  enum lspcon_vendor {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index e6c4cb844e37..b4f8abaea607 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3882,6 +3882,182 @@ cpt_set_link_train(struct intel_dp *intel_dp,
> >  	intel_de_posting_read(dev_priv, intel_dp->output_reg);  }
> >
> > +void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) {
> > +	u8 buf;
> > +	u8 rc_buf_blk_size;
> > +	u8 max_slices = 0;
> > +
> > +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > +	struct intel_dp_pcon_dsc *pcon_dsc = &intel_dp->pcon_dsc;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENCODER, &buf)
> > < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_ENCODER\n");
> > +		return;
> > +	}
> > +	pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED;
> > +	pcon_dsc->pps_override_support = buf &
> > DP_PCON_DSC_PPS_ENC_OVERRIDE;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_VERSION, &buf)
> > < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_VERSION\n");
> > +		return;
> 
> If we fail here or in any of the subsequent calls below shouldn't we reset the dsc
> params saying DSC not supported. Else we may return with ex.
> pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED which
> would ideally not be right.
> 
> > +	}
> > +	pcon_dsc->version_major = (buf & DP_PCON_DSC_MAJOR_MASK) >>
> > +				  DP_PCON_DSC_MAJOR_SHIFT;
> > +	pcon_dsc->version_minor = (buf & DP_PCON_DSC_MINOR_MASK) >>
> > +				  DP_PCON_DSC_MINOR_SHIFT;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> > DP_PCON_DSC_RC_BUF_BLK_INFO, &buf) < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_RC_BUF_BLK_INFO\n");
> > +		return;
> > +	}
> > +
> > +	switch (buf & DP_PCON_DSC_RC_BUF_BLK_SIZE) {
> > +	case DP_PCON_DSC_RC_BUF_BLK_1KB :
> > +		rc_buf_blk_size = 1;
> > +		break;
> > +	case DP_PCON_DSC_RC_BUF_BLK_4KB :
> > +		rc_buf_blk_size = 4;
> > +		break;
> > +	case DP_PCON_DSC_RC_BUF_BLK_16KB :
> > +		rc_buf_blk_size = 16;
> > +		break;
> > +	case DP_PCON_DSC_RC_BUF_BLK_64KB :
> > +		rc_buf_blk_size = 64;
> > +		break;
> > +	default :
> > +		rc_buf_blk_size = 0;
> > +	}
> 
> It would be good if you create sub-functions for each of these aspects to make it
> more readable.
> 
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_RC_BUF_SIZE,
> > &buf) < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_RC_BUF_SIZE\n");
> > +		return;
> > +	}
> > +	/* storing rc_buf_size in bytes */
> > +	pcon_dsc->rc_buf_size = (buf + 1) * rc_buf_blk_size * 1024;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_SLICE_CAP_2,
> > &buf) < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_SLICE_CAP_2\n");
> > +		return;
> > +	}
> > +	if (buf & DP_PCON_DSC_24_PER_DSC_ENC)
> > +	       max_slices = 24;
> > +	else if (buf & DP_PCON_DSC_20_PER_DSC_ENC)
> > +		max_slices = 20;
> > +	else if (buf & DP_PCON_DSC_16_PER_DSC_ENC)
> > +		max_slices = 16;
> > +
> > +	if (max_slices == 0) {
> > +		if (drm_dp_dpcd_readb(&intel_dp->aux,
> > DP_PCON_DSC_SLICE_CAP_1,
> > +				      &buf) < 0) {
> > +			drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_SLICE_CAP_2\n");
> 
> Its SLICE_CAP_1.
> 
> > +			return;
> > +		}
> > +
> > +		if (buf & DP_PCON_DSC_12_PER_DSC_ENC)
> > +			max_slices = 12;
> > +		else if (buf & DP_PCON_DSC_10_PER_DSC_ENC)
> > +			max_slices = 10;
> > +		else if (buf & DP_PCON_DSC_8_PER_DSC_ENC)
> > +			max_slices = 8;
> > +		else if (buf & DP_PCON_DSC_6_PER_DSC_ENC)
> > +			max_slices = 6;
> > +		else if (buf & DP_PCON_DSC_4_PER_DSC_ENC)
> > +			max_slices = 4;
> > +		else if (buf & DP_PCON_DSC_2_PER_DSC_ENC)
> > +			max_slices = 2;
> > +		else if (buf & DP_PCON_DSC_1_PER_DSC_ENC)
> > +			max_slices = 1;
> 
> Use switch here as well.
> 
> > +	}
> > +
> > +	pcon_dsc->max_slices = max_slices;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BUF_BIT_DEPTH,
> > &buf) < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_BUF_BIT_DEPTH\n");
> > +		return;
> > +	}
> > +	switch (buf & DP_PCON_DSC_BIT_DEPTH_MASK) {
> > +	case DP_PCON_DSC_DEPTH_8_BITS :
> > +		pcon_dsc->line_buf_bit_depth = 8;
> > +		break;
> > +	case DP_PCON_DSC_DEPTH_9_BITS :
> > +		pcon_dsc->line_buf_bit_depth = 9;
> > +		break;
> > +	case DP_PCON_DSC_DEPTH_10_BITS :
> > +		pcon_dsc->line_buf_bit_depth = 10;
> > +		break;
> > +	case DP_PCON_DSC_DEPTH_11_BITS :
> > +		pcon_dsc->line_buf_bit_depth = 11;
> > +		break;
> > +	case DP_PCON_DSC_DEPTH_12_BITS :
> > +		pcon_dsc->line_buf_bit_depth = 12;
> > +		break;
> > +	case DP_PCON_DSC_DEPTH_13_BITS :
> > +		pcon_dsc->line_buf_bit_depth = 13;
> > +		break;
> > +	case DP_PCON_DSC_DEPTH_14_BITS :
> > +		pcon_dsc->line_buf_bit_depth = 14;
> > +		break;
> > +	case DP_PCON_DSC_DEPTH_15_BITS :
> > +		pcon_dsc->line_buf_bit_depth = 15;
> > +		break;
> > +	case DP_PCON_DSC_DEPTH_16_BITS :
> > +		pcon_dsc->line_buf_bit_depth = 16;
> > +		break;
> > +	default :
> > +		pcon_dsc->line_buf_bit_depth = 0;
> > +	}
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> > DP_PCON_DSC_BLOCK_PREDICTION, &buf) < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_BLOCK_PREDICTION\n");
> > +		return;
> > +	}
> > +	if (buf && DP_PCON_DSC_BLOCK_PRED_SUPPORT)
> > +		pcon_dsc->blk_prediction_support = true;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> > DP_PCON_DSC_ENC_COLOR_FMT_CAP, &buf) < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_ENC_COLOR_FMT_CAP\n");
> > +		return;
> > +	}
> > +	pcon_dsc->color_fmt_mask = buf;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> > DP_PCON_DSC_ENC_COLOR_DEPTH_CAP, &buf) < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_ENC_COLOR_DEPTH_CAP\n");
> > +		return;
> > +	}
> > +	pcon_dsc->color_depth_mask = buf;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux,
> > DP_PCON_DSC_MAX_SLICE_WIDTH, &buf) < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_MAX_SLICE_WIDTH\n");
> > +		return;
> > +	}
> > +	pcon_dsc->max_slice_width = buf;;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BPP_INCR, &buf)
> > < 0) {
> > +		drm_err(&i915->drm, "Failed to read
> > DP_PCON_DSC_BPP_INCR\n");
> > +		return;
> > +	}
> > +	switch(buf & DP_PCON_DSC_BPP_INCR_MASK) {
> > +	case DP_PCON_DSC_ONE_16TH_BPP:
> > +		pcon_dsc->bpp_precision_incr = 16;
> > +		break;
> > +	case DP_PCON_DSC_ONE_8TH_BPP:
> > +		pcon_dsc->bpp_precision_incr = 8;
> > +		break;
> > +	case DP_PCON_DSC_ONE_4TH_BPP:
> > +		pcon_dsc->bpp_precision_incr = 4;
> > +		break;
> > +	case DP_PCON_DSC_ONE_HALF_BPP:
> > +		pcon_dsc->bpp_precision_incr = 2;
> > +		break;
> > +	case DP_PCON_DSC_ONE_BPP:
> > +		pcon_dsc->bpp_precision_incr = 1;
> > +		break;
> > +	default :
> > +		pcon_dsc->bpp_precision_incr = 0;
> > +	}
> > +}
> > +
> >  static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp)  {
> >  	int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps; @@ -
> > 6659,6 +6835,8 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
> >  		    intel_dp->dfp.max_tmds_clock,
> >  		    intel_dp->dfp.pcon_max_frl,
> >  		    intel_dp->dfp.sink_max_frl);
> > +
> > +	intel_dp_get_pcon_dsc_cap(intel_dp);
> >  }
> >
> >  static void
> > --
> > 2.17.1

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Re: [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1

[Nautiyal, Ankit K]

Thanks Uma for the review and highlighting the issues in the patch-series.

I agree to most of the comments and will be addressing comments and 
corrections in the next  version shortly.

Please find my response inline.

On 10/19/2020 2:17 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1
>>
>> From: Swati Sharma <swati2.sharma@intel.com>
>>
>> The HDMI2.1 extends HFVSBD (HDMI Forum Vendor Specific Data block) to have
> Typo in HFVSDB


Will fix in the next patch set.

>> fields related to newly defined methods of FRL (Fixed Rate Link) levels, number
>> of lanes supported, DSC Color bit depth, VRR min/max, FVA (Fast Vactive), ALLM
>> etc.
>>
>> This patch adds the new HFVSDB fields that are required for HDMI2.1.
>>
>> Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++
>>   1 file changed, 30 insertions(+)
>>
>> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index
>> b27a0e2169c8..1cc5c2c73282 100644
>> --- a/include/drm/drm_edid.h
>> +++ b/include/drm/drm_edid.h
>> @@ -229,6 +229,36 @@ struct detailed_timing {
>>       DRM_EDID_YCBCR420_DC_36 | \
>>       DRM_EDID_YCBCR420_DC_30)
>>
>> +/* HDMI 2.1 additional fields */
>> +#define DRM_EDID_MAX_FRL_RATE_MASK0xf0
>> +#define DRM_EDID_FAPA_START_LOCATION(1 << 0)
>> +#define DRM_EDID_ALLM(1 << 1)
>> +#define DRM_EDID_FVA(1 << 2)
>> +
>> +/* Deep Color specific */
>> +#define DRM_EDID_DC_30BIT_420(1 << 0)
>> +#define DRM_EDID_DC_36BIT_420(1 << 1)
>> +#define DRM_EDID_DC_48BIT_420(1 << 2)
>> +
>> +/* VRR specific */
>> +#define DRM_EDID_CNMVRR(1 << 3)
>> +#define DRM_EDID_CINEMA_VRR(1 << 4)
>> +#define DRM_EDID_MDELTA(1 << 5)
>> +#define DRM_EDID_VRR_MAX_UPPER_MASK0xc0
>> +#define DRM_EDID_VRR_MAX_LOWER_MASK0xff
>> +#define DRM_EDID_VRR_MIN_MASK0x3f
>> +
>> +/* DSC specific */
>> +#define DRM_EDID_DSC_10BPC(1 << 0)
>> +#define DRM_EDID_DSC_12BPC(1 << 1)
>> +#define DRM_EDID_DSC_16BPC(1 << 2)
>> +#define DRM_EDID_DSC_ALL_BPP(1 << 3)
>> +#define DRM_EDID_DSC_NATIVE_420(1 << 6)
>> +#define DRM_EDID_DSC_1P2(1 << 7)
>> +#define DRM_EDID_DSC_MAX_FRL_RATE0xf
> This should be set as mask and made it as 0xf0

Agreed, will take care in the next version.

Regards,

Ankit

>
>> +#define DRM_EDID_DSC_MAX_SLICES0xf
>> +#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES0x3f
>> +
>>   /* ELD Header Block */
>>   #define DRM_ELD_HEADER_BLOCK_SIZE4
>>
>> --
>> 2.17.1
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Re: [RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block

[Nautiyal, Ankit K]

On 10/19/2020 2:17 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block
>>
>> From: Swati Sharma <swati2.sharma@intel.com>
>>
>> This patch parses MAX_FRL field to get the MAX rate in Gbps that the HDMI 2.1
>> panel can support in FRL mode. Source need this field to determine the optimal
>> rate between the source and sink during FRL training.
>>
>> Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/drm_edid.c  | 51 +++++++++++++++++++++++++++++++++++++
>>   include/drm/drm_connector.h |  6 +++++
>>   2 files changed, 57 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
>> 631125b46e04..8afb136e73f5 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -4849,6 +4849,52 @@ static void drm_parse_vcdb(struct drm_connector
>> *connector, const u8 *db)
>>   info->rgb_quant_range_selectable = true;  }
>>
>> +static
>> +void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8
>> +*max_rate_per_lane) {
>> +switch(max_frl_rate) {
>> +case 1:
>> +*max_lanes = 3;
>> +*max_rate_per_lane = 3;
>> +break;
>> +case 2:
>> +*max_lanes = 3;
>> +*max_rate_per_lane = 6;
>> +break;
>> +case 3:
>> +*max_lanes = 4;
>> +*max_rate_per_lane = 6;
>> +break;
>> +case 4:
>> +*max_lanes = 4;
>> +*max_rate_per_lane = 8;
>> +break;
>> +case 5:
>> +*max_lanes = 4;
>> +*max_rate_per_lane = 10;
>> +break;
>> +case 6:
>> +*max_lanes = 4;
>> +*max_rate_per_lane = 12;
>> +break;
>> +case 0:
>> +default:
>> +*max_lanes = 0;
>> +*max_rate_per_lane = 0;
>> +}
>> +}
>> +
>> +static void drm_parse_hdmi_21_additional_fields(struct drm_connector
>> *connector,
>> +const u8 *db)
>> +{
>> +struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
>> +u8 max_frl_rate;
>> +
>> +max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;
> This seems wrong,  we need to right shift this by 4 to get the max_frl_rate.


Thanks Uma for catching this.

This was correct in the first patch, bug crept in while restructuring 
the code. Will fix in the next patchset.

>
>> +drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
>> +     &hdmi->max_frl_rate_per_lane);
> We can just pass the connecter and drm_get_max_frl_rate can fill the respective fields.


I wanted to make this generic, as this function is to be re-used in case 
of parsing DSC max frl also, so I just passed the lanes and rate per 
lane to be filled.


>
>> +}
>> +
>>   static void drm_parse_ycbcr420_deep_color_info(struct drm_connector
>> *connector,
>>          const u8 *db)
>>   {
>> @@ -4902,6 +4948,11 @@ static void drm_parse_hdmi_forum_vsdb(struct
>> drm_connector *connector,
>>   }
>>   }
>>
>> +if (hf_vsdb[7]) {
>> +    DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
>> +    drm_parse_hdmi_21_additional_fields(connector, hf_vsdb);
> We can get rid of this extra wrapper.


Agreed. Will take care of this in the next patchset.

Thanks & Regards,

Ankit

>
>> +}
>> +
>>   drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);  }
>>
>> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index
>> 928136556174..f351bf10c076 100644
>> --- a/include/drm/drm_connector.h
>> +++ b/include/drm/drm_connector.h
>> @@ -207,6 +207,12 @@ struct drm_hdmi_info {
>>
>>   /** @y420_dc_modes: bitmap of deep color support index */
>>   u8 y420_dc_modes;
>> +
>> +/** @max_frl_rate_per_lane: support fixed rate link */
>> +u8 max_frl_rate_per_lane;
>> +
>> +/** @max_lanes: supported by sink */
>> +u8 max_lanes;
>>   };
>>
>>   /**
>> --
>> 2.17.1
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Re: [RFC 03/13] drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON

[Nautiyal, Ankit K]

On 10/19/2020 3:03 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 03/13] drm/dp_helper: Add FRL training support for a DP-HDMI2.1
>> PCON
> You can name this patch as "Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON"

Makes sense, will change the commit msg in the next version.


>
>> This patch adds support for configuring a PCON device, connected as a DP
>> branched device to enable FRL Link training with a HDMI2.1 + sink.
>>
>> v2: Minor changes:
>> -removed unnecessary argument supplied to a drm helper function.
>> -fixed return value for max frl read from pcon.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/drm_dp_helper.c | 305 ++++++++++++++++++++++++++++++++
>>   include/drm/drm_dp_helper.h     |  80 +++++++++
>>   2 files changed, 385 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>> b/drivers/gpu/drm/drm_dp_helper.c index 14ddf28ecac0..df858533dbf7 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -2591,3 +2591,308 @@ void drm_dp_vsc_sdp_log(const char *level, struct
>> device *dev,  #undef DP_SDP_LOG  }  EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
>> +
>> +/**
>> + * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
>> + * @dpcd: DisplayPort configuration data
>> + * @port_cap: port capabilities
>> + *
>> + * Returns maximum frl bandwidth supported by PCON in GBPS,
>> + * returns 0 if not supported.
>> + **/
>> +int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>> +       const u8 port_cap[4])
>> +{
>> +int bw;
>> +u8 buf;
>> +
>> +buf = port_cap[2];
>> +bw = buf & DP_PCON_MAX_FRL_BW;
>> +
>> +switch (bw) {
>> +case DP_PCON_MAX_9GBPS:
>> +return 9;
>> +case DP_PCON_MAX_18GBPS:
>> +return 18;
>> +case DP_PCON_MAX_24GBPS:
>> +return 24;
>> +case DP_PCON_MAX_32GBPS:
>> +return 32;
>> +case DP_PCON_MAX_40GBPS:
>> +return 40;
>> +case DP_PCON_MAX_48GBPS:
>> +return 48;
>> +case DP_PCON_MAX_0GBPS:
>> +default:
>> +return 0;
>> +}
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
>> +
>> +/**
>> + * drm_dp_get_hdmi_max_frl_bw() - maximum frl supported by HDMI Sink
>> + * @aux: DisplayPort AUX channel
>> + *
>> + * Returns maximum frl bandwidth supported by HDMI in Gbps on success,
>> + * returns 0, if not supported.
>> + **/
>> +int drm_dp_get_hdmi_max_frl_bw(struct drm_dp_aux *aux) {
> s/hdmi/hdmi_sink/ will make it clear that we are referring to sink here.


Agreed. will change the name as suggested in next version.

>
>> +u8 buf;
>> +int bw, ret;
>> +
>> +ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_SINK, &buf);
>> +if (ret < 0)
>> +return 0;
>> +bw = buf & DP_HDMI_SINK_LINK_BW;
>> +
>> +switch (bw) {
>> +case DP_HDMI_SINK_BW_9GBPS:
>> +return 9;
>> +case DP_HDMI_SINK_BW_18GBPS:
>> +return 18;
>> +case DP_HDMI_SINK_BW_24GBPS:
>> +return 24;
>> +case DP_HDMI_SINK_BW_32GBPS:
>> +return 32;
>> +case DP_HDMI_SINK_BW_40GBPS:
>> +return 40;
>> +case DP_HDMI_SINK_BW_48GBPS:
>> +return 48;
>> +case DP_HDMI_SINK_BW_0GBPS:
>> +default:
>> +return 0;
>> +}
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_get_hdmi_max_frl_bw);
>> +
>> +/**
>> + * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
>> + * @aux: DisplayPort AUX channel
>> + *
>> + * Returns 0 if success, else returns negative error code.
>> + **/
>> +int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool
>> +enable_frl_ready_hpd) {
>> +int ret;
>> +u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
>> + DP_PCON_ENABLE_LINK_FRL_MODE;
>> +
>> +if (enable_frl_ready_hpd)
>> +buf |= DP_PCON_ENABLE_HPD_READY;
>> +
>> +ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
>> +
>> +return ret;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
>> +
>> +/**
>> + * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
>> + * @aux: DisplayPort AUX channel
>> + *
>> + * Returns true if success, else returns false.
>> + **/
>> +bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) {
>> +int ret;
>> +u8 buf;
>> +
>> +ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
>> +if (ret < 0)
>> +return false;
>> +
>> +if (buf & DP_PCON_FRL_READY)
>> +return true;
>> +
>> +return false;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
>> +
>> +/**
>> + * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
>> + * @aux: DisplayPort AUX channel
>> + * max_frl_mask: mask for selecting the bandwidths supported by source,
> @missing from variable and its not a mask here but an absolute value.


You are right, I will fix this in the next version.

>
>> + * to be tried by Pcon f/w.
>> + * @concurrent_mode: true if concurrent mode or operation is required,
>> + * false otherwise.
>> + *
>> + * Returns 0 if success, else returns negative error code.
>> + **/
>> +
>> +int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
>> +bool concurrent_mode)
>> +{
>> +int ret;
>> +u8 buf;
>> +
>> +ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
>> +if (ret < 0)
>> +return ret;
>> +
>> +if (concurrent_mode)
>> +buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
>> +else
>> +buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
>> +
>> +switch (max_frl_gbps) {
>> +case 9:
>> +buf |=  DP_PCON_ENABLE_MAX_BW_9GBPS;
>> +break;
>> +case 18:
>> +buf |=  DP_PCON_ENABLE_MAX_BW_18GBPS;
>> +break;
>> +case 24:
>> +buf |=  DP_PCON_ENABLE_MAX_BW_24GBPS;
>> +break;
>> +case 32:
>> +buf |=  DP_PCON_ENABLE_MAX_BW_32GBPS;
>> +break;
>> +case 40:
>> +buf |=  DP_PCON_ENABLE_MAX_BW_40GBPS;
>> +break;
>> +case 48:
>> +buf |=  DP_PCON_ENABLE_MAX_BW_48GBPS;
>> +break;
>> +case 0:
>> +buf |=  DP_PCON_ENABLE_MAX_BW_0GBPS;
>> +break;
>> +default:
>> +return -EINVAL;
>> +}
>> +
>> +ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
>> +if (ret < 0)
>> +return ret;
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
>> +
>> +/**
>> + * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
>> + * @aux: DisplayPort AUX channel
>> + * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
>> + * @extended_train_mode : true for Extended Mode, false for Normal Mode.
>> + * In Normal mode, the PCON tries each frl bw from the max_frl_mask
>> +starting
>> + * from min, and stops when link training is successful. In Extended
>> +mode, all
>> + * frl bw selected in the mask are trained by the PCON.
>> + *
>> + * Returns 0 if success, else returns negative error code.
>> + **/
>> +int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
>> +bool extended_train_mode)
>> +{
>> +int ret;
>> +u8 buf = 0;
>> +
>> +buf |= max_frl_mask;
> Can just initialize buf to max _frl_mask.


Agreed.

>
>> +
>> +if (extended_train_mode)
>> +buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
>> +
>> +ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
>> +if (ret < 0)
>> +return ret;
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
>> +
>> +/**
>> + * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
>> + * @aux: DisplayPort AUX channel
>> + *
>> + * Returns 0 if success, else returns negative error code.
>> + **/
>> +int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) {
>> +int ret;
>> +
>> +ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
>> +if (ret < 0)
>> +return ret;
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
>> +
>> +/**
>> + * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
>> + * @aux: DisplayPort AUX channel
>> + *
>> + * Returns 0 if success, else returns negative error code.
>> + **/
>> +int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) {
>> +int ret;
>> +u8 buf = 0;
>> +
>> +ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
>> +if (ret < 0)
>> +return ret;
>> +if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
>> +DRM_DEBUG_KMS("PCON in Autonomous mode, can't enable
>> FRL\n");
>> +return -EINVAL;
>> +}
>> +buf |= DP_PCON_ENABLE_HDMI_LINK;
>> +ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
>> +if (ret < 0)
>> +return ret;
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
>> +
>> +/**
>> + * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is
>> active.
>> + * @aux: DisplayPort AUX channel
>> + *
>> + * Returns true if link is active else returns false.
>> + **/
>> +bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) {
>> +u8 buf;
>> +int ret;
>> +
>> +ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
>> +if (ret < 0)
>> +return false;
>> +
>> +return buf & DP_PCON_HDMI_TX_LINK_ACTIVE; }
>> +EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
>> +
>> +/**
>> + * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
>> + * @aux: DisplayPort AUX channel
>> + * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
>> + * Valid only if the MODE returned is FRL. For Normal Link training
>> +mode
>> + * only 1 of the bits will be set, but in case of Extended mode, more
>> +than
>> + * one bits can be set.
>> + *
>> + * Returns the link mode : TMDS or FRL on success, else retunes
> Typo in returns

Will fix in the next version.


>
>> +negative error
>> + * code.
>> + **/
>> +int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8
>> +*frl_trained_mask) {
>> +u8 buf;
>> +int mode;
>> +int ret;
>> +
>> +ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS,
>> &buf);
>> +if (ret < 0)
>> +return ret;
>> +
>> +mode = buf & DP_PCON_HDMI_LINK_MODE;
>> +
>> +if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
> Should be bitwise and not logical and right ?. Also this mask is a bit ambigious,
> we could just use absolute bandwidth which would be more clear.

Actually these are two conditions here. First condition is to check if 
the frl_trained_mask is not a NULL pointer.

Second is to check if the FRL mode Hdmi Link is in FRL mode.

We need to set the FRL link training mask, only if the HDMI link is in 
FRL mode.

>
>> +*frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW)
>>>> 1;
>> +
>> +return mode;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>> f55a9d1320ca..d6f79b2d1287 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -411,6 +411,17 @@ struct drm_device;
>>   # define DP_DS_10BPC            1
>>   # define DP_DS_12BPC            2
>>   # define DP_DS_16BPC            3
>> +/* HDMI2.1 PCON FRL CONFIGURATION */
>> +# define DP_PCON_MAX_FRL_BW                 (7 << 2)
>> +# define DP_PCON_MAX_0GBPS                  (0 << 2)
>> +# define DP_PCON_MAX_9GBPS                  (1 << 2)
>> +# define DP_PCON_MAX_18GBPS                 (2 << 2)
>> +# define DP_PCON_MAX_24GBPS                 (3 << 2)
>> +# define DP_PCON_MAX_32GBPS                 (4 << 2)
>> +# define DP_PCON_MAX_40GBPS                 (5 << 2)
>> +# define DP_PCON_MAX_48GBPS                 (6 << 2)
>> +# define DP_PCON_SOURCE_CTL_MODE            (1 << 5)
>> +
>>   /* offset 3 for DVI */
>>   # define DP_DS_DVI_DUAL_LINK    (1 << 1)
>>   # define DP_DS_DVI_HIGH_COLOR_DEPTH    (1 << 2)
>> @@ -1053,6 +1064,61 @@ struct drm_device;
>>   #define DP_CEC_RX_MESSAGE_BUFFER               0x3010
>>   #define DP_CEC_TX_MESSAGE_BUFFER               0x3020
>>   #define DP_CEC_MESSAGE_BUFFER_LENGTH             0x10
>> +/* PROTOCOL CONVERSION HDMI SINK */
>> +#define DP_PCON_HDMI_SINK                      0x3035
>> +# define DP_HDMI_SINK_LINK_BW                  (7 << 0)
>> +# define DP_HDMI_SINK_BW_0GBPS       0
>> +# define DP_HDMI_SINK_BW_9GBPS       1
>> +# define DP_HDMI_SINK_BW_18GBPS       2
>> +# define DP_HDMI_SINK_BW_24GBPS       3
>> +# define DP_HDMI_SINK_BW_32GBPS       4
>> +# define DP_HDMI_SINK_BW_40GBPS       5
>> +# define DP_HDMI_SINK_BW_48GBPS       6
>> +
>> +/* PCON CONFIGURE-1 FRL FOR HDMI SINK */
>> +#define DP_PCON_HDMI_LINK_CONFIG_1             0x305A
>> +# define DP_PCON_ENABLE_MAX_FRL_BW             (7 << 0)
>> +# define DP_PCON_ENABLE_MAX_BW_0GBPS       0
>> +# define DP_PCON_ENABLE_MAX_BW_9GBPS       1
>> +# define DP_PCON_ENABLE_MAX_BW_18GBPS       2
>> +# define DP_PCON_ENABLE_MAX_BW_24GBPS       3
>> +# define DP_PCON_ENABLE_MAX_BW_32GBPS       4
>> +# define DP_PCON_ENABLE_MAX_BW_40GBPS       5
>> +# define DP_PCON_ENABLE_MAX_BW_48GBPS       6
>> +# define DP_PCON_ENABLE_SOURCE_CTL_MODE       (1 << 3)
>> +# define DP_PCON_ENABLE_CONCURRENT_LINK       (1 << 4)
>> +# define DP_PCON_ENABLE_LINK_FRL_MODE         (1 << 5)
>> +# define DP_PCON_ENABLE_HPD_READY      (1 << 6)
>> +# define DP_PCON_ENABLE_HDMI_LINK             (1 << 7)
>> +
>> +/* PCON CONFIGURE-2 FRL FOR HDMI SINK */
>> +#define DP_PCON_HDMI_LINK_CONFIG_2            0x305B
>> +# define DP_PCON_MAX_LINK_BW_MASK             (0x3F << 0)
>> +# define DP_PCON_FRL_BW_MASK_9GBPS            (1 << 0)
>> +# define DP_PCON_FRL_BW_MASK_18GBPS           (1 << 1)
>> +# define DP_PCON_FRL_BW_MASK_24GBPS           (1 << 2)
>> +# define DP_PCON_FRL_BW_MASK_32GBPS           (1 << 3)
>> +# define DP_PCON_FRL_BW_MASK_40GBPS           (1 << 4)
>> +# define DP_PCON_FRL_BW_MASK_48GBPS           (1 << 5)
>> +# define DP_PCON_FRL_LINK_TRAIN_EXTENDED      (1 << 6)
>> +
>> +/* PCON HDMI LINK STATUS */
>> +#define DP_PCON_HDMI_TX_LINK_STATUS           0x303B
>> +# define DP_PCON_HDMI_TX_LINK_ACTIVE          (1 << 0)
>> +# define DP_PCON_FRL_READY      (1 << 1)
>> +
>> +/* PCON HDMI POST FRL STATUS */
>> +#define DP_PCON_HDMI_POST_FRL_STATUS          0x3036
>> +# define DP_PCON_HDMI_LINK_MODE               (1 << 0)
>> +# define DP_PCON_HDMI_MODE_TMDS               0
>> +# define DP_PCON_HDMI_MODE_FRL                1
>> +# define DP_PCON_HDMI_FRL_TRAINED_BW          (0x3F << 1)
> This should be 0x3 < 1
>
>> +# define DP_PCON_FRL_TRAINED_BW_9GBPS      (1 << 1)
>> +# define DP_PCON_FRL_TRAINED_BW_18GBPS      (1 << 2)
>> +# define DP_PCON_FRL_TRAINED_BW_24GBPS      (1 << 3)
>> +# define DP_PCON_FRL_TRAINED_BW_32GBPS      (1 << 4)
>> +# define DP_PCON_FRL_TRAINED_BW_40GBPS      (1 << 5)
>> +# define DP_PCON_FRL_TRAINED_BW_48GBPS      (1 << 6)
>>
>>   #define DP_PROTOCOL_CONVERTER_CONTROL_00x3050 /* DP 1.3
>> */
>>   # define DP_HDMI_DVI_OUTPUT_CONFIG(1 << 0) /* DP 1.3 */
>> @@ -1967,4 +2033,18 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux
>> *aux,
>>   struct drm_dp_phy_test_params *data);  int
>> drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>>   struct drm_dp_phy_test_params *data, u8
>> dp_rev);
>> +int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>> +       const u8 port_cap[4]);
>> +int drm_dp_get_hdmi_max_frl_bw(struct drm_dp_aux *aux); int
>> +drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool
>> +enable_frl_ready_hpd); bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux
>> +*aux); int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int
>> max_frl_gbps,
>> +bool concurrent_mode);
>> +int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
>> +bool extended_train_mode);
>> +int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); int
>> +drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
>> +
>> +bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); int
>> +drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8
>> +*frl_trained_mask);
> Leave a blank line here.

Agreed. Will take care in the next version.


Thanks & Regards,

Ankit

>
>>   #endif /* _DRM_DP_HELPER_H_ */
>> --
>> 2.17.1
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Re: [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure

[Nautiyal, Ankit K]

On 10/19/2020 3:11 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure
>>
>> HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and by the
>> sink.
>>
>> This patch captures these in dfp cap structure in intel_dp and uses these to
>> prune connector modes that cannot be supported by the PCON and sink FRL
>> bandwidth.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 33 +++++++++++++++++--
>>   2 files changed, 32 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 0b5df8e44966..e2f58d0575a2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1398,6 +1398,7 @@ struct intel_dp {
>>   struct {
>>   int min_tmds_clock, max_tmds_clock;
>>   int max_dotclock;
>> +int pcon_max_frl, sink_max_frl;
> Append it with bw or rate.


Agreed, will add 'bw' for clarity.

>
>>   u8 max_bpc;
>>   bool ycbcr_444_to_420;
>>   } dfp;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 0902a9aeeda1..cd6934f28f32 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -683,6 +683,24 @@ intel_dp_mode_valid_downstream(struct
>> intel_connector *connector,
>>   const struct drm_display_info *info = &connector->base.display_info;
>>   int tmds_clock;
>>
>> +/* If PCON and HDMI2.1 sink both support FRL MODE, check FRL
> Use multi line comment style.

Agreed. Will take care in next version.


>
>> + * bandwidth constraints.
>> + */
>> +if (intel_dp->dfp.pcon_max_frl) {
>> +int target_bw;
>> +int max_frl_bw;
>> +int bpp = intel_dp_mode_min_output_bpp(&connector->base,
>> mode);
>> +
>> +target_bw = bpp * DIV_ROUND_UP(target_clock, 1000000);
> To avoid any roundup errors, it would be good to multiple max_frl_bw by 1000000 than dividing target_clock

Alright. Will take care of this in next version.


Thanks & Regards,

Ankit

>
>> +
>> +max_frl_bw = min(intel_dp->dfp.pcon_max_frl,
>> + intel_dp->dfp.sink_max_frl);
>> +if (target_bw > max_frl_bw)
>> +return MODE_CLOCK_HIGH;
>> +
>> +return MODE_OK;
>> +}
>> +
>>   if (intel_dp->dfp.max_dotclock &&
>>       target_clock > intel_dp->dfp.max_dotclock)
>>   return MODE_CLOCK_HIGH;
>> @@ -6383,13 +6401,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
>>    intel_dp->downstream_ports,
>>    edid);
>>
>> +intel_dp->dfp.pcon_max_frl =
>> +drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
>> +   intel_dp->downstream_ports);
>> +
>> +intel_dp->dfp.sink_max_frl =
>> +drm_dp_get_hdmi_max_frl_bw(&intel_dp->aux);
>> +
>>   drm_dbg_kms(&i915->drm,
>> -    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d,
>> TMDS clock %d-%d\n",
>> +    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d,
>> TMDS clock
>> +%d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n",
>>       connector->base.base.id, connector->base.name,
>>       intel_dp->dfp.max_bpc,
>>       intel_dp->dfp.max_dotclock,
>>       intel_dp->dfp.min_tmds_clock,
>> -    intel_dp->dfp.max_tmds_clock);
>> +    intel_dp->dfp.max_tmds_clock,
>> +    intel_dp->dfp.pcon_max_frl,
>> +    intel_dp->dfp.sink_max_frl);
>>   }
>>
>>   static void
>> @@ -6479,6 +6505,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>>   intel_dp->dfp.min_tmds_clock = 0;
>>   intel_dp->dfp.max_tmds_clock = 0;
>>
>> +intel_dp->dfp.pcon_max_frl = 0;
>> +intel_dp->dfp.sink_max_frl = 0;
>> +
>>   intel_dp->dfp.ycbcr_444_to_420 = false;
>>   connector->base.ycbcr_420_allowed = false;  }
>> --
>> 2.17.1
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Re: [RFC 05/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON

[Nautiyal, Ankit K]

On 10/19/2020 3:44 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 05/13] drm/i915: Add support for starting FRL training for HDMI2.1
>> via PCON
>>
>> This patch adds functions to start FRL training for an HDMI2.1 sink, connected via
>> a PCON as a DP branch device.
>> This patch also adds a new structure for storing frl training related data, when
>> FRL training is completed.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_types.h    |   7 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 200 ++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h       |   2 +
>>   3 files changed, 209 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index e2f58d0575a2..6c69922313d6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1287,6 +1287,11 @@ struct intel_dp_compliance {
>>   u8 test_lane_count;
>>   };
>>
>> +struct intel_dp_pcon_frl {
>> +bool is_trained;
>> +int trained_rate_gbps;
>> +};
>> +
>>   struct intel_dp {
>>   i915_reg_t output_reg;
>>   u32 DP;
>> @@ -1408,6 +1413,8 @@ struct intel_dp {
>>
>>   bool hobl_failed;
>>   bool hobl_active;
>> +
>> +struct intel_dp_pcon_frl frl;
>>   };
>>
>>   enum lspcon_vendor {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index cd6934f28f32..c1342b5e7781 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2885,6 +2885,9 @@ static void intel_dp_prepare(struct intel_encoder
>> *encoder,
>>   intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
>>   else
>>   intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
>> +
>> +intel_dp->frl.is_trained = false;
>> +intel_dp->frl.trained_rate_gbps = 0;
>>   }
>>   }
>>
>> @@ -3781,6 +3784,9 @@ static void intel_disable_dp(struct intel_atomic_state
>> *state,
>>   intel_edp_backlight_off(old_conn_state);
>>   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>>   intel_edp_panel_off(intel_dp);
>> +
>> +intel_dp->frl.is_trained = false;
>> +intel_dp->frl.trained_rate_gbps = 0;
>>   }
>>
>>   static void g4x_disable_dp(struct intel_atomic_state *state, @@ -3876,6
>> +3882,200 @@ cpt_set_link_train(struct intel_dp *intel_dp,
>>   intel_de_posting_read(dev_priv, intel_dp->output_reg);  }
>>
>> +static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp) {
>> +int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps;
>> +
>> +max_link_clock = intel_dp_max_link_rate(intel_dp);
>> +max_lanes = intel_dp_max_lane_count(intel_dp);
>> +max_rate_khz = intel_dp_max_data_rate(max_link_clock, max_lanes);
>> +max_rate_gbps = 8 * DIV_ROUND_UP(max_rate_khz, 1000000);
>> +
>> +return max_rate_gbps;
>> +}
>> +
>> +static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) {
>> +int bw_gbps[] = {9, 18, 24, 32, 40, 48};
>> +int i;
>> +
>> +for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
>> +if (frl_bw_mask & (1 << i))
>> +return bw_gbps[i];
>> +}
>> +return 0;
>> +}
>> +
>> +static int intel_dp_pcon_set_frl_mask(int max_frl) {
>> +int max_frl_mask = 0;
>> +
>> +switch (max_frl) {
>> +case 48:
>> +max_frl_mask |= DP_PCON_FRL_BW_MASK_48GBPS;
> Just say it as return DP_PCON_FRL_BW_MASK_48GBPS.
> Do it universally.


Makes sense. Will change this in next version.

>
>> +break;
>> +case 40:
>> +max_frl_mask |= DP_PCON_FRL_BW_MASK_40GBPS;
>> +break;
>> +case 32:
>> +max_frl_mask |= DP_PCON_FRL_BW_MASK_32GBPS;
>> +break;
>> +case 24:
>> +max_frl_mask |= DP_PCON_FRL_BW_MASK_24GBPS;
>> +break;
>> +case 18:
>> +max_frl_mask |= DP_PCON_FRL_BW_MASK_18GBPS;
>> +break;
>> +case 9:
>> +max_frl_mask |= DP_PCON_FRL_BW_MASK_9GBPS;
>> +break;
>> +default:
>> +max_frl_mask = 0;
>> +}
>> +
>> +return max_frl_mask;
>> +}
>> +
>> +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) {
>> +struct intel_connector *intel_connector = intel_dp->attached_connector;
>> +struct drm_connector *connector = &intel_connector->base;
>> +
>> +return (connector->display_info.hdmi.max_frl_rate_per_lane *
>> +connector->display_info.hdmi.max_lanes);
>> +}
>> +
>> +static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
>> +{ #define PCON_EXTENDED_TRAIN_MODE true#define
>> PCON_CONCURRENT_MODE
>> +true #define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE #define
>> +PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE #define
> Don't use true instead 1 < 0 as true is not the right thing to be used here.


Alright. I think you mean to use (1 > 0) as true here.

Will use (1 > 0) instead of true in the macro.

>
>> +TIMEOUT_FRL_READY_MS 500 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
>> +
>> +struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> +int max_frl, max_pcon_frl, max_sink_frl, max_rate_gbps, max_frl_edid,
>> ret;
>> +u8 max_frl_mask = 0, frl_trained_mask;
>> +bool is_active;
>> +
>> +ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
>> +if (ret < 0)
>> +return ret;
>> +
>> +max_rate_gbps = intel_dp_get_max_rate_gbps(intel_dp);
>> +drm_dbg(&i915->drm, "Source max rate = %d Gbps\n", max_rate_gbps);
>> +
>> +max_pcon_frl = intel_dp->dfp.pcon_max_frl;
> Append it with rate or bw.


Agreed, will be using it in the next version.

>
>> +drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl);
>> +
>> +/* Double Check from HDMI SINK EDID */
>> +max_frl_edid = intel_dp_hdmi_sink_max_frl(intel_dp);
>> +drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n",
>> +max_frl_edid);
>> +
>> +max_sink_frl = intel_dp->dfp.sink_max_frl;
>> +drm_dbg(&i915->drm, "Sink max rate from PCON = %d Gbps\n",
>> +max_sink_frl);
>> +
>> +/* TODO MAX SINK FRL from PCON is not enumerated. Using MAX FRL
>> value
> Use multi line comment style.
Agreed.
>
>> + * directly from EDID. Need to confirm from Spec.
>> + */
>> +max_frl = min(max_rate_gbps, min(max_frl_edid, max_pcon_frl));
>> +
>> +if (max_frl <= 0)
>> +return -EINVAL;
>> +
>> +ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
>> +if (ret < 0)
>> +return ret;
>> +/* Wait for PCON to be FRL Ready */
>> +wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true,
>> +TIMEOUT_FRL_READY_MS);
>> +
>> +if (!is_active)
>> +return -ETIMEDOUT;
>> +
>> +max_frl_mask = intel_dp_pcon_set_frl_mask(max_frl);
>> +ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl,
>> PCON_SEQUENTIAL_MODE);
>> +if (ret < 0)
>> +return ret;
>> +ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_mask,
>> PCON_NORMAL_TRAIN_MODE);
>> +if (ret < 0)
>> +return ret;
>> +ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
>> +if (ret < 0)
>> +return ret;
>> +/*
>> + * Wait for FRL to be completed
>> + * Check if the HDMI Link is up and active.
>> + */
>> +wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) ==
>> +true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
>> +
>> +if (!is_active)
>> +return -ETIMEDOUT;
>> +/*
>> + * Verify HDMI Link configuration shows FRL Mode.
>> + */
>> +if (DP_PCON_HDMI_MODE_FRL !=
>> drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask)) {
>> +drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL
>> Mode\n");
>> +return -EINVAL;
>> +}
>> +drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK =
>> %u\n",
>> +max_frl_mask, frl_trained_mask);
>> +
>> +/*
>> + * Read HDMI_LINK_STATUS_TRAINED 0x2005 bit 5
>> + * TODO: Details not mentioned in spec. Need to check.
>> + */
>> +
>> +intel_dp->frl.trained_rate_gbps =
>> intel_dp_pcon_get_frl_mask(frl_trained_mask);
>> +intel_dp->frl.is_trained = true;
>> +drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n",
>> +intel_dp->frl.trained_rate_gbps);
>> +
>> +return 0;
>> +}
>> +
>> +static bool intel_dp_is_frl_required(struct intel_dp *intel_dp) {
>> +if (!intel_dp->frl.is_trained)
>> +return true;
>> +/*
>> + * #TODO check if the mode really required FRL or can work
>> + * with TMDS mode.
>> + */
>> +
>> +return false;
>> +}
>> +
>> +static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) {
>> +if (drm_dp_is_branch(intel_dp->dpcd) &&
>> +    intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
>> +return true;
>> +
>> +return false;
>> +}
>> +
>> +void intel_dp_check_frl_training(struct intel_dp *intel_dp) {
>> +struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> +
>> +if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
>> +    !intel_dp_is_frl_required(intel_dp))
>> +return;
>> +
>> +if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
>> +int ret, mode;
>> +
>> +drm_dbg(&dev_priv->drm, "Couldnt set FRL mode, continuing
>> with TMDS mode\n");
>> +ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
>> +mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
>> +
>> +if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
>> +drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set
>> TMDS mode\n");
>> +}
>> +
>> +else
> Move it up and enclose in { to match the above if style.


Agreed. Will fix the styling issue here.


Regards,

Ankit

>
>> +drm_dbg(&dev_priv->drm, "FRL training Completed\n"); }
>> +
>>   static void
>>   g4x_set_link_train(struct intel_dp *intel_dp,
>>      const struct intel_crtc_state *crtc_state, diff --git
>> a/drivers/gpu/drm/i915/display/intel_dp.h
>> b/drivers/gpu/drm/i915/display/intel_dp.h
>> index fcc28eb242f2..81d83d88cd41 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -143,4 +143,6 @@ bool intel_dp_initial_fastset_check(struct intel_encoder
>> *encoder,  void intel_dp_sync_state(struct intel_encoder *encoder,
>>    const struct intel_crtc_state *crtc_state);
>>
>> +void intel_dp_check_frl_training(struct intel_dp *intel_dp);
>> +
>>   #endif /* __INTEL_DP_H__ */
>> --
>> 2.17.1
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Re: [RFC 06/13] drm/i915: Check for FRL training before DP Link training

[Nautiyal, Ankit K]

On 10/19/2020 3:51 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 06/13] drm/i915: Check for FRL training before DP Link training
>>
>> This patch calls functions to check FRL training requirements for an HDMI2.1 sink,
>> when connected through PCON.
>> The call is made before the DP link training. In case FRL is not required or failure
>> during FRL training, the TMDS mode is selected for the pcon.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
>> drivers/gpu/drm/i915/display/intel_dp.c  | 2 ++
>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index bb0b9930958f..1834e5de60a7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -3484,6 +3484,8 @@ static void tgl_ddi_pre_enable_dp(struct
>> intel_atomic_state *state,
>>   if (!is_mst)
>>   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>>
>> +intel_dp_check_frl_training(intel_dp);
> Good to move it near start_link_training to stay consistent with rest of the calls.


Alright. Will take care in the next version.

Thanks & Regards,

Ankit


>
>> +
>>   intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
>>   /*
>>    * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index c1342b5e7781..668165dd2b1a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4206,6 +4206,7 @@ static void intel_enable_dp(struct intel_atomic_state
>> *state,
>>
>>   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>>   intel_dp_configure_protocol_converter(intel_dp);
>> +intel_dp_check_frl_training(intel_dp);
>>   intel_dp_start_link_train(intel_dp, pipe_config);
>>   intel_dp_stop_link_train(intel_dp, pipe_config);
>>
>> @@ -6127,6 +6128,7 @@ int intel_dp_retrain_link(struct intel_encoder
>> *encoder,
>>       !intel_dp_mst_is_master_trans(crtc_state))
>>   continue;
>>
>> +intel_dp_check_frl_training(intel_dp);
>>   intel_dp_start_link_train(intel_dp, crtc_state);
>>   intel_dp_stop_link_train(intel_dp, crtc_state);
>>   break;
>> --
>> 2.17.1
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Re: [RFC 07/13] drm/dp_helper: Add support for link status and link recovery

[Nautiyal, Ankit K]

On 10/19/2020 4:07 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 07/13] drm/dp_helper: Add support for link status and link
>> recovery
> Move this in the start of the series along with rest of the generic DRM helpers.
Alight, will move this along with other DRM helpers.
>
>> From: Swati Sharma <swati2.sharma@intel.com>
>>
>> This patch adds support for link status and link recovery. There are specific
>> DPCD’s defined for link status check and recovery in case of any issues. PCON will
>> communicate the same using an IRQ_HPD to source. HDMI sink would have
>> indicated the same to PCON using SCDC interrupt mechanism. While source can
>> always read final HDMI sink’s status using I2C over AUX, it’s easier and faster to
>> read the PCON’s already read HDMI sink’s status registers.
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/drm_dp_helper.c | 33 +++++++++++++++++++++++++++++++++
>>   include/drm/drm_dp_helper.h     | 16 ++++++++++++++++
>>   2 files changed, 49 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>> b/drivers/gpu/drm/drm_dp_helper.c index df858533dbf7..33a4ac2fb225 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -2896,3 +2896,36 @@ int drm_dp_pcon_hdmi_link_mode(struct
>> drm_dp_aux *aux, u8 *frl_trained_mask)
>>   return mode;
>>   }
>>   EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
>> +
>> +void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
>> +   struct drm_connector *connector) {
> This just prints a message if error counts are detected. There isn't any recovery here.
> May be you should re-phrase the patch header and description to reflect the same.
>
> Also what will be the usage of this just prints a message, may be return the error to caller
> to plan a recovery or link reset .


You are right, this patch is just adding few DPCDs that will be useful 
in detection of Link failure.

These registers will be used while servicing short pulse IRQ_HPD and 
there the FRL training will be restarted. In case of failure, will be 
switched to TMDS mode.

This is taken care in the subsequent patch for i915, which modifies the 
intel_dp_short_pulse().

The helper function is more for debugging purpose, to identify the exact 
lanes which had issues and the magnitude of the error counts in that lane.

I will rephrase the commit message to be more clear.


>> +u8 buf, error_count;
>> +int i, num_error;
>> +struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
>> +
>> +for (i = 0; i < hdmi->max_lanes; i++)
>> +{
>> +if (drm_dp_dpcd_readb(aux,
>> DP_PCON_HDMI_ERROR_STATUS_LN0 + i , &buf) < 0)
>> +return;
>> +
>> +error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
>> +
>> +switch(error_count) {
> Alignment is off.


Agreed. Will fix this in next version.

>
>> +case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
>> +num_error = 100;
>> +break;
>> +case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
>> +num_error = 10;
>> +break;
>> +case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
>> +num_error = 3;
>> +break;
>> +default:
>> +num_error = 0;
>> +}
>> +
>> +DRM_ERROR("More than %d errors since the last read for lane
>> %d", num_error, i);
>> +}
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>> d6f79b2d1287..eb26c86dc8ca 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -946,6 +946,11 @@ struct drm_device;
>>   # define DP_CEC_IRQ                          (1 << 2)
>>
>>   #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
>> +# define RX_CAP_CHANGED                      (1 << 0)
>> +# define LINK_STATUS_CHANGED                 (1 << 1)
>> +# define STREAM_STATUS_CHANGED               (1 << 2)
>> +# define HDMI_LINK_STATUS_CHANGED            (1 << 3)
>> +# define CONNECTED_OFF_ENTRY_REQUESTED       (1 << 4)
>>
>>   #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
>>   # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
>> @@ -1130,6 +1135,16 @@ struct drm_device;
>>   #define DP_PROTOCOL_CONVERTER_CONTROL_20x3052 /* DP 1.3
>> */
>>   # define DP_CONVERSION_TO_YCBCR422_ENABLE(1 << 0) /* DP 1.3 */
>>
>> +/* PCON Downstream HDMI ERROR Status per Lane */
>> +#define DP_PCON_HDMI_ERROR_STATUS_LN0          0x3037
>> +#define DP_PCON_HDMI_ERROR_STATUS_LN1          0x3038
>> +#define DP_PCON_HDMI_ERROR_STATUS_LN2          0x3039
>> +#define DP_PCON_HDMI_ERROR_STATUS_LN3          0x303A
>> +# define DP_PCON_HDMI_ERROR_COUNT_MASK         (0x7 << 0)
>> +# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS   (1 << 0)
>> +# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS     (1 << 1)
>> +# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
>> +
>>   /* HDCP 1.3 and HDCP 2.2 */
>>   #define DP_AUX_HDCP_BKSV0x68000
>>   #define DP_AUX_HDCP_RI_PRIME0x68005
>> @@ -2047,4 +2062,5 @@ int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
>>
>>   bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);  int
>> drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
>> +void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
>> +struct drm_connector *connector);
> Leave a blank line.

Agreed. Will fix this in next version.


Thanks & Regards,

Ankit

>
>>   #endif /* _DRM_DP_HELPER_H_ */
>> --
>> 2.17.1
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Re: [RFC 08/13] drm/i915: Add support for enabling link status and recovery

[Nautiyal, Ankit K]

On 10/19/2020 4:19 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 08/13] drm/i915: Add support for enabling link status and recovery
>>
>> From: Swati Sharma <swati2.sharma@intel.com>
>>
>> In this patch enabled support for link status and recovery in i915 driver. HDMI
>> link loss indication to upstream DP source is indicated via IRQ_HPD. This is
>> followed by reading of HDMI link configuration status
>> (HDMI_TX_LINK_ACTIVE_STATUS). If the PCON → HDMI 2.1 link status is off;
>> reinitiate frl link training to recover.
>> Also, HDMI FRL link error count range for each individual FRL active lane is
>> indicated by DOWNSTREAM_HDMI_ERROR_STATUS_LN registers.
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++++--
>>   1 file changed, 44 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 668165dd2b1a..e6c4cb844e37 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -5955,6 +5955,29 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
>>   return link_ok;
>>   }
>>
>> +static void
>> +intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) {
>> +bool is_active;
>> +u8 buf = 0;
>> +
>> +is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
>> +if (intel_dp->frl.is_trained && !is_active) {
>> +if (drm_dp_dpcd_readb(&intel_dp->aux,
>> DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
>> +return;
>> +
>> +buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
>> +if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
>> +return;
>> +
>> +intel_dp->frl.is_trained = false;
>> +intel_dp->frl.trained_rate_gbps = 0;
>> +
>> +intel_dp_check_frl_training(intel_dp);
>> +drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux,
>> &intel_dp->attached_connector->base);
> Just printing the error here may not help in recovery. If FRL is failing may be a TMDS fallback should be
> attempted. Also error count should be returned instead of just a print.

The function dp_check_frl_training() will restart the FRL link training 
if required and fall back to TMDS if FRL does not succeed.

The function for error count should be first and later the frl training 
should be checked. Will fix this in next patch version.

The error counts will be different for different lanes, so IMHO, this 
information is more for debugging. Not sure, if we can

use this to take any corrective action.


>> +}
>> +}
>> +
>>   static bool
>>   intel_dp_needs_link_retrain(struct intel_dp *intel_dp)  { @@ -6320,7 +6343,7
>> @@ intel_dp_hotplug(struct intel_encoder *encoder,
>>   return state;
>>   }
>>
>> -static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
>> +static void intel_dp_check_device_service_irq(struct intel_dp
>> +*intel_dp)
>>   {
>>   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>   u8 val;
>> @@ -6344,6 +6367,23 @@ static void intel_dp_check_service_irq(struct intel_dp
>> *intel_dp)
>>   drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");  }
>>
>> +static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
>> +{
>> +u8 val;
>> +
>> +if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
>> +return;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux,
>> +      DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 ||
>> !val)
> An error message would be handy here.


Alright, will be adding appropriate error message here.

>
>> +return;
>> +
>> +drm_dp_dpcd_writeb(&intel_dp->aux,
>> DP_LINK_SERVICE_IRQ_VECTOR_ESI0,
>> +val);
> Check for error message here.

As mentioned above, will take care in next version.

Thanks & Regards,

Ankit


>
>> +
>> +if (val & HDMI_LINK_STATUS_CHANGED)
>> +intel_dp_handle_hdmi_link_status_change(intel_dp);
>> +}
>> +
>>   /*
>>    * According to DP spec
>>    * 5.1.2:
>> @@ -6383,7 +6423,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
>>   return false;
>>   }
>>
>> -intel_dp_check_service_irq(intel_dp);
>> +intel_dp_check_device_service_irq(intel_dp);
>> +intel_dp_check_link_service_irq(intel_dp);
>>
>>   /* Handle CEC interrupts, if any */
>>   drm_dp_cec_irq(&intel_dp->aux);
>> @@ -6815,7 +6856,7 @@ intel_dp_detect(struct drm_connector *connector,
>>       to_intel_connector(connector)->detect_edid)
>>   status = connector_status_connected;
>>
>> -intel_dp_check_service_irq(intel_dp);
>> +intel_dp_check_device_service_irq(intel_dp);
>>
>>   out:
>>   if (status != connector_status_connected && !intel_dp->is_mst)
>> --
>> 2.17.1
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Re: [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block

[Nautiyal, Ankit K]

On 10/19/2020 4:31 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block
> Move this also to beginning of series along with all DRM helpers.


Agreed will move this with other DRM helpers.

>
>> This patch parses HFVSDB fields for DSC1.2 capabilities of an
>> HDMI2.1 sink. These fields are required by a source to understand the DSC
>> capability of the sink, to set appropriate PPS parameters, before transmitting
>> compressed data stream.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/drm_edid.c  | 19 +++++++++++++++++++
>> include/drm/drm_connector.h | 32 ++++++++++++++++++++++++++++++++
>>   2 files changed, 51 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
>> 8afb136e73f5..feee19657a7a 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -4889,10 +4889,29 @@ static void
>> drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,  {
>>   struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
>>   u8 max_frl_rate;
>> +u8 dsc_max_frl_rate;
>>
>>   max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;
>>   drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
>>        &hdmi->max_frl_rate_per_lane);
>> +
>> +hdmi->dsc_1p2 = db[11] & DRM_EDID_DSC_1P2;
> We should right shift them as well to get right values.

You are right, For MAX_FRL_RATE and DSC_MAX_FRL_RATE_MASK given below, 
we need to rshift by 4 for getting correct values.

I had missed that in this patch. Will take care in the next version.

But for others there are only 1 bit, we are just storing these as bool, 
if the appropriate bit is set.


>
>> +        hdmi->dsc_native_420 = db[11] & DRM_EDID_DSC_NATIVE_420;
> Same here. Also Alignment is off.


Will fix the alignment in next version.

>
>> +hdmi->dsc_all_bpp = db[11] & DRM_EDID_DSC_ALL_BPP;
>> +
>> +if (db[11] & DRM_EDID_DSC_16BPC)
>> +hdmi->dsc_bpc_supported = 16;
>> +else if (db[11] & DRM_EDID_DSC_12BPC)
>> +hdmi->dsc_bpc_supported = 12;
>> +else if (db[11] & DRM_EDID_DSC_10BPC)
>> +hdmi->dsc_bpc_supported = 10;
>> +else
>> +hdmi->dsc_bpc_supported = 0;
>> +
>> +dsc_max_frl_rate = db[12] & DRM_EDID_DSC_MAX_FRL_RATE;
> This will not give correct value. Fix it.

As mentioned above, will fix this in next version.


>
>> +drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi->dsc_max_lanes,
>> +     &hdmi->dsc_max_frl_rate_per_lane);
>> +hdmi->dsc_total_chunk_kbytes = db[13] &
>> +DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
>>   }
>>
>>   static void drm_parse_ycbcr420_deep_color_info(struct drm_connector
>> *connector, diff --git a/include/drm/drm_connector.h
>> b/include/drm/drm_connector.h index f351bf10c076..7100012f9c0f 100644
>> --- a/include/drm/drm_connector.h
>> +++ b/include/drm/drm_connector.h
>> @@ -213,6 +213,38 @@ struct drm_hdmi_info {
>>
>>   /** @max_lanes: supported by sink */
>>   u8 max_lanes;
>> +
>> +/** @dsc_1p2: flag for dsc1.2 support by sink */
>> +bool dsc_1p2;
> Add a struct for all these HDMI dsc params.


Makes sense, will add a new struct for HDMI dsc parameters read for DSC 
supported by a given HDMI sink.

Thanks & Regards,

Ankit

>
>> +
>> +/** @dsc_native_420: Does sink support DSC with 4:2:0 compression */
>> +bool dsc_native_420;
>> +
>> +/**
>> + * @dsc_all_bpp: Does sink support all bpp with 4:4:4: or 4:2:2
>> + * compressed formats
>> + */
>> +bool dsc_all_bpp;
>> +
>> +/**
>> + * @dsc_bpc_supported: compressed bpc supported by sink : 10, 12 or 16
>> bpc
>> + */
>> +u8 dsc_bpc_supported;
>> +
>> +/** @dsc_max_slices: maximum number of Horizontal slices supported
>> by */
>> +u8 dsc_max_slices;
>> +
>> +/** @dsc_clk_per_slice : max pixel clock in MHz supported per slice */
>> +u8 dsc_clk_per_slice;
>> +
>> +/** @dsc_max_lanes : dsc max lanes supported for Fixed rate Link
>> training */
>> +u8 dsc_max_lanes;
>> +
>> +/** @dsc_max_frl_rate_per_lane : maximum frl rate with DSC per lane */
>> +u8 dsc_max_frl_rate_per_lane;
>> +
>> +/** @dsc_total_chunk_kbytes: max size of chunks in KBs supported per
>> line*/
>> +u8 dsc_total_chunk_kbytes;
>>   };
>>
>>   /**
>> --
>> 2.17.1
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Re: [RFC 10/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon

[Nautiyal, Ankit K]

On 10/19/2020 4:49 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 10/13] drm/dp_helper: Add support for Configuring DSC for
>> HDMI2.1 Pcon
>>
>> This patch adds registers for getting DSC encoder capability for a HDMI2.1 PCon.
>> It also addes helper functions to configure DSC between the PCON and HDMI2.1
>> sink.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/drm_dp_helper.c |  93 +++++++++++++++++++++++++++
>>   include/drm/drm_dp_helper.h     | 109 ++++++++++++++++++++++++++++++++
>>   2 files changed, 202 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>> b/drivers/gpu/drm/drm_dp_helper.c index 33a4ac2fb225..f10a9c2d6f04 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -2929,3 +2929,96 @@ void drm_dp_pcon_hdmi_frl_link_error_count(struct
>> drm_dp_aux *aux,
>>   }
>>   }
>>   EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
>> +
>> +static
>> +int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8
>> +pps_buf_config) {
>> +u8 buf = 0;
>> +int ret;
>> +
>> +buf |= DP_PCON_ENABLE_DSC_ENCODER;
> Directly assign it.


Alright, will change in next version.

>
>> +if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
>> +buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
>> +buf |= pps_buf_config << 2;
>> +}
>> +
>> +ret = drm_dp_dpcd_writeb(aux,
>> DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
>> +if (ret < 0)
>> +return ret;
>> +
>> +return 0;
>> +}
>> +
>> +/**
>> + * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
>> + * for DSC1.2 between PCON & HDMI2.1 sink
>> + * @aux: DisplayPort AUX channel
>> + *
>> + * Returns 0 on success, else returns negative error code.
>> + * */
>> +int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) {
>> +int ret;
>> +
>> +ret = drm_dp_pcon_configure_dsc_enc(aux,
>> DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
>> +if (ret < 0)
>> +return ret;
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_pps_default);
>> +
>> +/**
>> + * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override
>> +buffer for
>> + * HDMI sink
>> + * @aux: DisplayPort AUX channel
>> + * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
>> + *
>> + * Returns 0 on success, else returns negative error code.
>> + * */
>> +int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8
>> +pps_buf[128]) {
>> +int ret;
>> +
>> +ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE,
>> &pps_buf, 128);
>> +if (ret < 0)
>> +return ret;
>> +
>> +ret = drm_dp_pcon_configure_dsc_enc(aux,
>> DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
>> +if (ret < 0)
>> +return ret;
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
>> +
>> +/*
>> + * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC
>> +encoder
>> + * override registers
>> + * @aux: DisplayPort AUX channel
>> + * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
>> + * bits_per_pixel.
>> + *
>> + * Returns 0 on success, else returns negative error code.
>> + * */
>> +int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8
>> +pps_param[6]) {
>> +int ret;
>> +
>> +ret = drm_dp_dpcd_write(aux,
>> DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
>> +if (ret < 0)
>> +return ret;
>> +ret = drm_dp_dpcd_write(aux,
>> DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[1], 2);
>> +if (ret < 0)
>> +return ret;
>> +ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP,
>> &pps_param[2], 2);
>> +if (ret < 0)
>> +return ret;
>> +
>> +ret = drm_dp_pcon_configure_dsc_enc(aux,
>> DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
>> +if (ret < 0)
>> +return ret;
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>> eb26c86dc8ca..3de022d4a65e 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -441,6 +441,83 @@ struct drm_device;
>>   # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP    (1 << 2)
>>   # define DP_FEC_BIT_ERROR_COUNT_CAP    (1 << 3)
>>
>> +/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
>> +#define DP_PCON_DSC_ENCODER                 0x092
>> +# define DP_PCON_DSC_ENCODER_SUPPORTED      (1 << 0)
>> +# define DP_PCON_DSC_PPS_ENC_OVERRIDE       (1 << 1)
>> +
>> +/* DP-HDMI2.1 PCON DSC Version */
>> +#define DP_PCON_DSC_VERSION                 0x093
>> +# define DP_PCON_DSC_MAJOR_MASK    (0xF << 0)
>> +# define DP_PCON_DSC_MINOR_MASK    (0xF << 4)
>> +# define DP_PCON_DSC_MAJOR_SHIFT    0
>> +# define DP_PCON_DSC_MINOR_SHIFT    4
>> +
>> +/* DP-HDMI2.1 PCON DSC RC Buffer block size */
>> +#define DP_PCON_DSC_RC_BUF_BLK_INFO    0x094
>> +# define DP_PCON_DSC_RC_BUF_BLK_SIZE    (0x3 << 0)
>> +# define DP_PCON_DSC_RC_BUF_BLK_1KB    0
>> +# define DP_PCON_DSC_RC_BUF_BLK_4KB    1
>> +# define DP_PCON_DSC_RC_BUF_BLK_16KB    2
>> +# define DP_PCON_DSC_RC_BUF_BLK_64KB    3
>> +
>> +/* DP-HDMI2.1 PCON DSC RC Buffer size */
>> +#define DP_PCON_DSC_RC_BUF_SIZE    0x095
>> +
>> +/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
>> +#define DP_PCON_DSC_SLICE_CAP_1    0x096
>> +# define DP_PCON_DSC_1_PER_DSC_ENC     (0x1 << 0)
>> +# define DP_PCON_DSC_2_PER_DSC_ENC     (0x1 << 1)
>> +# define DP_PCON_DSC_4_PER_DSC_ENC     (0x1 << 3)
>> +# define DP_PCON_DSC_6_PER_DSC_ENC     (0x1 << 4)
>> +# define DP_PCON_DSC_8_PER_DSC_ENC     (0x1 << 5)
>> +# define DP_PCON_DSC_10_PER_DSC_ENC    (0x1 << 6)
>> +# define DP_PCON_DSC_12_PER_DSC_ENC    (0x1 << 7)
>> +
>> +#define DP_PCON_DSC_BUF_BIT_DEPTH    0x097
>> +# define DP_PCON_DSC_BIT_DEPTH_MASK    (0xF << 0)
>> +# define DP_PCON_DSC_DEPTH_9_BITS    0
>> +# define DP_PCON_DSC_DEPTH_10_BITS    1
>> +# define DP_PCON_DSC_DEPTH_11_BITS    2
>> +# define DP_PCON_DSC_DEPTH_12_BITS    3
>> +# define DP_PCON_DSC_DEPTH_13_BITS    4
>> +# define DP_PCON_DSC_DEPTH_14_BITS    5
>> +# define DP_PCON_DSC_DEPTH_15_BITS    6
>> +# define DP_PCON_DSC_DEPTH_16_BITS    7
>> +# define DP_PCON_DSC_DEPTH_8_BITS    8
>> +
>> +#define DP_PCON_DSC_BLOCK_PREDICTION    0x098
>> +# define DP_PCON_DSC_BLOCK_PRED_SUPPORT    (0x1 << 0)
>> +
>> +#define DP_PCON_DSC_ENC_COLOR_FMT_CAP    0x099
>> +# define DP_PCON_DSC_ENC_RGB    (0x1 << 0)
>> +# define DP_PCON_DSC_ENC_YUV444    (0x1 << 1)
>> +# define DP_PCON_DSC_ENC_YUV422_S    (0x1 << 2)
>> +# define DP_PCON_DSC_ENC_YUV422_N    (0x1 << 3)
>> +# define DP_PCON_DSC_ENC_YUV420_N    (0x1 << 4)
>> +
>> +#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP    0x09A
>> +# define DP_PCON_DSC_ENC_8BPC    (0x1 << 0)
>> +# define DP_PCON_DSC_ENC_10BPC    (0x1 << 0)
>> +# define DP_PCON_DSC_ENC_12BPC    (0x1 << 0)
> These offsets are wrong, should be 0x1 < (1, 2 and 3)


Thanks for catching this, will correct in next version.

Regards,

Ankit

>
>> +
>> +#define DP_PCON_DSC_MAX_SLICE_WIDTH    0x09B
>> +
>> +/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
>> +#define DP_PCON_DSC_SLICE_CAP_2             0x09C
>> +# define DP_PCON_DSC_16_PER_DSC_ENC    (0x1 << 0)
>> +# define DP_PCON_DSC_20_PER_DSC_ENC         (0x1 << 1)
>> +# define DP_PCON_DSC_24_PER_DSC_ENC         (0x1 << 2)
>> +
>> +/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
>> +#define DP_PCON_DSC_BPP_INCR    0x09E
>> +# define DP_PCON_DSC_BPP_INCR_MASK    (0x7 << 0)
>> +# define DP_PCON_DSC_ONE_16TH_BPP    0
>> +# define DP_PCON_DSC_ONE_8TH_BPP    1
>> +# define DP_PCON_DSC_ONE_4TH_BPP    2
>> +# define DP_PCON_DSC_ONE_HALF_BPP    3
>> +# define DP_PCON_DSC_ONE_BPP    4
>> +
>>   /* DP Extended DSC Capabilities */
>>   #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0  0x0a0   /* DP 1.4a SCR */
>>   #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1 @@ -1134,6
>> +1211,12 @@ struct drm_device;
>>   # define DP_HDMI_FORCE_SCRAMBLING(1 << 3) /* DP 1.4 */
>>   #define DP_PROTOCOL_CONVERTER_CONTROL_20x3052 /* DP 1.3
>> */
>>   # define DP_CONVERSION_TO_YCBCR422_ENABLE(1 << 0) /* DP 1.3 */
>> +# define DP_PCON_ENABLE_DSC_ENCODER        (1 << 1)
>> +# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK(0x3 << 2)
>> +# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED      0
>> +# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS     1
>> +# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER     2
>> +
>>
>>   /* PCON Downstream HDMI ERROR Status per Lane */
>>   #define DP_PCON_HDMI_ERROR_STATUS_LN0          0x3037
>> @@ -1145,6 +1228,29 @@ struct drm_device;
>>   # define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS     (1 << 1)
>>   # define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
>>
>> +/* PCON HDMI CONFIG PPS Override Buffer
>> + * Valid Offsets to be added to Base : 0-127  */
>> +#define DP_PCON_HDMI_PPS_OVERRIDE_BASE        0x3100
>> +
>> +/* PCON HDMI CONFIG PPS Override Parameter: Slice height
>> + * Offset-0 8LSBs of the Slice height.
>> + * Offset-1 8MSBs of the Slice height.
>> + */
>> +#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT    0x3180
>> +
>> +/* PCON HDMI CONFIG PPS Override Parameter: Slice width
>> + * Offset-0 8LSBs of the Slice width.
>> + * Offset-1 8MSBs of the Slice width.
>> + */
>> +#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH    0x3182
>> +
>> +/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
>> + * Offset-0 8LSBs of the bits_per_pixel.
>> + * Offset-1 2MSBs of the bits_per_pixel.
>> + */
>> +#define DP_PCON_HDMI_PPS_OVRD_BPP     0x3184
>> +
>>   /* HDCP 1.3 and HDCP 2.2 */
>>   #define DP_AUX_HDCP_BKSV0x68000
>>   #define DP_AUX_HDCP_RI_PRIME0x68005
>> @@ -2063,4 +2169,7 @@ int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
>> bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);  int
>> drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
>> void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, struct
>> drm_connector *connector);
>> +int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); int
>> +drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
>> +int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8
>> +pps_param[6]);
>>   #endif /* _DRM_DP_HELPER_H_ */
>> --
>> 2.17.1
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Re: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder

[Nautiyal, Ankit K]

On 10/19/2020 5:02 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Thursday, October 15, 2020 4:23 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com;
>> Sharma, Swati2 <swati2.sharma@intel.com>
>> Subject: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON
>> encoder
>>
>> This patch adds a helper function to read the DSC capabilities of the
>> HDMI2.1 PCon encoder. It also adds a new structure to store these caps, which
>> can then be used to get the PPS parameters for PCON-HDMI2.1 sink pair. Which
>> inturn will be used to take a call to override the existing PPS-metadata, by either
>> writing the entire new PPS metadata, or by writing only the PPS override
>> parameters.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_types.h    |  16 ++
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 178 ++++++++++++++++++
>>   2 files changed, 194 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 6c69922313d6..23282695a47f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1292,6 +1292,21 @@ struct intel_dp_pcon_frl {
>>   int trained_rate_gbps;
>>   };
>>
>> +struct intel_dp_pcon_dsc {
>> +bool enc_support;
>> +bool pps_override_support;
>> +bool blk_prediction_support;
>> +u8 version_major;
>> +u8 version_minor;
>> +u8 color_fmt_mask;
>> +u8 color_depth_mask;
>> +u8 max_slices;;
>> +u8 max_slice_width;
>> +u8 line_buf_bit_depth;
>> +u8 bpp_precision_incr;
>> +int rc_buf_size;
>> +};
>> +
>>   struct intel_dp {
>>   i915_reg_t output_reg;
>>   u32 DP;
>> @@ -1415,6 +1430,7 @@ struct intel_dp {
>>   bool hobl_active;
>>
>>   struct intel_dp_pcon_frl frl;
>> +struct intel_dp_pcon_dsc pcon_dsc;
>>   };
>>
>>   enum lspcon_vendor {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index e6c4cb844e37..b4f8abaea607 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -3882,6 +3882,182 @@ cpt_set_link_train(struct intel_dp *intel_dp,
>>   intel_de_posting_read(dev_priv, intel_dp->output_reg);  }
>>
>> +void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) {
>> +u8 buf;
>> +u8 rc_buf_blk_size;
>> +u8 max_slices = 0;
>> +
>> +struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> +struct intel_dp_pcon_dsc *pcon_dsc = &intel_dp->pcon_dsc;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENCODER, &buf)
>> < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_ENCODER\n");
>> +return;
>> +}
>> +pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED;
>> +pcon_dsc->pps_override_support = buf &
>> DP_PCON_DSC_PPS_ENC_OVERRIDE;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_VERSION, &buf)
>> < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_VERSION\n");
>> +return;
> If we fail here or in any of the subsequent calls below shouldn't we reset the dsc params saying DSC not
> supported. Else we may return with ex.
> pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED
> which would ideally not be right.

You are right, will take care in next patch. If dsc 1.2 is not supported 
we will not configure PCON encode DSC DPCDs.

Also I have realized, we do not use all the information for writing PPS 
parameters.

So aligning with the existing code, will read all the pcon's DSC encoder 
caps and store in intel_dp structure in a u8 array.

Will have drm helper functions to retrieve values like max slices, max 
slice with and bpp precision which need some processing, based on the 
port caps.


>> +}
>> +pcon_dsc->version_major = (buf & DP_PCON_DSC_MAJOR_MASK) >>
>> +  DP_PCON_DSC_MAJOR_SHIFT;
>> +pcon_dsc->version_minor = (buf & DP_PCON_DSC_MINOR_MASK) >>
>> +  DP_PCON_DSC_MINOR_SHIFT;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux,
>> DP_PCON_DSC_RC_BUF_BLK_INFO, &buf) < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_RC_BUF_BLK_INFO\n");
>> +return;
>> +}
>> +
>> +switch (buf & DP_PCON_DSC_RC_BUF_BLK_SIZE) {
>> +case DP_PCON_DSC_RC_BUF_BLK_1KB :
>> +rc_buf_blk_size = 1;
>> +break;
>> +case DP_PCON_DSC_RC_BUF_BLK_4KB :
>> +rc_buf_blk_size = 4;.
>> +break;
>> +case DP_PCON_DSC_RC_BUF_BLK_16KB :
>> +rc_buf_blk_size = 16;
>> +break;
>> +case DP_PCON_DSC_RC_BUF_BLK_64KB :
>> +rc_buf_blk_size = 64;
>> +break;
>> +default :
>> +rc_buf_blk_size = 0;
>> +}
> It would be good if you create sub-functions for each of these aspects to make it more readable.

Agreed. As mentioned above will have drm_helper functions for these.


>
>> +if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_RC_BUF_SIZE,
>> &buf) < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_RC_BUF_SIZE\n");
>> +return;
>> +}
>> +/* storing rc_buf_size in bytes */
>> +pcon_dsc->rc_buf_size = (buf + 1) * rc_buf_blk_size * 1024;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_SLICE_CAP_2,
>> &buf) < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_SLICE_CAP_2\n");
>> +return;
>> +}
>> +if (buf & DP_PCON_DSC_24_PER_DSC_ENC)
>> +       max_slices = 24;
>> +else if (buf & DP_PCON_DSC_20_PER_DSC_ENC)
>> +max_slices = 20;
>> +else if (buf & DP_PCON_DSC_16_PER_DSC_ENC)
>> +max_slices = 16;
>> +
>> +if (max_slices == 0) {
>> +if (drm_dp_dpcd_readb(&intel_dp->aux,
>> DP_PCON_DSC_SLICE_CAP_1,
>> +      &buf) < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_SLICE_CAP_2\n");
> Its SLICE_CAP_1.


Agreed, will fix in next version.


>
>> +return;
>> +}
>> +
>> +if (buf & DP_PCON_DSC_12_PER_DSC_ENC)
>> +max_slices = 12;
>> +else if (buf & DP_PCON_DSC_10_PER_DSC_ENC)
>> +max_slices = 10;
>> +else if (buf & DP_PCON_DSC_8_PER_DSC_ENC)
>> +max_slices = 8;
>> +else if (buf & DP_PCON_DSC_6_PER_DSC_ENC)
>> +max_slices = 6;
>> +else if (buf & DP_PCON_DSC_4_PER_DSC_ENC)
>> +max_slices = 4;
>> +else if (buf & DP_PCON_DSC_2_PER_DSC_ENC)
>> +max_slices = 2;
>> +else if (buf & DP_PCON_DSC_1_PER_DSC_ENC)
>> +max_slices = 1;
> Use switch here as well.

Wont be able to use switch here as logical & with different values is 
done. I will make it more compact and readable in next version.

Regards,

Ankit


>> +}
>> +
>> +pcon_dsc->max_slices = max_slices;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BUF_BIT_DEPTH,
>> &buf) < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_BUF_BIT_DEPTH\n");
>> +return;
>> +}
>> +switch (buf & DP_PCON_DSC_BIT_DEPTH_MASK) {
>> +case DP_PCON_DSC_DEPTH_8_BITS :
>> +pcon_dsc->line_buf_bit_depth = 8;
>> +break;
>> +case DP_PCON_DSC_DEPTH_9_BITS :
>> +pcon_dsc->line_buf_bit_depth = 9;
>> +break;
>> +case DP_PCON_DSC_DEPTH_10_BITS :
>> +pcon_dsc->line_buf_bit_depth = 10;
>> +break;
>> +case DP_PCON_DSC_DEPTH_11_BITS :
>> +pcon_dsc->line_buf_bit_depth = 11;
>> +break;
>> +case DP_PCON_DSC_DEPTH_12_BITS :
>> +pcon_dsc->line_buf_bit_depth = 12;
>> +break;
>> +case DP_PCON_DSC_DEPTH_13_BITS :
>> +pcon_dsc->line_buf_bit_depth = 13;
>> +break;
>> +case DP_PCON_DSC_DEPTH_14_BITS :
>> +pcon_dsc->line_buf_bit_depth = 14;
>> +break;
>> +case DP_PCON_DSC_DEPTH_15_BITS :
>> +pcon_dsc->line_buf_bit_depth = 15;
>> +break;
>> +case DP_PCON_DSC_DEPTH_16_BITS :
>> +pcon_dsc->line_buf_bit_depth = 16;
>> +break;
>> +default :
>> +pcon_dsc->line_buf_bit_depth = 0;
>> +}
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux,
>> DP_PCON_DSC_BLOCK_PREDICTION, &buf) < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_BLOCK_PREDICTION\n");
>> +return;
>> +}
>> +if (buf && DP_PCON_DSC_BLOCK_PRED_SUPPORT)
>> +pcon_dsc->blk_prediction_support = true;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux,
>> DP_PCON_DSC_ENC_COLOR_FMT_CAP, &buf) < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_ENC_COLOR_FMT_CAP\n");
>> +return;
>> +}
>> +pcon_dsc->color_fmt_mask = buf;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux,
>> DP_PCON_DSC_ENC_COLOR_DEPTH_CAP, &buf) < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_ENC_COLOR_DEPTH_CAP\n");
>> +return;
>> +}
>> +pcon_dsc->color_depth_mask = buf;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux,
>> DP_PCON_DSC_MAX_SLICE_WIDTH, &buf) < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_MAX_SLICE_WIDTH\n");
>> +return;
>> +}
>> +pcon_dsc->max_slice_width = buf;;
>> +
>> +if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BPP_INCR, &buf)
>> < 0) {
>> +drm_err(&i915->drm, "Failed to read
>> DP_PCON_DSC_BPP_INCR\n");
>> +return;
>> +}
>> +switch(buf & DP_PCON_DSC_BPP_INCR_MASK) {
>> +case DP_PCON_DSC_ONE_16TH_BPP:
>> +pcon_dsc->bpp_precision_incr = 16;
>> +break;
>> +case DP_PCON_DSC_ONE_8TH_BPP:
>> +pcon_dsc->bpp_precision_incr = 8;
>> +break;
>> +case DP_PCON_DSC_ONE_4TH_BPP:
>> +pcon_dsc->bpp_precision_incr = 4;
>> +break;
>> +case DP_PCON_DSC_ONE_HALF_BPP:
>> +pcon_dsc->bpp_precision_incr = 2;
>> +break;
>> +case DP_PCON_DSC_ONE_BPP:
>> +pcon_dsc->bpp_precision_incr = 1;
>> +break;
>> +default :
>> +pcon_dsc->bpp_precision_incr = 0;
>> +}
>> +}
>> +
>>   static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp)  {
>>   int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps; @@ -
>> 6659,6 +6835,8 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
>>       intel_dp->dfp.max_tmds_clock,
>>       intel_dp->dfp.pcon_max_frl,
>>       intel_dp->dfp.sink_max_frl);
>> +
>> +intel_dp_get_pcon_dsc_cap(intel_dp);
>>   }
>>
>>   static void
>> --
>> 2.17.1
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Re: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder

[Nautiyal, Ankit K]

On 10/19/2020 5:04 AM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Shankar, Uma
>> Sent: Monday, October 19, 2020 5:02 AM
>> To: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; Sharma, Swati2
>> <swati2.sharma@intel.com>
>> Subject: RE: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON
>> encoder
> Also it would be good to move to DRM Core.


Agreed, as mentioned in earlier patch, will move the appropriate code as 
drm_helper functions.


Regards,

Ankit

>
>>
>>> -----Original Message-----
>>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>>> Sent: Thursday, October 15, 2020 4:23 PM
>>> To: intel-gfx@lists.freedesktop.org
>>> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma
>>> <uma.shankar@intel.com>; Kulkarni, Vandita
>>> <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; Sharma,
>>> Swati2 <swati2.sharma@intel.com>
>>> Subject: [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1
>>> PCON encoder
>>>
>>> This patch adds a helper function to read the DSC capabilities of the
>>> HDMI2.1 PCon encoder. It also adds a new structure to store these
>>> caps, which can then be used to get the PPS parameters for
>>> PCON-HDMI2.1 sink pair. Which inturn will be used to take a call to
>>> override the existing PPS-metadata, by either writing the entire new
>>> PPS metadata, or by writing only the PPS override parameters.
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   .../drm/i915/display/intel_display_types.h    |  16 ++
>>>   drivers/gpu/drm/i915/display/intel_dp.c       | 178 ++++++++++++++++++
>>>   2 files changed, 194 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 6c69922313d6..23282695a47f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1292,6 +1292,21 @@ struct intel_dp_pcon_frl {
>>>   	int trained_rate_gbps;
>>>   };
>>>
>>> +struct intel_dp_pcon_dsc {
>>> +	bool enc_support;
>>> +	bool pps_override_support;
>>> +	bool blk_prediction_support;
>>> +	u8 version_major;
>>> +	u8 version_minor;
>>> +	u8 color_fmt_mask;
>>> +	u8 color_depth_mask;
>>> +	u8 max_slices;;
>>> +	u8 max_slice_width;
>>> +	u8 line_buf_bit_depth;
>>> +	u8 bpp_precision_incr;
>>> +	int rc_buf_size;
>>> +};
>>> +
>>>   struct intel_dp {
>>>   	i915_reg_t output_reg;
>>>   	u32 DP;
>>> @@ -1415,6 +1430,7 @@ struct intel_dp {
>>>   	bool hobl_active;
>>>
>>>   	struct intel_dp_pcon_frl frl;
>>> +	struct intel_dp_pcon_dsc pcon_dsc;
>>>   };
>>>
>>>   enum lspcon_vendor {
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index e6c4cb844e37..b4f8abaea607 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -3882,6 +3882,182 @@ cpt_set_link_train(struct intel_dp *intel_dp,
>>>   	intel_de_posting_read(dev_priv, intel_dp->output_reg);  }
>>>
>>> +void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) {
>>> +	u8 buf;
>>> +	u8 rc_buf_blk_size;
>>> +	u8 max_slices = 0;
>>> +
>>> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>> +	struct intel_dp_pcon_dsc *pcon_dsc = &intel_dp->pcon_dsc;
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENCODER, &buf)
>>> < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_ENCODER\n");
>>> +		return;
>>> +	}
>>> +	pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED;
>>> +	pcon_dsc->pps_override_support = buf &
>>> DP_PCON_DSC_PPS_ENC_OVERRIDE;
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_VERSION, &buf)
>>> < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_VERSION\n");
>>> +		return;
>> If we fail here or in any of the subsequent calls below shouldn't we reset the dsc
>> params saying DSC not supported. Else we may return with ex.
>> pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED which
>> would ideally not be right.
>>
>>> +	}
>>> +	pcon_dsc->version_major = (buf & DP_PCON_DSC_MAJOR_MASK) >>
>>> +				  DP_PCON_DSC_MAJOR_SHIFT;
>>> +	pcon_dsc->version_minor = (buf & DP_PCON_DSC_MINOR_MASK) >>
>>> +				  DP_PCON_DSC_MINOR_SHIFT;
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
>>> DP_PCON_DSC_RC_BUF_BLK_INFO, &buf) < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_RC_BUF_BLK_INFO\n");
>>> +		return;
>>> +	}
>>> +
>>> +	switch (buf & DP_PCON_DSC_RC_BUF_BLK_SIZE) {
>>> +	case DP_PCON_DSC_RC_BUF_BLK_1KB :
>>> +		rc_buf_blk_size = 1;
>>> +		break;
>>> +	case DP_PCON_DSC_RC_BUF_BLK_4KB :
>>> +		rc_buf_blk_size = 4;
>>> +		break;
>>> +	case DP_PCON_DSC_RC_BUF_BLK_16KB :
>>> +		rc_buf_blk_size = 16;
>>> +		break;
>>> +	case DP_PCON_DSC_RC_BUF_BLK_64KB :
>>> +		rc_buf_blk_size = 64;
>>> +		break;
>>> +	default :
>>> +		rc_buf_blk_size = 0;
>>> +	}
>> It would be good if you create sub-functions for each of these aspects to make it
>> more readable.
>>
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_RC_BUF_SIZE,
>>> &buf) < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_RC_BUF_SIZE\n");
>>> +		return;
>>> +	}
>>> +	/* storing rc_buf_size in bytes */
>>> +	pcon_dsc->rc_buf_size = (buf + 1) * rc_buf_blk_size * 1024;
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_SLICE_CAP_2,
>>> &buf) < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_SLICE_CAP_2\n");
>>> +		return;
>>> +	}
>>> +	if (buf & DP_PCON_DSC_24_PER_DSC_ENC)
>>> +	       max_slices = 24;
>>> +	else if (buf & DP_PCON_DSC_20_PER_DSC_ENC)
>>> +		max_slices = 20;
>>> +	else if (buf & DP_PCON_DSC_16_PER_DSC_ENC)
>>> +		max_slices = 16;
>>> +
>>> +	if (max_slices == 0) {
>>> +		if (drm_dp_dpcd_readb(&intel_dp->aux,
>>> DP_PCON_DSC_SLICE_CAP_1,
>>> +				      &buf) < 0) {
>>> +			drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_SLICE_CAP_2\n");
>> Its SLICE_CAP_1.
>>
>>> +			return;
>>> +		}
>>> +
>>> +		if (buf & DP_PCON_DSC_12_PER_DSC_ENC)
>>> +			max_slices = 12;
>>> +		else if (buf & DP_PCON_DSC_10_PER_DSC_ENC)
>>> +			max_slices = 10;
>>> +		else if (buf & DP_PCON_DSC_8_PER_DSC_ENC)
>>> +			max_slices = 8;
>>> +		else if (buf & DP_PCON_DSC_6_PER_DSC_ENC)
>>> +			max_slices = 6;
>>> +		else if (buf & DP_PCON_DSC_4_PER_DSC_ENC)
>>> +			max_slices = 4;
>>> +		else if (buf & DP_PCON_DSC_2_PER_DSC_ENC)
>>> +			max_slices = 2;
>>> +		else if (buf & DP_PCON_DSC_1_PER_DSC_ENC)
>>> +			max_slices = 1;
>> Use switch here as well.
>>
>>> +	}
>>> +
>>> +	pcon_dsc->max_slices = max_slices;
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BUF_BIT_DEPTH,
>>> &buf) < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_BUF_BIT_DEPTH\n");
>>> +		return;
>>> +	}
>>> +	switch (buf & DP_PCON_DSC_BIT_DEPTH_MASK) {
>>> +	case DP_PCON_DSC_DEPTH_8_BITS :
>>> +		pcon_dsc->line_buf_bit_depth = 8;
>>> +		break;
>>> +	case DP_PCON_DSC_DEPTH_9_BITS :
>>> +		pcon_dsc->line_buf_bit_depth = 9;
>>> +		break;
>>> +	case DP_PCON_DSC_DEPTH_10_BITS :
>>> +		pcon_dsc->line_buf_bit_depth = 10;
>>> +		break;
>>> +	case DP_PCON_DSC_DEPTH_11_BITS :
>>> +		pcon_dsc->line_buf_bit_depth = 11;
>>> +		break;
>>> +	case DP_PCON_DSC_DEPTH_12_BITS :
>>> +		pcon_dsc->line_buf_bit_depth = 12;
>>> +		break;
>>> +	case DP_PCON_DSC_DEPTH_13_BITS :
>>> +		pcon_dsc->line_buf_bit_depth = 13;
>>> +		break;
>>> +	case DP_PCON_DSC_DEPTH_14_BITS :
>>> +		pcon_dsc->line_buf_bit_depth = 14;
>>> +		break;
>>> +	case DP_PCON_DSC_DEPTH_15_BITS :
>>> +		pcon_dsc->line_buf_bit_depth = 15;
>>> +		break;
>>> +	case DP_PCON_DSC_DEPTH_16_BITS :
>>> +		pcon_dsc->line_buf_bit_depth = 16;
>>> +		break;
>>> +	default :
>>> +		pcon_dsc->line_buf_bit_depth = 0;
>>> +	}
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
>>> DP_PCON_DSC_BLOCK_PREDICTION, &buf) < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_BLOCK_PREDICTION\n");
>>> +		return;
>>> +	}
>>> +	if (buf && DP_PCON_DSC_BLOCK_PRED_SUPPORT)
>>> +		pcon_dsc->blk_prediction_support = true;
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
>>> DP_PCON_DSC_ENC_COLOR_FMT_CAP, &buf) < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_ENC_COLOR_FMT_CAP\n");
>>> +		return;
>>> +	}
>>> +	pcon_dsc->color_fmt_mask = buf;
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
>>> DP_PCON_DSC_ENC_COLOR_DEPTH_CAP, &buf) < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_ENC_COLOR_DEPTH_CAP\n");
>>> +		return;
>>> +	}
>>> +	pcon_dsc->color_depth_mask = buf;
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux,
>>> DP_PCON_DSC_MAX_SLICE_WIDTH, &buf) < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_MAX_SLICE_WIDTH\n");
>>> +		return;
>>> +	}
>>> +	pcon_dsc->max_slice_width = buf;;
>>> +
>>> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BPP_INCR, &buf)
>>> < 0) {
>>> +		drm_err(&i915->drm, "Failed to read
>>> DP_PCON_DSC_BPP_INCR\n");
>>> +		return;
>>> +	}
>>> +	switch(buf & DP_PCON_DSC_BPP_INCR_MASK) {
>>> +	case DP_PCON_DSC_ONE_16TH_BPP:
>>> +		pcon_dsc->bpp_precision_incr = 16;
>>> +		break;
>>> +	case DP_PCON_DSC_ONE_8TH_BPP:
>>> +		pcon_dsc->bpp_precision_incr = 8;
>>> +		break;
>>> +	case DP_PCON_DSC_ONE_4TH_BPP:
>>> +		pcon_dsc->bpp_precision_incr = 4;
>>> +		break;
>>> +	case DP_PCON_DSC_ONE_HALF_BPP:
>>> +		pcon_dsc->bpp_precision_incr = 2;
>>> +		break;
>>> +	case DP_PCON_DSC_ONE_BPP:
>>> +		pcon_dsc->bpp_precision_incr = 1;
>>> +		break;
>>> +	default :
>>> +		pcon_dsc->bpp_precision_incr = 0;
>>> +	}
>>> +}
>>> +
>>>   static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp)  {
>>>   	int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps; @@ -
>>> 6659,6 +6835,8 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
>>>   		    intel_dp->dfp.max_tmds_clock,
>>>   		    intel_dp->dfp.pcon_max_frl,
>>>   		    intel_dp->dfp.sink_max_frl);
>>> +
>>> +	intel_dp_get_pcon_dsc_cap(intel_dp);
>>>   }
>>>
>>>   static void
>>> --
>>> 2.17.1
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